JP2005030977A - Phase difference measuring apparatus, phase difference measurement method, and testing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems, wherein a circuit does not operate normally when the phase difference between two signals becomes close to 0° or 180° since a D-type flip-flip circuit requires setup time and hold time when polarity is determined by using the D-type flip-flop circuit. <P>SOLUTION: When the phase difference between two input signals 1, 2 is measured, the input signals 1, 2 are delayed by the same delay time each by delay circuits 13, 14 having the same characteristics, and the absolute value of the phase difference between a signal (e) after the delay and the other signal (d) before the delay is detected by an absolute value phase difference detection circuit 16. The absolute value of the phase difference between one signal (c) before the delay and the other signal (f) after the delay is detected by an absolute value phase difference detection circuit 17, the detection output voltages (h), (i) are compared by a voltage comparison circuit 18, and the polarity of the phase difference information detected by the absolute value phase difference detection circuit 15 is set on the basis of a comparison result (j). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a phase difference measuring apparatus, a phase difference measuring method, and a test apparatus, and more particularly to a phase difference measuring apparatus that measures a phase difference between two input signals (hereinafter simply referred to as “between two input signals”). The present invention relates to a phase difference measuring method and a test apparatus using the phase difference measuring apparatus.

  In quality inspection of communication LSIs and the like, it is desired that the phase difference between two high-speed signals can be measured stably and accurately. A known inspection apparatus using an IC tester or the like employs a counting method using an internal reference clock, and therefore has a limit on the frequency of the internal reference clock. Therefore, when measuring the time difference corresponding to the phase difference between the two signals, the limit is about 20 to 30 ns, and the phase difference between the two high-speed signals cannot be measured with high accuracy.

  Therefore, in order to increase the resolution of the measurement time, a time difference voltage conversion method is generally employed. Hereinafter, a conventional example of the time difference voltage conversion type phase difference measuring apparatus will be described with reference to FIG.

  The phase difference measuring apparatus according to this conventional example includes voltage comparison circuits 101 and 102 for waveform shaping of two input signals 1 and 2 having a constant frequency, and two signals shaped by the voltage comparison circuits 101 and 102, respectively. The phase difference detection circuit 103 detects the phase difference and converts the voltage. The phase difference detection circuit 103 includes a phase comparison circuit 104 and an integration circuit 105. As the phase comparison circuit 104, a circuit composed of a waveform shaping circuit 111 and an RS flip-flop circuit 112 is used as shown in FIG.

  The circuit operation of the phase difference measuring apparatus having the above configuration will be described with reference to the timing chart of FIG.

  As shown in FIG. 12, the phase comparison circuit 104 starts from the rising edge of its output (output of the RS flip-flop circuit 112; QY) output of the voltage comparison circuit 101 (input of the waveform shaping circuit 111; Z1). It is configured to be in a high level (hereinafter referred to as “H” level) for a period until the rising edge of the output 102 (input of the waveform shaping circuit; Z2). Here, the period during which the output QY of the phase comparison circuit 104 is at the “H” level is represented as W.

As the overall operation of the phase difference measuring apparatus, the output QY of the phase comparison circuit 104 is integrated by the integration circuit 105, the voltage is measured, and the phase difference obtained by converting the result is obtained. For example, it is assumed that the output voltage value of the phase difference detection circuit 103 is 0 volt in a low level (hereinafter referred to as “L” level) and 5 volt in an “H” level state. The resulting phase difference θ is measured as Vm.
θ = {Vm / (5-0)} * 360 °
It is represented by

  However, when the phase difference between the two signals approaches 0 ° or 360 °, due to noise or jitter of the measurement system, and when the circuit of FIG. 11 is used as the phase comparison circuit 104, the set shown in FIG. The output state including the pulse width of the pulse S and the reset pulse R becomes unstable, and a stable output voltage cannot be obtained. That is, the phase difference measuring apparatus having the above-described configuration has a drawback in that an indeterminate region occurs near 0 ° or 360 ° as shown in FIG.

  As an improvement measure, there has conventionally been proposed a phase measuring device that realizes a circuit configuration that is less susceptible to noise by using an exclusive OR circuit (see, for example, Patent Document 1). Briefly describing this phase measuring apparatus, the absolute value of the phase difference between two input signals is detected by an exclusive OR circuit. Which phase of the two signals is advanced by this detection alone? That is, since the polarity of the phase difference between the two signals cannot be determined (hereinafter, this may be simply referred to as “polarity determination”), polarity determination is performed using a D-type flip-flop circuit, and signal processing is performed based on the determination result. Then, phase measurement is performed.

Japanese Patent Laid-Open No. 11-248765

  However, in the conventional phase measuring apparatus described in Patent Document 1, the setup time and hold time are required for the D type flip-flop circuit for polarity determination, and therefore the phase difference between the two signals is 0 ° or 180 °. There is a problem that the circuit does not operate normally at around 0 °, and there is a certain uncertainty region. Naturally, this becomes more prominent as jitter is added to the input signal or the frequency of the input signal is higher.

  The present invention has been made in view of the above problems, and its object is to provide an accurate and highly accurate phase difference over a range of 0 ° to 360 ° by stable polarity determination between two input signals. An object is to provide a phase difference measuring apparatus and a phase difference measuring method capable of measurement, and a test apparatus using the phase difference measuring apparatus.

  In order to achieve the above object, the present invention detects the absolute value of the phase difference between two input signals, delays the two input signals by the same delay time, and delays the delay with one of the delayed signals. The absolute value of the phase difference between the other signal before and the absolute value of the phase difference between the one signal before the delay and the other signal after the delay are detected. Then, the polarity of the phase difference between the two input signals is set based on the comparison result between the absolute values of the detected phase differences.

  The two input signals are respectively delayed by the same delay time, and the absolute value of the phase difference between the delayed signal and the other signal before the delay, and the one signal before the delay and the other signal after the delay By comparing the absolute value of the phase difference, which phase of the two input signals is advanced, that is, the polarity of the phase difference between the two input signals can be determined stably. Then, by setting the polarity of the phase difference based on the determination result, the phase difference between the two input signals can be measured over 0 ° to 360 °.

  According to the present invention, the polarity determination as to which phase of the two input signals is advanced is performed stably, and the polarity of the phase difference information is set based on the determination result, whereby the two input signals are The phase difference can be measured accurately and with high accuracy over 0 ° to 360 °.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration example of a phase difference measuring apparatus according to an embodiment of the present invention. In FIG. 1, the phase difference measuring apparatus according to this embodiment includes waveform shaping circuits 11 and 12 provided corresponding to two input signals 1 and 2 respectively input from input terminals IN1 and IN2, and the same delay time. Delay circuits 13 and 14 having the same characteristics, three absolute value phase difference detection circuits 15, 16 and 17, a voltage comparison circuit 16, and a polarity selection circuit 19.

  In this phase difference measuring apparatus, the waveform shaping circuits 11 and 12 are configured by, for example, a comparator that operates as a zero crossing detector, and shape the input signals (a) and (b) to be measured into square waves. . The delay circuits 13 and 14 delay the signals (c) and (d) after waveform shaping by the waveform shaping circuits 11 and 12 by the same delay time, respectively. Specifically, the delay circuit 13 delays the phase of the waveform-shaped signal (c) by θ ° (time conversion; Td). Similarly, the delay circuit 14 delays the phase of the waveform-shaped signal (d) by θ °.

  The absolute value phase difference detection circuit 15 detects the absolute value of the phase difference between the signals (c) and (d) waveform-shaped by the waveform shaping circuits 11 and 12, and is a DC voltage proportional to the absolute value of the phase difference amount. (G) is output. The absolute value phase difference detection circuit 16 detects the absolute value of the phase difference between the signal (e) delayed by the delay circuit 13 and the signal (d) waveform-shaped by the waveform shaping circuit 12, and detects the phase difference. A DC voltage (h) proportional to the absolute value of the quantity is output. The absolute value phase difference detection circuit 17 detects the absolute value of the phase difference between the signal (c) waveform-shaped by the waveform shaping circuit 11 and the signal (f) delayed by the delay circuit 14, and the amount of phase difference DC voltage (i) proportional to the absolute value of is output.

  These absolute value phase difference detection circuits 15, 16, and 17 have the same circuit configuration. Specifically, the absolute value phase difference detection circuit 15 includes, for example, an exclusive OR circuit 151 that takes the signals (c) and (d) after waveform shaping as two inputs and obtains an exclusive OR thereof, and the circuit 151. And an integrating circuit 152 that integrates the output of. The absolute value phase difference detection circuit 16 receives the delayed signal (e) and the waveform-shaped signal (d) as two inputs, takes an exclusive OR of them, and an output of the circuit 161 And an integration circuit 162 that integrates. The absolute value phase difference detection circuit 17 receives the signal (c) after waveform shaping and the signal (f) after delay as two inputs, an exclusive OR circuit 171 that takes the exclusive OR of these signals, and the output of the circuit 171 And an integration circuit 172 that integrates.

  2 shows the input signals (a) and (b) to be measured, the signals (c) and (d) after waveform shaping, and the output voltages (g) and (h) of the absolute value phase difference detection circuits 15, 16 and 17. FIG. 6 is a timing waveform diagram showing each waveform of () and (i). In the absolute value phase difference detection circuits 15, 16, and 17, when a general CMOS gate is used as the exclusive OR circuits 151, 161, and 171 and the power supply voltage Vdd is 5 volts, the absolute value phase difference detection circuit 15, The output voltages (g), (h), (i) of 16, 17 are such that the phase difference between the input signals (a), (b) is 0 volts at 0 ° and 360 °, 5 volts at 180 °, It becomes 2.5 volts at 90 ° and 270 °. That is, the output voltages (g), (h), (i) are given by the calculation formula (2θ / 360 °) × Vdd.

  The absolute value phase difference detection circuits 15, 16, and 17 have a circuit configuration in which the phase difference between the input signals (a) and (b) is 0 °, the phase is delayed by the same amount with respect to the input, or When advanced, the same output voltage is obtained after integration. This is shown in FIG. Similarly, when the phase difference between the input signals (a) and (b) is 180 °, if the phase is delayed or advanced by the same amount with respect to the input, the same output voltage is obtained after integration (not shown). )

  The voltage comparison circuit 18 compares the output voltage (h) of the absolute value phase difference detection circuit 16 with the output voltage (i) of the absolute value phase difference detection circuit 17, and the output voltage (h) is obtained from the output voltage (i). The comparison output (j) is set to “H” level when it is high, and to “L” level when it is low. The polarity selection circuit 19 is controlled by the comparison output (j) of the voltage comparison circuit 18, and when the comparison output (j) is at "H" level, the output voltage (g of the absolute value phase difference detection circuit 15 as an input) ) Is inverted, and the polarity of the output voltage (g) is non-inverted when the level is “L”.

  The voltage comparison circuit 18 and the polarity selection circuit 19 compare two output signals by comparing the output voltage (h) of the absolute value phase difference detection circuit 16 and the output voltage (i) of the absolute value phase difference detection circuit 17. Which phase is advanced, that is, the polarity of the phase difference between the input signals 1 and 2 is determined, and based on the determination result (comparison result), the output voltage of the absolute value phase difference detection circuit 15 ( The polarity setting means for setting the polarity of the phase difference information between the two input signals 1 and 2 is configured by controlling whether or not the polarity of g) is reversed. The selection output (k) of the polarity selection circuit 19 is output through the output terminal OUT as phase difference information between the two input signals 1 and 2.

  Next, the circuit operation of the phase difference measuring apparatus according to the present embodiment having the above configuration will be described with reference to the drawings.

  First, only by detecting the absolute value of the phase difference between the two input signals 1 and 2 by the absolute value phase difference detection circuit 15, it is possible to determine which input signal phase is advanced, that is, the polarity of the phase difference. Therefore, some means for determining the polarity is required. Here, attention is paid to output voltages (g), (h), and (i) of the absolute value phase difference detection circuits 15, 16, and 17 with respect to the phase difference (= input signal 1-input signal 2) shown in FIG.

  The signal (e) input to the absolute value phase difference detection circuit 16 is delayed by a fixed phase by the delay circuit 13. Therefore, the output voltage (h) of the absolute value phase difference detection circuit 16 is phase-shifted to the right by θ ° (time conversion; Td) on the time axis of FIG. The signal (f) input to the absolute value phase difference detection circuit 17 is delayed by a fixed phase by the delay circuit 14. Therefore, the output voltage (i) of the absolute value phase difference detection circuit 17 is phase-shifted to the left by θ ° on the time axis in FIG.

  Here, when viewed from the outputs of the waveform shaping circuits 11 and 12, the signal paths to the inputs of the absolute value phase difference detection circuits 16 and 17 are completely symmetric, so that the circuit configurations of the delay circuits 13 and 14 are the same. If there is, the influence of the parasitic capacitance due to the wiring etc. is the same and cancels out. As a result, the absolute value of the phase shift amount is the same in the absolute value phase difference detection circuits 16 and 17, and the output voltages (h) and (i) are also symmetric at 0 ° (360 °) and 180 °. Therefore, the cross points are exactly 0 ° (360 °) and 180 °.

  It can be seen from FIG. 4 that the magnitude relationship between the output voltages (h) and (i) of the absolute value phase difference detection circuits 16 and 17 is reversed with the cross point as the boundary. Therefore, in the voltage comparison circuit 18, the output voltage (h) of the absolute value phase difference detection circuit 16 is Vh, the output voltage (i) of the absolute value phase difference detection circuit 17 is Vi, and the absolute value phase difference detection circuits 16, 17. By taking the difference voltage Vout (= Vh−Vi) between the output voltages (h) and (i), the polarity of the phase difference between the input signals 1 and 2 can be determined. FIG. 5 shows waveforms of the differential output voltage Vout of the absolute value phase difference detection circuits 16 and 17 and the output voltage of the voltage comparison circuit 18.

  The comparison output (j) of the voltage comparison circuit 18 is given to the polarity selection circuit 19 as a control signal for performing the selection control. When the comparison output (j) of the voltage comparison circuit 18 is at “H” level, the polarity selection circuit 19 inverts the polarity of the output voltage (g) of the absolute value phase difference detection circuit 15 and outputs “L”. A phase difference of 0 ° to 360 ° can be measured by outputting the output voltage (g) with non-inverted polarity at the level. FIG. 6 shows the relationship of the output voltage (k) of the polarity selection circuit 19 with respect to the phase difference between the two input signals 1 and 2.

  As described above, when the phase difference between the two input signals 1 and 2 is measured, the input signals 1 and 2 are delayed by the same delay time by the delay circuits 13 and 14 having the same characteristics, respectively, and one of the signals after the delay is delayed. The absolute value phase difference detection circuit 16 detects the absolute value of the phase difference between (e) and the other signal (d) before the delay, and at the same time, one signal (c) before the delay and the other signal after the delay ( The absolute value of the phase difference with respect to f) is detected by the absolute value phase difference detection circuit 17, and the detected output voltages (h) and (i) are compared by the voltage comparison circuit 18. It is possible to stably determine the polarity of which phase is advanced. Therefore, by setting the polarity of the phase difference information detected by the absolute value phase difference detection circuit 15 based on the determination result (j), the phase difference between the two input signals 1 and 2 is set to 0 ° to 360 °. It is possible to measure accurately and with high accuracy.

  In particular, in the absolute value phase difference detection circuits 16 and 17, the absolute values of the phase differences detected by the exclusive OR circuits 161 and 171 are integrated by the integration circuits 162 and 172 and output as stable DC voltages (h) and (i). As a result, the voltage comparison circuit 18 can determine the polarity of the input signals 1 and 2 by comparing the stable DC voltages (h) and (i). As a result, output fluctuations are mitigated with respect to the jitter of the input signals 1 and 2, so that the polarity determination of the input signals 1 and 2 does not malfunction. When the phase difference between the two input signals 1 and 2 approaches 0 ° or 180 °, the polarity determination between the input signals 1 and 2 is performed by avoiding the generation of an indeterminate region around 0 ° or 180 °. Since it can be performed stably, accurate and highly accurate phase difference measurement is possible.

[Application example]
FIG. 7 is a block diagram showing a configuration example of a test apparatus according to the present invention to which the phase difference side measuring apparatus according to the embodiment is applied.

  In FIG. 7, the test apparatus 20 according to the present configuration example receives a signal generated by the signal generation apparatus 30 and outputs a signal under test (for example, an IC) 40 that outputs two signals 1 and 2 synchronized with the signal. Is to inspect the quality of the DUT 40 by measuring the phase difference between the signals 1 and 2 and the amplitudes of the signals 1 and 2. The test apparatus 20 includes a phase measuring unit 20A that measures the phase difference between the signals 1 and 2 and an amplitude measuring unit 20B that measures the amplitude of each of the signals 1 and 2.

  The phase measurement unit 20A includes a phase difference measurement device 21 that measures a phase difference between the signals 1 and 2 and a determination circuit 22 that determines a measurement result of the phase difference measurement device 21. The phase difference measurement device The phase difference measuring apparatus according to the embodiment described above as 21 is used. The determination circuit 22 includes two voltage comparison circuits (comparators) 221 and 222 and an AND (logical product) circuit 223.

  The voltage comparison circuit 221 generates an “H” level output voltage when the output voltage of the phase difference measuring device 21 (the output voltage of the addition circuit 17 in FIG. 1) is equal to or lower than the upper limit voltage VOH corresponding to the upper limit value of the standard. To do. The voltage comparison circuit 222 generates an “H” level output voltage when the output voltage of the phase difference measuring device 21 is equal to or higher than the lower limit voltage VOL corresponding to the lower limit value of the standard. The AND circuit 223 calculates the logical product of the output voltages of the voltage comparison circuits 221 and 222, and confirms that the test has passed when the output voltage of the phase difference measuring device 21 is within the specifications of the upper limit voltage VOH to the lower limit voltage VOL. An “H” level determination result PASS is output, and an “L” level determination result FAIL indicating that the test has failed is output when the standard is not satisfied.

  The amplitude measuring unit 20B includes two effective value detection circuits 23 and 24 and determination circuits 25 and 26 corresponding to the signals 1 and 2, respectively. The effective value detection circuits 23 and 24 detect the respective amplitudes of the signals 1 and 2 by detecting the effective values of the signals 1 and 2. The determination circuits 25 and 26 have the same configuration as the determination circuit 22, that is, a configuration including two voltage comparison circuits and an AND circuit, and pass the test when the amplitudes of the signals 1 and 2 are within the standard. “H” level determination result PASS is output, and “L” level determination result FAIL indicating that the test is failed when the standard is not satisfied.

  As described above, in the test apparatus 20 for inspecting the quality of the device under test 40 such as a communication LSI, the phase difference measurement apparatus 21 that measures the phase difference between the two signals 1 and 2 according to the embodiment described above. By using the phase difference measuring device, the phase difference measuring device can measure a phase difference of 360 ° or more stably and reliably, so that the quality inspection of the DUT 40 can be performed with high accuracy.

  By the way, as the accuracy and the number of functions of ICs increase, the test time significantly increases, resulting in an increase in test cost. An analog tester is generally considered to be time consuming, and further increase in test time in this analog tester leads to a significant decrease in productivity. Therefore, it is desired to develop a new technology that is cheap, quick, and accurate. Therefore, a test method called BOST (Built Out Self Test), in which the self-determination (Se1f-Test function) circuit is outside the DUT (Device Under Test), that is, on the device interface board (load board) of the IC tester, has attracted attention. ing.

  The major merit of this BOST is the investment reduction effect. Compared to analog testers that cost nearly 100 million yen and logic testers that cost tens of millions of yen, BOST can be realized at a cost of 1/20 to 1/100. Second is the effect of shortening the test time. This is because analog testers and analog options usually perform measurement processing of test items in series, whereas BOST allows parallel processing (multi-channel simultaneous test). Therefore, if the BOST method is used, an expensive IC tester is not required, and a high-accuracy analog test can be realized using a conventional low-cost IC tester or logic IC tester.

  FIG. 8 is a schematic diagram showing the overall configuration of a test system using the BOST technique. In FIG. 8, this test system includes a low-cost IC tester or logic IC tester (hereinafter simply referred to as “IC tester”) 51, a test head 52, and a load board 53 incorporated in the test head 52. Yes. However, the handler or prober is not shown. The IC tester 51 includes a tester main body 511, a terminal, and a keyboard 512.

  In this test system, the test apparatus 20 shown in FIG. 7 is used by being built in the load board 53. Then, the determination results of the determination circuits 22, 25, and 26 in the test apparatus 20 are sent to the IC tester 51 via a data line (not shown). Since each determination result of these determination circuits 22, 25, and 26 is PASS / FAIL information, the IC tester 51 only needs to determine the PASS / FAIL information. The IC tester 51 sets the voltage values of the upper limit voltage VOH and the lower limit voltage VOL of the determination circuits 22, 25, and 26 to the test apparatus 20 via a control data line (not shown).

  FIG. 9 shows an outline of the data processing flow in the case of measurement using the conventional measurement method (analog tester or analog option) (A) and in the case of measurement using the BOST method (B). As is apparent from FIG. 9, when measuring and determining each amplitude of the signals 1 and 2 and measuring and determining the phase difference between the signals 1 and 2, the conventional measurement method (A) Since the test takes time because serial processing is performed, in the BOST method (B), each processing can be performed in parallel (multi-channel simultaneous test), and the IC tester 51 can perform PASS / FAIL. Since only the information determination process is required, the test time can be greatly reduced.

  As described above, by applying the BOST method, it is possible to expect the effects of suppressing the investment and improving the manufacturing throughput by shortening the test time. Further, the test target is not limited to the IC, but may be a module or the like. Furthermore, the BOST-mounted load board 53 is suitable for improving the measurement performance of the IC tester 51 and for expanding the functions thereof, and can be shipped and sold independently as an external test auxiliary device.

It is a block diagram which shows the structural example of the phase difference measuring apparatus which concerns on one Embodiment of this invention. It is a timing waveform diagram showing each waveform of two input signals, a signal after waveform shaping, and an output voltage of an absolute value phase difference detection circuit. When the phase difference between two input signals is 0 °, it is a timing waveform diagram showing an output waveform after integration when the phase is delayed by the same amount or advanced with respect to the input. It is a figure which shows the relationship of the output voltage of an absolute value phase difference detection circuit with respect to the phase difference between two input signals. It is a timing waveform diagram showing the waveforms of the differential output voltage of the absolute value phase difference detection circuit and the output voltage of the voltage comparison circuit. It is a figure which shows the relationship of the output voltage of a polarity selection circuit with respect to the phase difference between two input signals. It is a block diagram which shows the structural example of the test apparatus by this invention. 1 is a schematic diagram showing an overall configuration of a test system using a BOST technique. It is a figure which shows the outline | summary of the flow of the data processing of the case of the measurement by the conventional measuring method (A), and the case of the measurement by the BOST method (B). It is a block diagram which shows the phase difference measuring apparatus of the time difference voltage conversion system which concerns on a prior art example. It is a block diagram which shows an example of a structure of a phase comparison circuit. It is a timing chart with which it uses for description of operation | movement of the phase difference measuring apparatus which concerns on a prior art example. It is a figure which shows a mode that an indefinite area | region generate | occur | produces in the phase difference measuring apparatus which concerns on a prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11, 12 ... Waveform shaping circuit, 13, 14 ... Delay circuit, 15, 16, 17 ... Absolute value phase difference detection circuit, 18 ... Voltage comparison circuit, 19 ... Polarity selection circuit, 20 ... Test apparatus, 20A ... Phase measurement part , 20B ... Amplitude measuring unit, 21 ... Phase measuring device, 22, 25,26 ... Determination circuit, 23,24 ... RMS detector, 30 ... Signal generator, 40 ... DUT, 51 ... Low cost IC tester or logic IC tester, 52 ... Test head, 53 ... Load board

Claims (5)

First detecting means for detecting an absolute value of a phase difference between two input signals;
First delay means for delaying one of the two input signals by a predetermined delay time;
Second delay means for delaying the other of the two input signals by the same delay time as the delay time of the first delay means;
Second detection means for detecting an absolute value of a phase difference between the one signal delayed by the first delay means and the other signal before being delayed by the second delay means;
Third detection means for detecting an absolute value of a phase difference between one signal before being delayed by the first delay means and the other signal delayed by the second delay means;
The absolute value of the phase difference detected by the second detection means is compared with the absolute value of the phase difference detected by the third detection means, and detected by the first detection means based on the comparison result And a polarity setting means for setting the polarity of the phase difference. The second detection means includes
A first exclusive OR circuit having two inputs of one signal delayed by the first delay means and the other signal before being delayed by the second delay means;
A first integrating circuit for integrating the output of the first exclusive OR circuit;
The third detection means includes
A second exclusive OR circuit having two inputs, one signal before being delayed by the first delay means and the other signal delayed by the second delay means;
The phase difference measuring apparatus according to claim 1, further comprising: a second integration circuit that integrates an output of the second exclusive OR circuit. A first step of detecting an absolute value of a phase difference between two input signals;
A second step of delaying one of the two input signals by a predetermined delay time;
A third step of delaying the other of the two input signals by the same delay time as the delay time in the second step;
A fourth step of detecting an absolute value of a phase difference between the one signal delayed in the second step and the other signal before being delayed in the third step;
A fifth step of detecting an absolute value of a phase difference between the one signal before being delayed in the second step and the other signal delayed in the third step;
The absolute value of the phase difference detected in the fourth step is compared with the absolute value of the phase difference detected in the fifth step, and the phase difference information detected in the first step is compared based on the comparison result. A phase difference measurement method comprising: a sixth step of determining polarity. The phase difference measurement method according to claim 3, wherein in the fourth and fifth steps, the absolute value of the detected phase difference is further integrated. A phase difference measuring device for measuring a phase difference between two input signals;
A test apparatus comprising: a determination circuit that determines whether the phase difference is vacant within a predetermined range based on a measurement result of the phase difference measurement apparatus;
The phase difference measuring device includes:
First detecting means for detecting an absolute value of a phase difference between two input signals;
First delay means for delaying one of the two input signals by a predetermined delay time;
Second delay means for delaying the other of the two input signals by the same delay time as the delay time of the first delay means;
Second detection means for detecting an absolute value of a phase difference between the one signal delayed by the first delay means and the other signal before being delayed by the second delay means;
Third detection means for detecting an absolute value of a phase difference between one signal before being delayed by the first delay means and the other signal delayed by the second delay means;
The absolute value of the phase difference detected by the second detection means is compared with the absolute value of the phase difference detected by the third detection means, and detected by the first detection means based on the comparison result And a polarity setting means for setting the polarity of the phase difference.

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