JP2013034119A - Phase comparison device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase comparison device that extracts an integral value without waiting for a step response convergence time, and computes a phase difference in response to the extracted integral value even if frequencies of input signals are unknown.SOLUTION: A frequency divider 4 divides the frequency of an input signal in two, an integrator 5 integrates pulses generated by an exclusive OR circuit 3 for the period set by the frequency divider 4, a reference integrator 7 integrates a reference signal of a known fixed level for the period set by the frequency divider 4, and a signal processing section 10 computes a phase difference in accordance with integral values by the integrator 5 and the reference integrator 7. In the configuration, the use of the formation of a sync filter characteristic having null points at a frequency that is an integral multiple of half the frequency of the input signal dispenses with a low pass filter to allow integral values to be extracted without waiting for a step response convergence time. Even if frequencies of two input signals are unknown, a phase difference can be computed between the two input signals.

Description

  The present invention relates to a phase comparison device that calculates a phase difference between two input signals.

  As a conventional phase comparator, an exclusive ethical sum circuit that generates a pulse corresponding to the phase difference between two input signals, and a signal that is connected to the subsequent stage of the exclusive ethical sum circuit and corresponds to the phase difference between the two input signals Is provided with a low-pass filter that outputs (FIG. 1 of Patent Document 1 below).

  Also, as a conventional phase comparator, an integrator that starts charging in response to the rising of one of the two input signals and stops charging in response to the rising of the other input signal; There is a sample hold circuit that extracts an integrated voltage after stopping charging and outputs the integrated voltage as time information of a rise time difference between two input signals (FIG. 5 of Patent Document 1 below).

JP 59-161119 A

Since the conventional phase comparator is configured as described above, it has the following problems.
In the phase comparator in which a low pass filter is connected to the subsequent stage of the exclusive ethical sum circuit, the output signal of the exclusive ethical sum circuit rises in a step response when the two input signals are pulse waves. Therefore, in order for the output signal of the low-pass filter to become stable, it is necessary to wait for the time that the step response due to the time constant of the low-pass filter converges. The time will be longer. In addition, if the step response time becomes too long, the output signal falls and there is a problem that phase comparison cannot be performed.

A phase comparator having a sample-and-hold circuit connected to the subsequent stage of the integrator outputs an integrated voltage as time information of a rise time difference between two input signals. Therefore, if the frequencies of the two input signals are known, the phase difference between the two input signals can be calculated from the time information of the rise time difference and the known frequency, but the frequencies of the two input signals are known. If the frequency does not change or the frequency fluctuates, there is a problem that the phase difference between the two input signals cannot be calculated.
In addition, since the start and stop of charging of the integrator are controlled according to the rise of two different input signals, a delay at the start of charging and a delay at the time of stopping charging are individually generated and extracted. There is a problem that the error fluctuation of the integral value becomes large.

  The present invention has been made to solve the above-described problems, and extracts an integrated value without having to wait for the step response convergence time, and also extracts an integrated value even if the frequency of the input signal is not known. It is an object of the present invention to obtain a phase comparison device that calculates a phase difference according to the above and further has a small error fluctuation of an integral value.

  The phase comparison apparatus according to the present invention sets a phase comparison unit that generates a pulse corresponding to a phase difference between a first input signal and a second input signal, and a time N times the period of the first input signal. Time setting means, first integration means for integrating the pulses generated by the phase comparison means for the time set by the time setting means, and integration for a known constant level reference signal for the time set by the time setting means The second integration means, the first integration value by the first integration means and the second integration value by the second integration means are extracted, and the position is determined according to the first integration value and the second integration value. Phase difference calculating means for calculating the phase difference is provided.

  According to the present invention, the time setting means sets a time N times the period of the first input signal, and the first integration means sets the pulses generated by the phase comparison means for the time set by the time setting means. Since it is configured to integrate, a simple configuration utilizing the fact that a sync filter characteristic having a null point is formed at a frequency that is an integer multiple of the frequency of 1 / N times the frequency of the first input signal. Thus, high-frequency filtering can be performed in a short time, a low-pass filter is not required, and an integrated value can be extracted without having to wait for the step response convergence time.

  The first integration means integrates the pulse generated by the phase comparison means for the time set by the time setting means, and the second integration means sets a known constant level reference signal by the time setting means. Since the time difference is integrated, the phase difference calculating means is configured to calculate the phase difference according to the first integrated value by the first integrating means and the second integrated value by the second integrating means, so two inputs Even when the frequency of the signal is not known or the frequency fluctuates, the phase difference between the two input signals can be calculated.

  Further, the phase comparison unit is configured to generate a pulse corresponding to the phase difference between the first input signal and the second input signal, and the first integration unit is configured to integrate the pulse generated by the phase comparison unit. Therefore, the first integration means only needs to integrate the pulse generated by the phase comparison means, and there is an effect that the error fluctuation of the extracted integrated value can be reduced.

It is a block diagram which shows the phase comparison apparatus by Embodiment 1 of this invention. It is a timing chart which shows operation | movement of the phase comparison apparatus by Embodiment 1 of this invention. It is a characteristic view which shows the output signal spectrum of the phase comparison apparatus by Embodiment 1 of this invention. It is a characteristic view which shows the phase comparison output characteristic of the phase comparison apparatus by Embodiment 1 of this invention. It is a block diagram which shows the phase comparison apparatus by Embodiment 2 of this invention. It is a timing chart which shows operation | movement of the phase comparison apparatus by Embodiment 2 of this invention.

Embodiment 1 FIG.
1 is a block diagram showing a phase comparison apparatus according to Embodiment 1 of the present invention.
In FIG. 1, an exclusive OR circuit (phase comparison means, phase comparison circuit) 3 takes an exclusive OR of input signals from input signal terminals 1 and 2.
The frequency divider (time setting means) 4 divides the frequency of the input signal from the input signal terminal 1 by two.

The integrator (first integrating means) 5 integrates the pulse generated by the exclusive OR circuit 3 by the period divided by 2 by the frequency divider 4.
The reference signal source 6 generates a known constant level reference signal.
The reference integrator (second integration means) 7 integrates the reference signal generated by the reference signal source 6 by the period divided by 2 by the frequency divider 4.

The sample hold circuit (phase difference calculation means) 8 samples and holds the integrated value after being stopped by the integrator 5.
The sample hold circuit (phase difference calculation means) 9 samples and holds the integrated value after being stopped by the reference integrator 7.
The signal processing unit (phase difference calculation means) 10 calculates a phase difference according to the integrated value sampled and held by the sample hold circuit 8 and the integrated value sampled and held by the sample hold circuit 9.

  In the example of FIG. 1, the exclusive OR circuit 3, the frequency divider 4, the integrator 5, the reference signal source 6, the reference integrator 7, the sample and hold circuits 8 and 9, It is assumed that the signal processing unit 10 is configured by hardware such as a semiconductor circuit board. However, the signal processing unit 10 may be configured by software such as a semiconductor circuit board. In this case, a program in which processing contents of the signal processing unit 10 are described is stored in a memory, and a microcomputer CPU The functions of the signal processing unit 10 are realized by executing a program stored in the memory.

Next, the operation will be described.
FIG. 2 is a timing chart showing the operation of the phase comparator.
Hereinafter, a description will be given with reference to FIGS. 1 and 2.

  Two input signals from the input signal terminal 1 and the input signal terminal 2 are subjected to phase comparison in the exclusive OR circuit 3. The exclusive OR circuit 3 takes an exclusive OR of the two input signals and generates a phase difference pulse at the rising edge and the falling edge of the input signal.

  The input signal from the input signal terminal 1 is also supplied to the frequency divider 4, and the frequency divider 4 divides the frequency of the input signal from the input signal terminal 1 by two. Therefore, the frequency divider 4 generates a signal having a cycle twice that of the input signal from the input signal terminal 1.

  The pulse generated by the exclusive OR circuit 3 is supplied to the integrator 5. The integrator 5 starts integration at the rising edge of the pulse output from the frequency divider 4, integrates the pulse generated by the exclusive OR circuit 3, and stops the integration after the period divided by two.

  Further, the reference signal source 6 generates a reference signal of a certain level and is supplied to the reference integrator 7. The reference integrator 7 starts integration at the rising edge of the pulse output from the frequency divider 4, integrates a constant level reference signal generated by the reference signal source 6, and stops the integration after a period divided by two. To do.

  The sample hold circuit 8 samples and holds the integration value after being stopped by the integrator 5, and the sample hold circuit 9 samples and holds the integration value after being stopped by the reference integrator 7. For example, after the integration of the integrator 5 and the reference integrator 7 is stopped, the integrated values (integrated voltages) of the integrator 5 and the reference integrator 7 are sampled and held by an A / D converter or the like.

The integrated values sampled and held by the sample hold circuits 8 and 9 are supplied to the signal processing unit 10. The signal processing unit 10 calculates a phase difference according to each integrated value sampled and held.
In the signal processing unit 10, for example, the phase difference is calculated as follows according to each integral value.
If the high level of the output of the exclusive OR circuit 3 and the output level of the reference signal source 6 are the same, the phase difference is obtained by setting the integration value of the sample hold circuit 8 to Vp and the integration value of the sample hold circuit 9 to Vr. φ can be calculated by the following equation (1).

Thereafter, the values held in the integrator 5, the reference integrator 7, and the sample hold circuits 8 and 9 are reset.
Similarly, in the next phase difference calculation, the integrator 5 and the reference integrator 7 start the integration at the rising edge of the pulse output from the frequency divider 4, and stop the integration after the period divided by two. The signal processing unit 10 calculates the phase difference according to each integral value.

Next, the principle that the configuration of the first embodiment has an effect will be described.
1 and 2, the exclusive OR circuit 3 takes an exclusive OR of two input signals and generates a pulse corresponding to the phase difference at the rise and fall of the input signals 1 and 2.
The pulse corresponding to this phase difference has harmonic components of the input signals 1 and 2, and the 0th-order component corresponds to the input signals 1 and 2.

Therefore, the pulse corresponding to the phase difference has a spectrum of a direct current component 0, a fundamental frequency component fin, and a harmonic component 2fin of the fundamental frequency component, as shown by a solid line and a broken line in FIG.
If sampling is performed without any processing, the output level fluctuates depending on the sampling timing, and the measured value does not stabilize due to the signal component generated by itself, and looks like noise.

  Therefore, as shown in FIG. 1 of Patent Document 1, it is common to suppress the harmonics using a low-pass filter so that phase difference information represented by a DC voltage can be accurately sampled. However, since the output signal of the exclusive OR circuit 3 rises in a step response in the low pass filter, it is necessary to wait for the time that the step response due to the time constant of the low pass filter converges. There is a drawback that it is not possible to perform proper sampling.

In the first embodiment, by performing interval integration with a period twice as long as the period of the input frequency fin of the input signal 1, a sync filter characteristic having a null point can be formed at the frequency of fin / 2. And suppresses harmonic components of fin, 2fin,...
Therefore, high-frequency filtering can be performed in a short time with a simple configuration, a low-pass filter is not required, and an integrated value can be extracted without having to wait for the step response convergence time.

  FIG. 4 shows the phase comparison output characteristics of the phase comparison apparatus according to the first embodiment. The output level of the reference integrator 7 is full scale, and has linear output characteristics in the interval of π radians with respect to the phase.

  According to the first embodiment, the frequency divider 4 divides the frequency of the input signal by 2, and the integrator 5 divides the pulse generated by the exclusive OR circuit 3 into the period set by the frequency divider 4. Since it is configured to integrate, the fact that a sync filter characteristic having a null point is formed at a frequency that is an integral multiple of a frequency that is ½ times the frequency of the input signal is used for a short time with a simple configuration. Thus, high-frequency filtering can be performed, a low-pass filter is not required, and an integral value can be extracted without having to wait for the step response convergence time.

  Further, the integrator 5 integrates the pulse generated by the exclusive OR circuit 3 for the period set by the frequency divider 4, and the reference integrator 7 sets a known constant level of the reference signal by the frequency divider 4. Since the signal processing unit 10 is configured to calculate the phase difference according to the integration value by the integrator 5 and the reference integrator 7, the frequencies of the two input signals are not known, Even if fluctuates, the phase difference between the two input signals can be calculated.

  Further, since the exclusive OR circuit 3 generates a pulse corresponding to the phase difference between the two input signals, and the integrator 5 integrates the pulse generated by the exclusive OR circuit 3, the integrator 5 only needs to integrate the pulses generated by the exclusive OR circuit 3, and the error fluctuation of the extracted integrated value can be reduced.

  In addition, according to Embodiment 1 described above, the exclusive OR circuit 3 is applied as the phase comparison circuit, but an analog multiplier or an RS flip-flop may be applied as the phase comparison circuit. Only the phase comparison output characteristic of each phase comparison circuit has the same operation.

  Further, according to the first embodiment, the frequency divider 4 divides the frequency of the input signal from the input signal terminal 1 by 2, but it divides the frequency by N (N is an arbitrary natural number). It is also possible to suppress the harmonic components of fin, 2fin,... Using the fact that a sync filter characteristic having a null point is formed at a frequency that is an integral multiple of the frequency of fin / N. can do.

Embodiment 2. FIG.
FIG. 5 is a block diagram showing a phase comparison apparatus according to Embodiment 2 of the present invention.
In FIG. 5, a comparator (comparison means) 11 compares the integration value obtained by the reference integrator 7 with a preset threshold value, and generates a trigger signal when the integration value exceeds the threshold value.
The counter (time setting means) 12 counts the wave number of the input signal from the input signal terminal 1, and when the trigger signal is generated by the comparator 11, the counter ends at the edge of the next wave when the trigger signal is generated. To do.
Other configurations are the same as those shown in FIG. 1 except that the frequency divider 4 is omitted.

Next, the operation will be described.
FIG. 6 is a timing chart showing the operation of the phase comparator.
Hereinafter, a description will be given with reference to FIGS. 5 and 6.

  Two input signals from the input signal terminal 1 and the input signal terminal 2 are subjected to phase comparison in the exclusive OR circuit 3. The exclusive OR circuit 3 takes an exclusive OR of the two input signals and generates a phase difference pulse at the rising edge and the falling edge of the input signal.

  The input signal from the input signal terminal 1 is also supplied to the counter 12, and the counter 12 counts the wave number of the input signal from the input signal terminal 1.

  The pulse generated by the exclusive OR circuit 3 is supplied to the integrator 5. The integrator 5 starts integration when the counter 12 starts counting, and integrates the pulse generated by the exclusive OR circuit 3.

  Further, the reference signal source 6 generates a reference signal of a certain level and is supplied to the reference integrator 7. The reference integrator 7 starts integration when the counter 12 starts counting, and integrates a constant level reference signal generated by the reference signal source 6.

The comparator 11 has a threshold value set in advance, compares the integrated value obtained by the reference integrator 7 with a preset threshold value, and generates a trigger signal when the integrated value exceeds the threshold value.
When the trigger signal is generated by the comparator 11, the counter 12 finishes counting at the edge of the wave of the next input signal when the trigger signal is generated. In FIG. 6, the count is finished at count 3.
The integrator 5 and the reference integrator 7 stop the integration when the counter 12 finishes counting.

  The sample hold circuit 8 samples and holds the integration value after being stopped by the integrator 5, and the sample hold circuit 9 samples and holds the integration value after being stopped by the reference integrator 7.

  The integrated values sampled and held by the sample hold circuits 8 and 9 are supplied to the signal processing unit 10. The signal processing unit 10 calculates a phase difference according to each integrated value sampled and held. The calculation method is the same as Expression (1) in the first embodiment.

Thereafter, the values held in the integrator 5, the reference integrator 7, the sample hold circuits 8 and 9, and the counter 12 are reset.
In the next phase difference calculation, similarly, the integrator 5 and the reference integrator 7 start the integration when the counter 12 starts counting, stop the integration when the counting ends, and the signal processing unit 10 The phase difference is calculated according to the value.

Next, the principle that the configuration of the second embodiment is effective will be described.
Also in the second embodiment, a sync filter characteristic in which a null point can be formed at a frequency that is an integral multiple of the frequency of fin / 3 by performing interval integration at a cycle that is three times the cycle of the input frequency fin of the input signal 1. Is used to suppress the harmonic components of fin, 2fin,...
Therefore, high-frequency filtering can be performed in a short time with a simple configuration, a low-pass filter is not required, and an integrated value can be extracted without having to wait for the step response convergence time.

  The phase comparison output characteristic of the phase comparison apparatus according to the second embodiment is the same as that shown in FIG.

Furthermore, in the phase comparison device according to the first embodiment, when the frequency of the input signal changes greatly, the phase resolution may change greatly depending on the frequency.
This is because the output Vr is proportional to 1 / fin, so that the output Vr decreases and the phase resolution decreases as the frequency of the input signal increases.

  On the other hand, in the phase comparison apparatus according to the second embodiment, the output Vr is at least equal to or greater than the threshold value preset in the comparator 11, so that the number of counts only increases even when the frequency of the input signal increases. The output Vr can be kept substantially constant, and the phase resolution can be kept almost constant.

  According to the second embodiment, the counter 12 counts the wave number of the input signal by three, and the integrator 5 integrates the pulse generated by the exclusive OR circuit 3 for the time set by the counter 12. Therefore, by using the fact that a sync filter characteristic having a null point is formed at a frequency that is an integer multiple of the frequency of three times the frequency of the input signal, high-frequency filtering can be performed in a short time with a simple configuration. A low-pass filter is not required, and an integrated value can be extracted without having to wait for the step response convergence time.

  Further, the integrator 5 integrates the pulse generated by the exclusive OR circuit 3 for the time set by the counter 12, and the reference integrator 7 applies the known constant level reference signal for the time set by the counter 12. Since the signal processing unit 10 calculates the phase difference according to the integration value by the integrator 5 and the reference integrator 7, the frequencies of the two input signals are not known or the frequencies fluctuate. Even so, the phase difference between the two input signals can be calculated.

  Further, since the exclusive OR circuit 3 generates a pulse corresponding to the phase difference between the two input signals, and the integrator 5 integrates the pulse generated by the exclusive OR circuit 3, the integrator 5 only needs to integrate the pulses generated by the exclusive OR circuit 3, and the error fluctuation of the extracted integrated value can be reduced.

  Further, the comparator 11 compares the integration value obtained by the reference integrator 7 with a preset threshold value, and generates a trigger signal when the integration value exceeds the threshold value. The counter 12 generates a trigger signal by the comparator 11. In this case, since the count is terminated at the edge of the next wave when the trigger signal is generated, the output Vr, which is an integrated value by the reference integrator 7, is at least equal to or greater than a threshold value preset in the comparator 11. Even if the frequency of the input signal increases, the phase resolution can be kept substantially constant.

  According to the second embodiment, the comparator 11 is set with a threshold value in advance. However, the threshold value in the comparator 11 may be variably set, and the phase resolution may be variably set. Can be.

Further, according to the second embodiment, the comparator 11 and the counter 12 are provided. When the trigger signal is generated by the comparator 11, the counter 12 finishes counting at the edge of the next wave when the trigger signal is generated. I tried to do it.
However, the counter 12 counts the wave number of the input signal from the input signal terminal 1, and when counting the preset N wave number (N is an arbitrary natural number), the counter 12 ends counting at the edge of the next wave. Anyway. In this case, it is not necessary to provide the comparator 11, and the configuration can be facilitated.

  In the present invention, within the scope of the invention, a free combination of each embodiment, a modification of an arbitrary component of each embodiment, or an omission of any component in each embodiment is possible. is there.

  1, 2 input signal terminals, 3 exclusive OR circuit, 4 frequency divider, 5 integrator, 6 reference signal source, 7 reference integrator, 8, 9 sample hold circuit, 10 signal processing unit, 11 comparator, 12 counter .

Claims (5)

Phase comparison means for generating a pulse according to the phase difference between the first input signal and the second input signal;
Time setting means for setting a time N (N is an arbitrary natural number) times the period of the first input signal;
First integration means for integrating the pulse generated by the phase comparison means for the time set by the time setting means;
Second integrating means for integrating a known constant level reference signal for the time set by the time setting means;
The first integrated value by the first integrating means and the second integrated value by the second integrating means are extracted, and the phase difference is calculated according to the first integrated value and the second integrated value. A phase comparison device comprising phase difference calculation means. Comparing the integration value by the second integration means with a preset threshold value, and comprising a comparison means for generating a trigger signal when the integration value exceeds the threshold value,
The time setting means is
2. The phase comparison apparatus according to claim 1, wherein when a trigger signal is generated by the comparison means, an end time of a time N times the period of the first input signal is set. A phase comparison circuit that generates a pulse according to a phase difference between the first input signal and the second input signal;
A frequency divider that divides the frequency of the first input signal by N (N is an arbitrary natural number);
A first integrator that integrates a pulse generated by the phase comparison circuit by a period N divided by the divider;
A reference signal source for generating a reference signal of a certain level;
A second integrator for integrating the reference signal generated by the reference signal source by a period divided by N by the divider;
A first sample and hold circuit for extracting a first integrated value after being stopped by the first integrator;
A second sample and hold circuit for extracting a second integrated value after stopping by the second integrator;
A phase comparison comprising a signal processing unit for calculating a phase difference in accordance with the first integrated value extracted by the first sample and hold circuit and the second integrated value extracted by the second sample and hold circuit apparatus. A phase comparison circuit that generates a pulse according to a phase difference between the first input signal and the second input signal;
A counter that terminates counting when the wave number of the first input signal is counted N (N is an arbitrary natural number);
A first integrator that starts integration of pulses generated by the phase comparison circuit at the start of counting by the counter and stops integration at the end of counting by the counter;
A reference signal source for generating a reference signal of a certain level;
A second integrator that starts integration of the reference signal generated by the reference signal source at the start of counting by the counter and stops integration at the end of counting by the counter;
A first sample and hold circuit for extracting a first integrated value after being stopped by the first integrator;
A second sample and hold circuit for extracting a second integrated value after stopping by the second integrator;
A phase comparison comprising a signal processing unit for calculating a phase difference in accordance with the first integrated value extracted by the first sample and hold circuit and the second integrated value extracted by the second sample and hold circuit apparatus. A comparator that compares the integration value obtained by the second integration means with a preset threshold value and generates a trigger signal when the integration value exceeds the threshold value;
The above counter
5. The wave number of the first input signal is counted, and when a trigger signal is generated by the comparator, the counting ends at the edge of the next wave when the trigger signal is generated. Phase comparator.

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