JP6740795B2 - Speed control system - Google Patents

Description

The present invention relates to a speed control system for controlling the rotation speed of a rotating machine (motor, generator, etc.) such as a variable speed device, and relates to a PI control method used for speed feedback control.

The absolute type encoder has a high resolution, and the current position information can be periodically obtained by serial transmission or the like, so that an accurate rotation phase or speed can be detected. However, in an environment where the environment is poor, a pulse encoder having a configuration in which a gear-shaped metal and a sensor using the principle of magnetism or high frequency are combined is used. Some encoders for servo applications have high resolution of about several thousand pulses (2 to the power of 10 to 12), but if there are problems such as environmental resistance and mechanical vibration, (6 of 2 An encoder having a resolution as low as (~8th power) may be used. The present invention aims to improve the speed control performance by changing the PI control method on the assumption that such a low-resolution pulse encoder is used.

There are various types of PI control such as position type and speed type, but speed type PI control is often used in speed control. FIG. 1 shows the velocity type PI control in a calculation block diagram of a discrete system of sample value control. This FIG. 1 is referred to as Conventional Example 1. It consists of the following elements:

(1) Input: speed command value ω_ref, speed detection value ω_det by encoder
(2) Proportional gain: Kps
(3) Integration time constant: Tis
(4) Sample period (time): dT
(5) Sampler, delay element of sample time: Z ^-1
(6) Torque command output: τ_pio
(7) Limiter value of torque command output: ±τ_lim
In order to execute control by the digital control arithmetic unit, it is necessary to handle in a sample value system (discrete system), and this arithmetic operation starts the arithmetic processing by an interrupt signal (sample timing) for speed control. In order to detect the speed from the pulse encoder signal, first measure the value of the pulse counter and its pulse generation time with a circuit implemented in hardware, etc. The detection information is read from the circuit. As a process, after first performing a speed detection calculation, a speed control calculation as shown in FIG. 1 is executed to output a torque command.

As a prior art document relating to speed detection calculation, there is Patent Document 1, and this principle is described in Non-Patent Document 1.

In FIG. 1, since speed detection is executed at interrupt (sample) timing, it is clearly shown that the timing is limited by the sampler (latch circuit) (Z ⁻¹ ) operating at the interrupt cycle (sample cycle). In the samplers 1a and 1b of the input section, the speed command value ω_ref and the speed detection value ω_det after speed calculation are latched. In the PI control, in the proportional term, the subtractor 2a subtracts the detected speed value from the speed command value, and the difference is multiplied by the proportional gain Kps to obtain the proportional term torque command τ_p. In the integral term, first, in the coefficient unit 3, the torque command τ_p of the proportional term is multiplied by a coefficient (dT/Tis) corresponding to the integration time constant, and the integral term corresponding to the increment of the torque command of the integral term in the sampling period. Calculate the Δτ_i component.

In the velocity PI control, the time difference of the τ_p term (Δτ_p) by the sampler 1c and the subtractor 2b and the integral term Δτ_i are added by the adder 4a, and the previous torque command output τ_pio delayed by the sampler 1d is added. The torque command output (τ_p+τ_i) to be updated is calculated by the addition by the adder 4b. However, since it is necessary to limit the torque limiter value (±τ_lim), the value limited by the torque limiter (torque limiter) 5 becomes the final torque command output τ_pio.

This is a basic configuration example of the speed PI control, which has been already described in many documents.

When the configuration of FIG. 1 is further developed as shown in FIGS. 2A, 2B, and 2C, feedback is provided to the integral term during the limiter operation for the “positional PI control configuration” as shown in FIG. It is also possible to have a configuration in which a function for

In FIG. 2A, the respective inputs (feedback amount) of the samplers 1c and 1d in FIG. 1 are put together by the subtractor 2c and the sampler 1e, and the addition destination (adder 4a) of the sampler 1e is moved to the integral term. The deviation output of the subtractor 2c is the torque correction amount (feedback amount) Δτ_fb.

In FIG. 2B, only the layout is changed in the same configuration as that of FIG.

In FIG. 2(c), the addition unit (adder 4b) of τ_p and τ_i in FIG. 2(b) is moved before the point A in FIG. 2(b). Since it crosses the branch of the point A, an adder 4c for adding τ_i and the torque correction amount Δτ_fb is additionally provided for equalization.

In FIG. 3, the addition destination of Δτ_fb in FIG. 2C is moved to the previous adder 4a, and the feedback unit of Δτ_fb and the integrating unit that outputs τ_i are separated. Therefore, the adder 4d and the sampler 1f are provided between the adders 4a and 4b in FIG. 2(c).

Although FIG. 3 is equivalent in function to FIG. 1, the form of the configuration is different, and therefore this is referred to as Conventional Example 2. In FIG. 1, the component of the integral term did not appear explicitly, but in FIG. 3, the component of the integral term (time integration of the difference between the speed command value and the speed detection value) is clearly shown. This can be said to be the difference from FIG. However, they are functionally the same and output the same operation result if they have the same input.

Here, as a conventional example having a similar purpose to the present invention, control is performed using a speed detection device for obtaining the speed detection value ω_det by the encoder in FIGS. 1 and 3 and the speed detection value obtained by the speed detection device. Examples of the speed control system to be performed are shown in FIGS.

The configuration of FIG. 15 showing the speed detecting device is roughly divided into a “digital detection circuit” on the left side and a “CPU operation” on the right side. The part of the digital detection circuit is basically the same as the detection circuit of Patent Document 1 or Non-Patent Document 1.

A pulse encoder 50 detects the rotation angle of the rotating machine, and generates a pulse signal according to the phase of a rotating body such as a motor. Although a two-phase pulse signal is output, the description will be simplified here to a one-phase pulse signal.

Reference numeral 51 is a waveform shaping circuit that shapes the output pulse from the pulse encoder 50, detects the rising edge and the falling edge of the output pulse of the pulse encoder 50, and outputs the UP/DOWN signal (Edg_up/ Edg_dw).

Reference numeral 52 is an OR circuit that outputs the pulse generation signal Edg by performing an OR operation on the UP/DOWN signal of the counter output from the waveform shaping circuit 51. Hereinafter, the “pulse generation signal” may be simply used as “pulse”.

Reference numeral 53 denotes a pulse phase up/down counter that counts up/down by the rising edge and the falling edge of the pulse detected by the waveform shaping circuit 51 and outputs the count value as a pulse phase value (θpp). The counter value θpp is incremented (Up)/decremented (Dw) by the signal (Edg_up/Edg_dw).

Reference numeral 54 is a timer circuit that generates a reference time for measuring the pulse generation time, counts the reference clock of the digital circuit, and outputs time data t. The timer circuit 54 also has a function of outputting an interrupt signal Smpl(m) for each sample period according to the sample period setting input from the CPU via the D-type flip-flop 55.

Here, (m) of Smpl(m) is an identifier for indicating the timing of occurrence, and the specific value of m is expressed as "m1, m2, m3... ". A pulse generation time measurement circuit 56 stores and holds the time data t output from the timer circuit 54 when the pulse generation signal Edg is generated, and outputs it as the pulse generation time tpp. The output of the OR circuit 52 (Edg ) Is used as an enable signal, and a latch circuit (DEN-ff) is used.

57 is set by the pulse generation signal Edg from the OR circuit 52 and reset by the interrupt signal Smpl(m) from the timer circuit 54, and a pulse edge (Edg) is generated during the generation period of the interrupt signal. It is a flip-flop circuit that detects whether or not. The flip-flop circuit 57 is a set-priority SR-flip-flop (SRff) circuit, and is "0" if a pulse edge (Edg) has not occurred between the interrupt signals Smpl(m), and if it has occurred. The pulse presence flag of "1" is output and output to the read buffer 58 in the next stage (strictly speaking, data transfer is performed when an EN (enable) signal is generated on the receiving side).

As described above, the interrupt signal Smpl(m) is not only used by the flip-flop circuit 57 for determining whether the speed detection calculation is possible/impossible, but also the read buffer 58 including a multistage buffer described later. It is also used to control the data transfer of. Therefore, the three types of “pulse presence/absence flag, pulse phase value θpp, and pulse generation time tpp” are updated at the same time.

The read buffer 58 uses the interrupt signal Smpl(m) from the timer circuit 54 as an enable signal, the pulse phase value θpp sent from the pulse phase up/down counter 53, and the pulse sent from the pulse generation time measuring circuit 56. It holds the occurrence time tpp and the pulse presence/absence flag (pulse presence/absence signal) sent from the flip-flop circuit 57, respectively.

This read buffer 58 stores a latch circuit 58a to store three instantaneous values of a "pulse presence/absence flag", a "pulse phase value θpp", and a "pulse generation time tpp" at the generation time of the interrupt signal Smpl(m). 58c (Dff1 to Dff3 in the figure).

The output sides of the latch circuits 58a to 58c are read as measured values from the CPU or the like, and the interrupt signal Smpl( is set so that the values do not change and the simultaneity is lost during a period in which a plurality of data are accessed by the bus. At the timing of occurrence of m), the values are latched at the same time, and the values are held in other periods.

In addition, the waveform shaping circuit 51, the OR circuit 52, the pulse phase up/down counter 53, the timer circuit 54, the D-type flip-flop 55, the pulse generation time measuring circuit 56, the flip-flop circuit 57, and the read buffer 58, the pulse information acquisition unit. Is composed of.

Reference numeral 61 is a pulse phase buffer (multistage buffer; Buff2) for reading and storing the register value (pulse phase value θpp) of the latch circuit 58b (Dff2), and 62 is the register value (pulse generation) of the latch circuit 58c (Dff3). It is a pulse time buffer (multi-stage buffer; Buff3) that reads and stores (time tpp).

Reference numeral 63 sets a selection signal (Sel) for selecting the pulse information (pulse phase value θpp, pulse generation time tpp) acquired a plurality of sample periods before and stored in the pulse phase buffer 61 and the pulse time buffer 62. It is a speed difference data selection circuit (selection signal setting unit). The selection signal Sel is, specifically, a value of (m) which is an identifier of the interrupt signal Smpl(m) output for each sampling period, and is set to a value corresponding to a plurality of sampling periods before.

Reference numeral 64 denotes a previous value selection selector (Select2) (past information) for selecting (past) pulse phase information before a plurality of sample periods indicated by the selection signal Sel from the pulse phase information stored in the pulse phase buffer 61. Selection section).

Reference numeral 65 designates a previous value selection selector (Select3) (past information) for selecting (past) pulse time information of a plurality of sample periods before the pulse time information stored in the pulse time buffer 62, which is indicated by the selection signal Sel. Selection section).

The pulse phase buffer 61 and the pulse time buffer 62 store the latest pulse information in the first-stage buffer and the past pulse information in the second-stage buffer, for example, in Patent Document 1, and the two Although the speed detection value is calculated based on the information of FIG. 16, in FIG. 15, as shown in FIG. 16, the speed detection value is expanded to a stack memory (multistage buffer) that performs a multistage FIFO (first in first out) operation. There is.

In FIG. 16, reference numeral 71 is an AND circuit that calculates the logical product of the interrupt signal Smpl(m) (output of the timer circuit 54) and the pulse presence/absence signal (output of the latch circuit Dff1) in FIG.

Reference numeral 72 is a multi-stage buffer that stores pulse phase information and pulse generation time information (detection data) read from the read buffer 58 in FIG. 15, and is a latch circuit 72-0 (Dff0) (latest) that stores the latest information. The information storage buffer) and n-stage (n is an integer) latch circuits 72-1 to 72-5 (Dff1 to Dff5) (past information storage buffer) that store past information.

Note that in FIG. 16, the n-stage latch circuit that is the buffer for storing past information is configured as five, but it may be configured by a plurality of other stages. Further, although Dff1 to Dff3 of the latch circuits 58a to 58c of the reading buffer 58 of FIG. 15 and Dff1 to Dff3 of the latch circuits 72-1 to 72-3 of FIG. Are different circuits.

The output of the latch circuit 58b (pulse phase information) or the output of the latch circuit 58c (pulse time information) of the read buffer 58 is input as detection data to the D terminal of the latch circuit 72-0.

The Q output of the latch circuit 72-0 is input to the D terminal of the latch circuit 72-1, the Q output of the latch circuit 72-1 is input to the D terminal of the latch circuit 72-2, and the Q output of the latch circuit 72-2. Is input to the D terminal of the latch circuit 72-3, the Q output of the latch circuit 72-3 is input to the D terminal of the latch circuit 72-4, and the Q output of the latch circuit 72-4 is the D terminal of the latch circuit 72-5. It is input to the terminal.

Each of the latch circuits 72-0 to 72-5 uses the output of the AND circuit 71, which is the logical product of the interrupt signal and the pulse presence/absence signal, as an enable signal, and writes read data and buffers (latch circuits 72-0 to 72-0. Data movement (between 72 and 5) is executed by the interrupt process.

Since the AND signal of the interrupt signal and the pulse presence/absence signal is used as the enable signal in this manner, each buffer (latch circuits 72-0 to 72-5) is provided only when the pulse presence/absence signal (pulse presence/absence flag) "generates a pulse". ) Is operated and the past value can be held when there is no pulse. Since it has a data transfer limiting function by such a pulse presence/absence signal, it can cope even if the rotation speed is lowered and the pulse generation period becomes longer than the interrupt signal period to enter the “pulse pause” state.

Reference numeral 73 in FIG. 16 is a previous value selection selector that realizes the function of the previous value selection selectors 64 and 65 (Select2, Select3) in FIG. 15, and is each Q output of the latch circuits 72-1 to 72-5. Of the data Data(1) to Data(5), the data before the plurality of sample cycles indicated by the selection signal Sel from the speed difference data selection circuit 63 (stack buffer) is selected.

By switching the selection signal Sel according to the setting to the CPU (changing the selection signal in the speed difference data selection circuit 63), even if the data is latched at a fixed sample period, the data is latched at a time earlier than an arbitrary number of samples. It becomes possible to take out the information of the generated pulse.

Reference numeral 66 in FIG. 15 is a subtracter (Sub2) for calculating the difference between the latest pulse phase in the pulse phase buffer 61 and the pulse phase selected by the previous value selection selector 64 before a plurality of sample periods, and 67 is , A subtracter (Sub3) for calculating the difference between the latest pulse time in the pulse time buffer 62 and the pulse time selected by the previous value selection selector 65 a plurality of sample cycles before.

Reference numeral 68 denotes a divider that divides the phase difference output from the subtractor 66 by the time difference output from the subtractor 67 and outputs the speed detection 1 (speed detection value). The subtractors 66 and 67 and the divider 68 constitute the speed detection calculation unit of the present invention.

The pulse phase buffer 61, the pulse time buffer 62, the speed difference data selection circuit 63, the previous value selection selectors 64 and 65, the subtracters 66 and 67, and the divider 68 are implemented as software as constituent elements of the CPU arithmetic function. I assume that.

It is set as the selection signal Sel of the speed difference data selection circuit 63. How to determine this selection signal Sel is based on the empirical rule that "the shorter the time interval for calculating the speed calculation is, the higher the response performance is, and the longer the time is, the better the accuracy is". An empirical method such as the number and the amount of generated jitter can be considered.

According to the configurations of FIGS. 15 and 16, the speed detection period from the pulse information of a plurality of pulse periods before to the latest pulse information can be lengthened (set by the selection signal setting unit), and the pulse signal of the speed detection can be performed. It is possible to suppress the offset error due to the fluctuation of the occurrence time and improve the speed detection accuracy.

FIGS. 15 and 16 show a configuration in which the speed detection period can be changed even in the fixed interrupt cycle. This can be easily realized by effectively utilizing the memory function inside the CPU. Further, by increasing the number of speed calculation times, it is possible to execute a plurality of speed detection calculations having different speed detection periods. Therefore, FIG. 17 shows an example in which a plurality of speed detections, for example, two speed detection calculations of speed detection 1 and speed detection 2 are executed. In FIG. 17, a portion different from FIG. 15 will be described. As a selection signal setting unit, instead of the speed difference data selection circuit 63 of FIG. 15, the pulse information acquired and stored before the first sample period is selected. The first selection signal Sel1 (previous time 1) and the second selection signal Sel2 (previous time 2) for selecting the pulse information acquired and stored before the second sampling period before the first sampling period. ) And a speed difference data selection circuit 83 are provided.

Further, as a first past information selection unit, a previous value 1 selection selector 64-1 for selecting the pulse phase information before the first sample period in the pulse phase buffer 61 by the first selection signal Sel1, and a pulse time A previous value 1 selection selector 65-1 for selecting pulse time information before the first sample period in the buffer 62 is provided.

Further, as the second past information selection unit, the previous value 2 selection selector 64-2 that selects the pulse phase information before the second sample period in the pulse phase buffer 61 by the second selection signal Sel2, and the pulse time A previous value 2 selection selector 65-2 for selecting pulse time information before the second sample period in the buffer 62 is provided.

Further, as a first speed detection calculation unit, a subtracter that calculates a difference between the latest pulse phase of the pulse phase buffer 61 and the pulse phase before the first sample period selected by the selector 64-1 for selecting the previous value 1 66-1 and a subtracter 67-1 for calculating the difference between the latest pulse generation time of the pulse time buffer 62 and the pulse generation time before the first sample period selected by the previous value 1 selection selector 65-1. , A divider 68-1 that divides the phase difference that is the deviation output of the subtractor 66-1 by the time difference that is the deviation output of the subtractor 67-1 to output the speed detection 1 (first speed detection value). And are provided.

Also, as a second speed detection calculation unit, a subtractor that calculates a difference between the latest pulse phase of the pulse phase buffer 61 and the pulse phase before the second sample period selected by the selector 24-2 for selecting the previous value 2 66-2 and a subtracter 67-2 for calculating a difference between the latest pulse generation time of the pulse time buffer 62 and the pulse generation time of the second sample period selected by the previous value 2 selection selector 65-2. , A divider 68-2 that divides the phase difference, which is the deviation output of the subtractor 66-2, by the time difference that is the deviation output of the subtractor 67-2, and outputs the speed detection 2 (second speed detection value). And are provided.

Other parts are configured the same as in FIG.

In the configuration of FIG. 17, each operation up to the speed detection calculation is the same as that of FIG. 15, and the speed detection 1 and the speed detection 2 calculated in different speed detection periods can be obtained.

In this way, different speed detection periods are set for the two types of speed detection, and the advantages of each speed detection are utilized, whereby "speed error becomes large when the speed detection cycle is short, and conversely when the speed detection period is long, waste time is lost." Is long and the response performance is limited.” FIG. 18 is a block diagram of a speed control system of a rotating machine that takes measures against the problem, and the speed detection device of FIG. 17 is applied to a speed control method called general proportional-plus-integral (derivative) control (PI(D) control). It is an example.

In FIG. 18, the CPU operation portion is expressed as a frame and arranged in the center, and the left side outside this frame corresponds to the digital detection circuit of FIGS. 15 and 17, and each element other than the pulse encoder 50 in the digital detection circuit. The circuit is the speed detection circuit 100.

The ASR control unit (Automatic Speed Regulator) 200 of the CPU calculation unit is configured as follows.

The speed command generator 201 outputs the target speed of the rotating machine as a speed command according to time, and the speed control performs an operation to follow this.

The speed detection calculation unit 210 corresponds to the CPU calculation unit on the right side of FIG. 17, and outputs two types of speed detection values, speed detection 1 and speed detection 2, which are different in speed detection period.

The subtractor 202 takes the deviation between the speed command and the speed detection 1, and the subtractor 203 takes the deviation between the speed command and the speed detection 2.

Reference numeral 204 is a P(D) control unit as a proportional control term for performing proportional (derivative) control on the deviation output of the subtractor 202, and 205 is an integral control term for performing integral control on the deviation output of the subtractor 203. I control unit.

The PI control output obtained by adding the outputs of the P(D) control unit 204 and the I control unit 205 by the adder 206 corresponds to the torque command desired to be generated in the rotating machine.

Reference numeral 300 denotes a torque/current command conversion unit that converts the torque command output from the adder 206 into a current command to flow to the rotating machine.

The output of the torque/current command conversion unit 300 is deviated from the detected current value (actual current) in the subtractor 400.

The ACR control unit 500 performs ACR control on the deviation output of the subtractor 400 and outputs an output voltage command, and performs current control (ACR) so that the actual current follows the current command.

In the above configuration, the PI control in the ASR control unit 200 is a control method that combines two types of functions, "P control realizes high-speed response performance and I control slowly corrects steady-state error." is there. Therefore, as the speed detection information which is the deviation from the speed command, it is sufficient to use the speed detection information having the property of sufficiently exhibiting the function corresponding thereto.

Therefore, the first selection signal Sel1 for obtaining the speed detection 1 in FIG. 17 is set to, for example, a selection signal for selecting pulse information two sampling cycles before, and the second selection signal for obtaining the speed detection 2 is set. Sel2 is set as a selection signal for selecting pulse information of, for example, 8 sample periods before. As a result, the speed detection 1 has a short detection period, and the speed detection 2 has a long detection period.

Since the proportional control (P(D) control unit 204) in the ASR control unit 200 of FIG. 18 affects the performance of responsiveness, wasteful time is reduced by using information in which the detection period of the speed detection 1 is short, and the proportional term Set the control gain of as high as possible to improve the response performance.

On the other hand, the time constant of the integral term is a value determined by the moment of inertia of the machine, and is usually longer than the speed detection cycle. Therefore, for the speed detection of the integral term (I control unit 205), even if a signal with a long dead time is used, the adverse effect is small. Therefore, the measurement time of the speed detection 2 is long (the dead time is large but the accuracy is high). Use good) information.

In this way, a control system that achieves both "speed control accuracy and response performance" is constructed by properly using the speed information to be used according to the control term so that the characteristics possessed by the two types of speed detection can be exerted. be able to.

The speed control system shown in FIG. 18 can shorten the interrupt cycle (sampling cycle) because the performance of the digital arithmetic unit is improved. When the time is shortened, the influence of the fluctuation of the waveform is increased to the contrary, and the problem that the speed detection error is increased is solved. That is, in order to satisfy the contradictory requirements of the speed detection accuracy and the delay time of speed detection, two types of speed detection with different lengths of the measurement period are installed, and the proportional term of PI control has a speed of a short measurement period. The detection value is configured to use the speed detection value for a long measurement period as the integral term.

This is because the proportional term realizes the response performance, but the integral component dominates the speed control accuracy. Therefore, only the integral term is applied to a measuring method that emphasizes accuracy rather than responsiveness. The configuration of FIG. 18 is referred to as reference example 1. This is assumed to be effective when the pulse resolution is high, and is shown as a comparison target in order to make the novel point of the present invention easy to understand.

Japanese Patent No. 3173174

Chapter 2 of The Institute of Electrical Engineers of Japan, Theory of Electricity, Vol. 155, No. 11, pp1316-1324 (1995)

The configuration of Reference Example 1 assumes a case where the resolution of the pulse encoder is high to some extent, and when a low-resolution pulse encoder of a few hundred pulses [p/r] or less per revolution is applied, The encoder pulse period at time is much lower than the control sample period.

Therefore, even if an attempt is made to execute the speed detection calculation in the interrupt process, the measurement information is not updated and the speed detection value cannot be updated because the pulse does not occur (is inactive). This will be referred to as a pulse or speed detection pause period. When such a pulse pause period occurs, the delay time before the controller detects the speed with respect to the actual speed increases, and if measures such as holding the previous value during the pause period are adopted, the actual speed The error of becomes large.

FIG. 9 is a schematic time chart for explaining the influence of the delay time of the speed detection and the pulse pause period. FIG. 9A shows an output pulse waveform of the “A phase and B phase” two-phase encoder, and shows a state in which the speed further decreases in the low speed region.

By detecting this pulse edge and counting up and down the phase counter, it is converted into phase detection information of a digital value corresponding to the encoder pulse phase such as θpp in FIG. 9B. When the digital control process is started by the interrupt signal shown in FIG. 9C, first, the value of the phase counter is read, and then the difference between the phase and the time information read at the time of the previous interrupt is calculated to obtain the value shown in FIG. The phase difference Δθpp and the time difference Δtpp in b) are obtained, and the detection speed is calculated by dividing these (Δθpp/Δtpp). However, since this speed detection value is calculated in the processing in synchronization with the interrupt signal, it is updated in synchronization with the interrupt signal as shown in FIG. 9D showing the speed detection value ωdet and the actual speed ωr. Recognized as a waveform. Then, when the actual speed is changing, the delay component due to the time width of Δtpp necessary for speed detection and the delay time between the pulse generation time and the interrupt timing ((Da) in FIG. 9D) are detected. Equivalent) will occur.

Furthermore, when the pulse period becomes longer than the interrupt period as in the latter half of the time elapsed, speed detection due to the fact that the phase counter value is not updated in the interrupt process indicated by the ellipse (dotted line) in the figure There will be a rest period. In the pulse pause period of FIG. 9, the speed detection value holds the previous detection value, but it can be seen that this causes a large error from the actual speed.

As described above, in the speed detection using the PAL encoder, there are the following two types of detection delays.

(Delay time 1) One is a sum of a delay component due to the time width of the sample time difference Δtpp between two pulse edges and a component in which the timing of digital calculation is delayed with respect to the pulse generation time. It is always present, even if the pulse is not paused.

(Delay time 2) The other is a delay component due to the fact that speed cannot be detected due to pulse pause. In particular, a delay factor occurs at extremely low speeds.

For these explanations, what happens to the phase obtained by time-integrating the speed detection value ωdet in FIG. 9D is schematically shown as a dotted line in FIG. 9B. (Delay time 1) is a time difference component between the sample time and the intermediate time of the measurement pulse interval shown by (Da) in the figure, and when decelerating as in FIG. 9, only this delay time Since the speed detection is delayed, it causes a speed detection error. Further, when a delay time occurs due to the pulse pause, a period in which the speed detection holds the previous value also occurs as shown in (Db) in the figure, and a delay component of (delay time 2) is also added.

Normally, the influence of the speed detection error caused by these two types of delay time is evaluated by the size of the difference from the actual speed ωr. However, in the present invention, since it is evaluated as a disturbance with respect to the integral term of the speed control, FIG. In (b), the speed detection is inversely time-integrated and returned to the phase component (θintg=∫(ωdet)dt), which is expressed as a phase error of the original θ _pp (measured pulse phase) waveform. Seen (illustration (Dc)).

In FIG. 9B, since the speed detection error due to (delay time 1) is integrated over time as the speed becomes slower, the phase difference shown in (Dc) gradually increases, but due to the pulse pause in the latter half (delay time 2). Occurs, the phase error will increase significantly.

Since the difference between the speed command value and the speed detection value is also time-integrated in the integral term of the PI control calculation, an error proportional to such a phase error should occur. When the speed further changes suddenly, the speed detection error caused by the delay of the detection time as shown in (Da) of FIG. 9 becomes larger, and when the speed is rapidly decelerated to the extremely low speed range, The error component due to the pulse pause delay such as Db) becomes large. As described above, since these delay time components are accumulated in a large amount during acceleration/deceleration, they cause overshoot when shifting to a constant speed after acceleration, and the latter (delay time 2) that occurs at a lower speed is Not only the speed error is large, but also the waste time component of the control becomes long, which causes an unstable phenomenon.

First, FIG. 10 is a schematic time chart for explaining an example of overshoot during acceleration. In FIG. 10, “proportional control (P control)” (illustrated characteristic line (1)) and “PI control in an ideal case where there is no delay time in speed detection” in response to a speed command for shifting from an accelerating state to a constant speed. "(Represented characteristic line (2)) and "PI control with detection delay in speed detection" (represented characteristic line (3)) are shown.

In the case of P control (characteristic line (1)), overshoot does not occur when shifting from the acceleration state to a constant speed, but the response at the portion reaching the command value is slow, and the steady deviation with respect to the command value Occurs.

Next, in the case of a combination of ideal speed detection with no detection delay and PI control (characteristic line (2)), the response delay is reduced because the speed difference in the acceleration period is reduced by the integral term, but the broken line As shown in, overshoot occurs. On the other hand, even in the same PI control, if there is a speed detection delay, the response waveform (characteristic line (3)) is like a solid line, and during the acceleration period, the speed detection delay causes a large speed difference between the speed command value and the speed detection value. Since it appears, during acceleration in the positive direction, a control error occurs in which the integral term of PI control increases in the positive direction.

Therefore, as shown in FIG. 10A, since the integral term due to the speed error component due to the detection delay is excessively corrected, the speed difference from the speed command during the acceleration period is smaller, but during this acceleration period An excessive integral term is accumulated, and therefore, when the speed shifts to a steady speed, the speed overshoot becomes large as shown in (a). As described above, a disturbance occurs in the response characteristic of PI control due to the delay time of speed detection. Therefore, in designing the proportional gain and the integral time constant, it is necessary to consider the disturbance and design the control response to be low. There is a need.

As superposed on this, in the low speed region, the delay component due to the pulse pause period causes a large disturbance, so that it becomes more unstable. Therefore, it is necessary to further design the control response to be low.

When PI control of Conventional Example 1 (FIG. 1) and Conventional Example 2 (FIG. 3) is combined with “speed detection by a low-resolution pulse encoder”, an error occurs in the speed control characteristic compared to the ideal state. However, there are problems that it is necessary to design the response performance to be low and that it tends to become unstable in the low speed range.

The present invention is to solve the above problems, and an object thereof is to provide a speed control system capable of suppressing a disturbance caused by a speed detection delay.

The speed control system according to claim 1 for solving the above-mentioned problems is a speed control system for a rotating machine to which a speed detection using a pulse encoder and a speed-type proportional-plus-integral control method are applied,
The torque command component (τ_p) of the proportional term of the proportional-plus-integral control method is obtained by multiplying the difference between the speed command value (ω_ref) and the detected speed value (ω_det) by the proportional gain (Kps),
The torque command component (τ_i) of the integral term of the proportional-plus-integral control method is added to the speed command value (ω_ref) and the correction amount (Δω_fb) of the speed command value, and the phase command value ( (Θ_ref)′) is calculated, and a proportional gain (Kps) and a coefficient gain (dT/d) corresponding to an integration time constant are calculated with respect to the difference between the phase command value ((θ_ref)′) and the phase detection value (θ_det). It is calculated by multiplying
The torque command component (τ_p) of the proportional term and the torque command component (τ_i) of the integral term are added, and the addition output is passed through the torque limiting unit to output the torque command (τ_pio) of the proportional-integral control,
The correction amount (Δω_fb) of the speed command value is calculated as the torque command correction amount (Δτ_fb) by subtracting the input component of the torque limiting unit from the output component of the torque limiting unit. The torque command correction amount (Δτ_fb) is then calculated by multiplying the proportional gain and the reciprocal number (1/Kps, Tis/dT) of the coefficient gain corresponding to the integral time constant.

The speed control system according to claim 2 is the speed control system according to claim 1, wherein the detected speed value (ω_det) detects each of rising and falling edges of the output pulse of the pulse encoder, and each detected edge. Is counted and latched as a pulse phase value, the phase difference that is the difference between the latest pulse phase value and the past pulse phase value before the edge detection timing is calculated, and the latest pulse generation time of the output pulse and edge detection It is characterized in that a time difference, which is a difference from a past pulse generation time before timing, is calculated, and the calculated phase difference is divided by the calculated time difference.

According to the above configuration, since the torque command component of the integral term directly uses the phase detection information that is not subjected to time integration, it is not affected by the speed error due to the delay time caused by the time width of the time difference for speed detection. can do.

For this reason, the speed error component due to the detection delay is not accumulated in the integral term during acceleration/deceleration, the overshoot amount at the time of shifting to the steady speed is suppressed, and the ideal speed response characteristic without speed detection delay is obtained. You can get closer.

Further, the speed control system according to claim 3 is the speed control system according to claim 1, wherein the phase detection value (θ_det) detects the rising edge and the falling edge of the output pulse of the pulse encoder to obtain edge detection timing. , Is obtained by counting the output pulses at the edge detection timing, latching the output pulse as a pulse phase value, and reading the latched pulse phase value at a sample timing generated by a sample period generating unit,
The speed detection value (ω_det) is calculated by calculating a phase difference, which is a difference between the latest phase detection value of the obtained phase detection values (θ_det) and the past phase detection value before the edge detection timing, The clock signal is counted as time information, the time when the count value of the output pulse changes at the edge detection timing is latched, and the latched time is read at the sample timing to generate the pulse generation time (Tpp). And calculating a first time difference that is the difference between the latest pulse generation time and the past pulse generation time before the edge detection timing, and dividing the calculated phase difference by the calculated first time difference. Demanded by
A sample time (Ts) updated at the sample timing is measured from time information of counting the reference clock signal, and a clock difference (Ts) corresponding to an elapsed time from the pulse generation time (Tpp) to the sample time (Ts). -Tpp) as the second time difference (ΔT_est),
The correction ratio (ΔT_est/dT) is obtained by dividing the second time difference by the sampling period (dT), and the correction ratio is added to the speed command value (ω_ref) and the correction amount (Δω_fb) of the speed command value. (ΔT_est/dT) is multiplied to obtain the phase difference correction component (Δθref_est),
The phase command value is obtained as a phase command value (θ_ref) approximate to the pulse generation time by subtracting the phase difference correction component (Δθref_est) from the phase command value ((θ_ref)′). I am trying.

According to the above configuration, it is possible to temporally match the sampling period for executing the speed detection and speed control (PI control) processing with the generation time of the encoder pulse, and it is possible to calculate an accurate phase command. This has the effect of correcting the phase component corresponding to the delay time difference for the delay time component caused by the asynchronous sampling time and pulse generation time, suppressing the influence of the delay time on the integral term, and speed response. The characteristic can be brought closer to a more ideal response characteristic with no detection delay.

The speed control system according to claim 4 is the speed control system according to claim 1, wherein the phase detection value (θ_det) detects the rising edge and the falling edge of the output pulse of the pulse encoder to obtain edge detection timing. , Is obtained by counting the output pulses at the edge detection timing, latching the output pulse as a pulse phase value, and reading the latched pulse phase value at a sample timing generated by a sample period generating unit,
The speed detection value (ω_det) is calculated by calculating a phase difference, which is a difference between the latest phase detection value of the obtained phase detection values (θ_det) and the past phase detection value before the edge detection timing, The clock signal is counted as time information, the time when the count value of the output pulse changes at the edge detection timing is latched, and the latched time is read at the sample timing to generate the pulse generation time (Tpp). And calculating a first time difference that is the difference between the latest pulse generation time and the past pulse generation time before the edge detection timing, and dividing the calculated phase difference by the calculated first time difference. Demanded by
A sample time (Ts) updated at the sample timing is measured from the time information obtained by counting the reference clock signal, and a clock difference (Ts) corresponding to the elapsed time from the pulse generation time (Tpp) to the sample time (Ts). -Tpp) as the second time difference (ΔT_est),
The speed detection value (ω_det) is multiplied by the second time difference (ΔT_est) to obtain the predicted amount (Δθ_est) of the phase that changes within the second time difference, and the predicted amount is used as the phase detection value (θ_det). By adding, the corrected phase detection value (θ_destest) at the interrupt time is obtained,
The phase detection value (θ_destest) is used in place of the phase detection value (θ_det) to obtain the difference from the phase command value ((θ_ref)′).

According to the above configuration, the predicted amount (Δθ_est) of the phase that changes during the elapsed time (second time difference ΔT_est) from the pulse generation time (Tpp) to the sampling time (Ts) corresponding to the time delay component is calculated, The corrected phase detection value (θ_dest) at the interrupt time is obtained by correcting the phase detection value (θ_det). Therefore, by using this θ_destest as the phase detection value, it is possible to match the simultaneity of the phase command and the phase detection.

Further, since the sample time (Ts) is updated at the sample timing (for each interrupt signal), the second time difference (ΔT_est) corresponding to the time delay component and the predicted amount of phase (Δθ_est) are also updated, As a result, it works to keep updating the corrected phase detection value (θ_destest) at the interrupt time.

As a result, it is possible to suppress the delay component due to the fact that the speed cannot be detected due to the pulse pause.

A speed control system according to a fifth aspect is characterized in that, in any one of the first to fourth aspects, a low-pass filter is provided on a torque command output side of the proportional-plus-integral control.

According to the above configuration, when the phase resolution of the pulse encoder is low, it is possible to suppress a disturbance in which the integral term changes stepwise.

(1) According to the invention described in claims 1 to 5, since the torque command component of the integral term directly uses the phase detection information that is not time-integrated, it is caused by the time width of the time difference for speed detection. It is possible to eliminate the influence of the speed error due to the delay time.

For this reason, the speed error component due to the detection delay is not accumulated in the integral term during acceleration/deceleration, the overshoot amount at the time of shifting to the steady speed is suppressed, and the ideal speed response characteristic without speed detection delay is obtained. You can get closer.

Therefore, it is possible to suppress the disturbance caused by the speed detection delay.
(2) According to the invention described in claim 3, the sampling period for executing the processing of the speed detection and the speed control (PI control) and the generation time of the encoder pulse can be temporally matched, and an accurate phase can be obtained. Command can be calculated. This has the effect of correcting the phase component corresponding to the delay time difference for the delay time component caused by the asynchronous sampling time and pulse generation time, suppressing the influence of the delay time on the integral term, and speed response. The characteristic can be brought closer to a more ideal response characteristic with no detection delay.
(3) According to the invention described in claim 4, the corrected phase detection value (θ_destest) at the interrupt time is obtained by the predicted amount (Δθ_est) of the phase changing at the second time difference (ΔT_est), and Is used as the phase detection value, it is possible to match the simultaneity of the phase command and the phase detection.

Further, since the sample time (Ts) is updated at the sample timing (for each interrupt signal), the second time difference (ΔT_est) corresponding to the time delay component and the predicted amount of phase (Δθ_est) are also updated, As a result, it works to keep updating the corrected phase detection value (θ_destest) at the interrupt time.

As a result, it is possible to suppress the delay component due to the fact that the speed cannot be detected due to the pulse pause.
(4) According to the invention described in claim 5, when the phase resolution of the pulse encoder is low, the disturbance in which the integral term changes stepwise can be suppressed.

The block diagram which shows the prior art example 1 of the PI control system used by a speed control system. The block diagram which shows the structure in the middle of converting from the prior art example 1 of the PI control system used in a speed control system to the prior art example 2. The block diagram which shows the prior art example 2 of the PI control system used by a speed control system. The block diagram which shows the structure in the middle of converting from the conventional example 2 of the PI control system used by a speed control system to this invention system. 1 is a block diagram of Embodiment 1 of the present invention. FIG. 2 is a block diagram of Embodiment 2 of the present invention. FIG. 3 is a block diagram of Embodiment 3 of the present invention. FIG. The block diagram which shows the other form of Example 3 of this invention. 4A and 4B are diagrams illustrating a problem in speed detection at a low speed, in which FIG. 7A is an output signal waveform diagram of a two-phase pulse encoder, FIG. 7B is an encoder pulse phase characteristic diagram, and FIG. The figure, (d) is the characteristic figure of detection speed and actual speed. Explanatory drawing which compared the influence of speed control system and speed detection. FIG. 9 is a velocity characteristic diagram for explaining acceleration characteristics of Conventional Example 1 and Example 3. FIG. 9 is a torque control characteristic diagram for explaining acceleration characteristics of Conventional Example 1 and Example 3. FIG. 6 is a speed characteristic diagram for explaining characteristics of deceleration to a low speed range after acceleration in Conventional Example 1 and Example 3. FIG. 8 is a torque control characteristic diagram for explaining characteristics of deceleration to a low speed range after acceleration in Conventional Example 1 and Example 3. FIG. 3 is a configuration diagram of a device that is a base of a speed detection device used in Reference Example 1 of the speed control system. The block diagram of the principal part of FIG. The block diagram of the speed detection apparatus used for the reference example 1 of a speed control system. The block diagram which shows the reference example 1 of a speed control system.

Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments. FIG. 9B shows the detected phase θpp by the pulse encoder and the phase (θintg=∫(ωdet)dt) obtained by time-integrating the speed detection value. However, by changing the idea, this phase difference is integrated by PI control. It can be regarded as corresponding to the term, that is, the time integral value of the speed difference. This phase can be used only for the integral term, but since only the phase detection information is required, it is possible to suppress the disturbance caused by the speed detection delay.

Therefore, in the present embodiment, the PI control block diagram configured by the discrete system of FIG. 3 is further developed into an equivalent control block, and the integral term of PI control is ““phase command obtained by time integration of speed command value”. And "the difference of the detected phase of the encoder" is used.

The configuration of the first embodiment is shown in FIG. This can be derived by performing equivalent conversion as shown in FIG. 4 on the configuration of FIG. First, in FIG. 4A, the integrating unit (the circuit of the sampler 1f and the adder 4d) that outputs the torque command τ_i of the integral term in FIG. 3 is moved to the immediately preceding input term of the adder 4a. Then, the integration gain (dT/Tis) (coefficient unit 3) is provided at the subsequent stage (the circuit of the sampler 1g and the adder 4e) and the feedback term (the sampler 1h and the adder 4f of the torque correction amount Δτ_fb that is the torque limit excess amount). The integrating unit is branched and present at two places of (circuit).

Next, the integration unit (the circuit of the sampler 1g and the adder 4e) on the integral gain side in FIG. 4A is moved to before the difference calculation between the speed command value and the speed detection value (the input side of the subtractor 2a). Then, as shown in FIG. 4B, the speed command value ω_ref is integrated by the sampler 1i and the adder 4g to calculate the phase command θ_ref, and the speed detection value ω_det is integrated by the sampler 1j and the adder 4h to detect the phase. The value θ_det is calculated. Then, the difference between θ_ref and θ_det is taken by the subtractor 2d, the deviation output of the subtractor 2d is multiplied by the proportional gain Kps, and then input to the coefficient unit 3 (integral gain). Originally, in order to integrate the speed with time and convert it into a phase, the sample time dT is multiplied before the adders 4g and 4h, but for simplicity, it is summarized in the coefficient unit 3.

Further, the position of the adder 4a to which the torque correction amount Δτ_fb, which is the excess amount of the torque limit in FIG. 4(b), is fed back is set to a position before the position of the speed command side integrating unit (the circuit of the sampler 1i and the adder 4g). 4C, the structure shown in FIG. Since Kps and dT/Tis gain exist on the output side of the subtractor 2d, the reciprocal of this gain, 1/Kps and Tis/dT, are inserted in the feedback loop of Δτ_fb. The value obtained by multiplying the reciprocal is the value Δω_fb (correction amount of the speed command value) in units of speed.

The above-mentioned modification, that is, the movement of the block, is a functionally equivalent conversion only by moving backward the addition portion of the signal flowing to one side.

In order to expand this to FIG. 5, speed detection is used as an input in the proportional term of FIG. 4C, but it is replaced with a configuration in which phase detection (θ_det) is time difference (corresponding to time differentiation) and speed detection is performed. .. Further, θ_det obtained by integrating the speed detection of the integral term of FIG. 4C is replaced with the sampled phase detection component of the phase information (θ_det) i obtained by measuring the pulse generated by the encoder (time integration is performed. Without using the phase detection information directly). By doing this, it is possible to obtain the phase difference as shown in FIG. 5 by utilizing the fact that the time difference of the speed difference between the speed command value and the speed detection value is equivalent to the phase difference through the equivalent conversion of FIG. It is possible to obtain a configuration that realizes almost the same function.

In FIG. 5, the speed detection value (ω_det) is detected by the rising edge and the falling edge of the output pulse of the pulse encoder, the detected edges are counted, and the pulse phase value (θ_det) i is stored in the latch circuit 11a. The latch circuit 11b and the subtracter 2e calculate the phase difference, which is the difference between the latest pulse phase value (immediately before the sampling time) and the previous pulse phase value before the edge detection timing, and the output pulse is generated. The time information ((T_det)i) is latched in the latch circuit 11c, and the time difference (ΔT), which is the difference between the latest pulse generation time (immediately before the sample time) and the past pulse generation time before the edge detection timing, is calculated. Calculation is performed by the latch circuit 11d and the subtractor 2f, and the calculated phase difference is divided by the calculated time difference (ΔT) in the divider 12a to obtain the value.

The speed detection value (ω_det) can be obtained, for example, by using the speed detection device shown in FIGS.

Here, the portion for calculating the speed detection value (ω_det) in FIG. 5 uses the symbol “ΔT” which is a time difference different from the other sample time (sample period: dT), and the difference in the occurrence time of the encoder pulse edge. Since it is a component, it is not related to the control sample timing. Therefore, a symbol different from other samplers (Z ⁻¹ ) is used to describe the difference by describing it as a timing signal (edge detection timing signal) “Edg”. The details will be described in the part of the speed detection method of the second embodiment. However, since the generation timing of the encoder pulse is not synchronized with the sample period, the operation timing of Z ⁻¹ and the time difference component thereof in the part for obtaining the time difference of speed detection Since it is different from the sample period of the control calculation, timing matching processing is required. However, since the main purpose is to understand the principle in FIG. 5, the complicated part is omitted and only the symbol “Edg” is simplified to make it different. Emphasized that it is timing.

Since the pulse generation time and the sampling time are asynchronous, a part of the error of (delay time 1) described in the section “Problems to be solved by the invention” occurs. Example 3 proposes a countermeasure against this error.

FIG. 5 after conversion from the conventional examples 1 and 2 has the following configuration. Items (1) to (7) used in the description of FIG. 1 are the same, so description thereof will be omitted, and only differences will be described.

As described above, the speed detection value ω_det is replaced with the time difference (corresponding to differentiation) of the phase detection θ_det. Specifically, the phase θ_det and the generation time T_det by the phase counter at the pulse generation timing (Edg) immediately before the sample time are read out, and the difference between the phase and time already read in the previous sample processing is calculated to obtain the phase difference. Is divided by the time difference to obtain the speed detection value ω_det.

As in the case of FIG. 1, the proportional term calculates the torque command component τ_p of the proportional term by multiplying the difference between ω_ref and ω_det by the proportional gain Kps. However, the difference is the integral term, which is for speed detection. The phase information θ_det (corresponding to θpp in FIG. 9B) before being used as the time difference is directly used. Instead, the speed command value ω_ref is time-integrated (integrated for each sample calculation) by the sampler 1i and the adder 4g to generate a phase command (θ_ref)'.

Strictly speaking, this is not a problem if the output of the PI control does not reach the torque limit of the torque limiter 5. However, in the speed type PI control, when the torque limit before final output operates, feedback is provided to the integral term. It is necessary to take this component into consideration because it is corrected. Therefore, the feedback correction component Δω_fb (correction amount of the speed command value) is added by the adder 4a between the speed command value ω_ref and the integrating unit (sampler 1i and adder 4g).

Then, the corrected speed command values are integrated (time integrated) to obtain a phase command (θ_ref)′ in consideration of the limiting operation by the torque limiter 5. Further, the phase detection value θ_det is subtracted from the phase command (θ_ref)′ by the subtracter 2d to obtain the difference Δθ_i, which is used as “a component obtained by time-integrating the difference between the speed command value and the speed detection value” in Conventional Example 2. Considering this to be equivalent, this Δθ_i is multiplied by the gain Kps and dT/Tis to calculate the torque command τ_i of the integral component.

Then, as in Conventional Example 2 in FIG. 3, the proportional term τ_p and the integral term τ_i are added by the adder 4b to calculate (τ_p+τ_i), and the torque limiter 5 limits this within the range of (±τ_lim). And the final PI control output is obtained.

The value obtained by subtracting the value on the input side from the value on the output side of the torque limiter 5 becomes the excess amount Δτ_fb (torque command correction amount) of the torque command suppressed by the torque limiter 5, so the reciprocal of the integration coefficient (Tis/ dT and 1/Kps) are multiplied to obtain the correction value Δω_fb (correction amount of the speed command value) of the integral term used in the next calculation.

When the phase resolution of the encoder or the like is low as compared with the conventional method of integrating the speed difference, a disturbance in which the integral term changes stepwise occurs. For this, a countermeasure method such as adding a low-pass filter (high-pass cutoff filter) 15 as a broken-line block (LPF shown in the figure) to the output of the PI control in FIG. Should be applied. However, in the case of a control system that is less affected by the above disturbance, the low pass filter 15 may not be provided.

By configuring the velocity-type proportional-plus-integral control computation as shown in FIG. 5, a control computation equivalent to that in FIG. 1 can be realized, and the phase information before the time integration is directly performed for the integral term instead of speed detection. By using it, it is possible to eliminate the influence of the speed error due to the delay time caused by the time width of the time difference for speed detection.

The speed detection error component due to the delay time component becomes large when the speed is accelerated or decelerated, but by applying the first embodiment, it is possible to prevent the speed detection error from being accumulated in the integral term of the speed control during the acceleration and deceleration. As a result, it is possible to suppress the overshoot component of the speed that has occurred at the time of shifting to the steady speed. In order to realize the torque limiting operation, the feedback correction value Δω_fb of the integral term is used to modify the integration calculation unit of the phase command (θ_ref)′, so that the same speed PI control as in FIG. 1 is performed. be able to.

As described above, according to the first embodiment, the function equivalent to the speed control system using the conventional speed PI control is realized, but it is shown in the section of "Problems to be solved by the invention" ( The error accumulated in the integral term of the speed PI control can be suppressed by the speed error component due to the delay time 1). Therefore, the speed error component due to the detection delay during acceleration/deceleration is less likely to be accumulated in the integral term, so the amount of overshoot at the time of shifting to the steady speed can be suppressed, and the speed response can be approximated to the ideal speed response characteristic without speed detection delay. You can

In the first embodiment, the speed is detected only by reading the phase and time information latched at the time of the pulse in the calculation processing of the discrete system which is activated at the sample timing of the interrupt signal or the like. Strictly speaking, contradiction occurs because different interrupt timings are mixed.

Strictly speaking, the encoder pulse generation time is generated independently of the sample timing (asynchronously), so if you want to match more precisely different times, use interpolation calculation from the phase command sample values before and after the pulse generation timing. It suffices to obtain the phase command estimated value of the pulse generation timing, and the accuracy can be improved by using this method.

In particular, as shown in FIG. 9, when the pause time of the encoder pulse becomes longer as the speed becomes slower, only the command phase advances more and more. Therefore, if the time is not adjusted, a large difference in phase difference appears. become. It can be considered that this has an effect corresponding to (delay time 2) described in the section “Problems to be solved by the invention”.

Therefore, it is necessary to take measures against the two types of delay time components shown in the section "Problems to be solved by the invention" in the first embodiment. In order to suppress the influence of this delay time, the following two types of measures are proposed below, such as the second and third embodiments.

(Countermeasure of the second embodiment)... Since there is a time lag between the sampling period for performing the speed detection and speed control (PI control) processing and the generation time of the encoder pulse, the pulse generation time and the time coincidence. Calculate accurate phase command. Specifically, interpolation calculation or the like is applied to the phase command of the sample time using the pulse generation time information.

(Countermeasure of Third Embodiment)... The phase command is updated at an interrupt cycle for executing the processes of speed detection and speed control (PI control), and the detected phase is corrected this time. Specifically, the phase lead amount before the interrupt time from the pulse generation time is predicted and corrected. As a result, not only time matching but also the problem that the phase difference changes stepwise within the width corresponding to the pulse resolution can be dealt with, and the phase correction function during the pulse pause period can also be realized.

The configuration of the second embodiment is shown in FIG. This is to correct the phase command value (θ_ref)′ obtained by integrating the speed command value ω_ref, and is a measure to obtain the phase command at the pulse generation time by correction calculation.

In the configuration of FIG. 6, since it is necessary to clearly indicate the pulse time used for speed detection, an example of the speed detection method is additionally shown in the drawing. It is composed of the following measuring circuits and arithmetic functions.

(1) pp is a pulse signal of the encoder (corresponding to the A and B phase signals in FIG. 9A).

(2) The edge detector 16 detects the edge detection timing Edg at which the pulse signal changes.

(3) The phase counter 17 up/down the counter value at the edge detection timing and outputs the count value corresponding to the phase, and further, this is sampled by the sampler 1 m (Z ⁻¹ ) by the sampling period generator. It is latched at the sample timing s (timing of the interrupt signal of FIG. 9C) generated at 30 to obtain the phase information θpp. As the phase counter value, the value updated at the edge detection timing Edg is held in the latch circuit 11e, and the phase data read for speed detection is latched in the sampler 1m at the sample period. In other words, since the latch structure has two different stages of Edg and sample timing s, the latch circuit 11e operated by Edg of the first stage is drawn in the phase counter block.

The sample timing s is an interrupt signal for starting the speed detection and control processing, but is also a timing signal for latching the data read by the speed detection and control processing in the register in the measurement circuit. In the digital arithmetic unit, in the process executed by this interrupt signal, the measured value latched from this register is read to obtain the phase θ_det. If the unit of the measured value (pulse number [p]) is converted to the rotation angle [rad], it may be converted by multiplying by the coefficient 2π/(4·Npp) (here, Npp[p/ r] is the number of pulses per one rotation of the A phase or B phase of the encoder). In FIG. 6, a multiplier 18 is provided on the output side of the sampler 1 m to convert it into a rotation angle [rad].

The time counter 19 counts up an accurate and high-frequency reference clock signal such as a crystal oscillator and outputs a counter value t corresponding to time, and when the phase counter is changed by the latch circuit 11f that updates at the Edg timing. Is latched in the latch circuit 1n (readout register; Z ^{−1 in the} figure) at the sample timing (interrupt timing) s, and the time information Tpp used for speed detection is measured. This is also read by the digital arithmetic unit, and when the unit of time is treated as [s], it may be converted to the time component T_det[s] by multiplying it by the period Tclk[s] of the reference clock signal. In FIG. 6, a multiplier 20a is provided on the output side of the sampler 1n, and the time unit of T_det is treated as [s (seconds)].

In order to obtain the speed detection from the values obtained by reading the phase and time information by the digital arithmetic unit, the subtractor subtracts the phase information θpp_z read at the time of the previous pulse generation by the latch circuit 11g and the sampler 1o and the latest read phase information θpp. 2f is subtracted to obtain the phase difference Δθpp, and the time information Tpp_z read at the time of the previous pulse generation by the latch circuit 11h and the sampler 1p and the latest read time information Tpp are subtracted by the subtractor 2g to obtain the time difference ΔTpp (first time difference ) Is obtained, and the divider 21 divides the phase difference Δθpp by the time difference ΔTpp to obtain the detection speed.

The conversion coefficient for speed detection may be a combination of the above-mentioned phase and time conversion coefficients (2π/4·Npp, Tclk[s]), but in reality, it is the pole of the rotating machine, which is the conversion coefficient of the mechanical angle and the electrical angle. It is also necessary to consider the logarithm (Pole/2). However, in FIG. 6, assuming that the number of pole pairs (Pole/2) is two poles, the term of the number of pole pairs is omitted.

In the case of an encoder that outputs a two-phase pulse, the measuring circuit for speed detection has a complicated configuration that further considers forward rotation and reverse rotation, but in FIG. 6 it is simplified and only the functional description is shown. Since a more detailed method has already been described in Non-Patent Document 1, it is omitted here.

The content of the proposal of the second embodiment focuses on the timing Edg at which the phase counter 17 operates and measures the value of the encoder pulse generation time with respect to the phase command value (θ_ref)′ corresponding to the time integration of the speed command value. As possible, similarly to the measurement circuit of the speed detection θpp, a sampling circuit (latch circuits 11e to 11h and a latch circuit 11i provided on the output side of the adder 4g) that latches at the edge detection timing Edg, and a sampling timing s. A read register to be operated (samplers 1m to 1p and a sampler 1r provided between the latch circuit 11i and the subtractor 2d) is inserted. As a result, by correcting the timing of obtaining the phase command value (θ_ref)′ (by setting the phase detection value θ_det to the minus input of the subtractor 2d), it is possible to obtain a temporal match with the occurrence time of the phase detection. I can.

That is, in the speed detection method as shown in FIG. 6, since the phase and the time at the pulse edge timing Edg are measured, the phase command value (θ_ref)′ obtained by integrating the speed command values is also measured at the same timing Edg. If sampled, the phase command value (θ_ref)′ at the same time as the pulse detection can be obtained, and the problem of time matching can be dealt with. In FIG. 6, the phase command value (θ_ref)′ is sequentially calculated and latched by the sampler (FIGS. 6A and 6B), and an equivalent interpolation calculation method that can be replaced (FIG. 6( c)) is described.

In the method of latching the phase command at the same time as the first pulse phase (FIGS. 6(a) and 6(b)), the phase integration is configured by a digital circuit and continuously updated in units of reference clocks, and the phase counter and By detecting with the same measuring circuit as the time latch, the phase command time-matched with the pulse generation time is obtained. As a result, the phase command and the phase detection can be temporally matched with each other, so that the error of the integral term of the PI control is suppressed.

However, in order to implement this function as it is, it is necessary to calculate and update the phase command value (θ_fef)′ at a high-speed frequency of the reference clock, which requires a dedicated high-speed arithmetic circuit. Therefore, it is proposed in FIG. 6C to approximate an equivalent function by interpolation calculation in the speed detection calculation process.

That is, the sample time Ts is measured from the time information of the time counter 19 by the sampler 1q updated at the sample timing s, and the clock difference (equivalent to the elapsed time from the pulse generation time (Tpp) to the sample time (Ts) ( (Ts-Tpp) is measured by the subtractor 2h, and this is multiplied by the coefficient Tclk of the multiplier 20b to perform unit conversion to obtain the time difference ΔT_est (second time difference).

Then, since the increment corresponding to the sample period (interval of the interrupt signal in FIG. 9) dT is added in the integration portion of the phase command, the second time difference is divided by the sample period (dT) and the correction ratio ( ΔT_est/dT) is obtained, and the output of the adder 4a is multiplied by the correction ratio (ΔT_est/dT) by the multiplier 22 to obtain the phase difference correction component Δθref_est as shown in FIG. 6C.

Then, the subtracter 2i subtracts the phase difference correction component Δθref_est from the phase command value (θ_fef)′ to obtain the phase command value θ_ref_ approximated to the pulse generation time.

As described above, according to the second embodiment, when the phase difference between the integral terms is calculated, the time matching between the two phases is performed, so that the “problem to be solved by the invention” is shown (delay time). With respect to the delay time component caused by the asynchronous generation of the pulse generation time and the sample time among the components according to 1), the effect of correcting the phase component corresponding to the delay time difference between the generated pulse and the sample timing of the speed control can be obtained. Therefore, the influence of this delay time can be suppressed for the integral term. As a result, the velocity response characteristic as shown in FIG. 10 can be made closer to the ideal response characteristic when there is no detection delay.

In the second embodiment (FIG. 6), the phase command is corrected and calculated to achieve temporal consistency. However, the problem of the delay time due to the pulse pause period remains, as shown in (Delay time 2) in the column of "Problems to be solved by the invention". In view of this, the third embodiment proposes a countermeasure method for correcting the phase detection by applying the phase prediction corresponding to the elapsed time, and FIG. 7 shows the configuration thereof. This is done by removing the portions ((b) and (c) in FIG. 6) corresponding to the command phase latch circuit inserted in the second embodiment and returning to the original configuration (configuration in FIG. 5), and instead detecting the phase. The following interpolation function is added to.

In FIG. 7, the time Ts at the interrupt timing s is sampled by the latch circuit 1q, and the elapsed time (the number of clocks) from the last pulse generation time Tpp to the interrupt time Ts is calculated by the subtractor 2h (Ts-Tpp). Ask as. Since this is the time delay component to be phase-corrected, the multiplier 23 receives ΔT_est (second time difference) obtained by multiplying the elapsed time (Ts-Tpp) by the coefficient Tclk of the multiplier 20b and the previous speed detection value ω_det. To obtain the predicted amount Δθ_est of the phase that changes during the elapsed time (Ts−Tpp). Then, this is added to the phase θ_det at the pulse generation time by the adder 4h and regarded as the corrected phase detection value θ_destest at the interrupt (sample) time.

Here, since the predicted amount of phase Δθ_est should be less than the pulse resolution θ_step=2π/(4·Npp), considering the case where noise is mixed in the pulse signal and the speed detection becomes abnormal, for protection, The phase limiter 25 applies a limiter of |θ_step| to each of the positive and negative directions (by limiting the width to ±θ_step) to prevent an excessive θ_dest. Accordingly, the correction value θ_destest for phase detection does not become excessively large even when the speed detection is abnormal.

In FIG. 7, a low pass filter 26 is provided between the coefficient unit 3 and the adder 4b.

As described above, the configuration of the third embodiment is to correct the velocity detection phase based on the information on the sample time and the pulse generation time at which the velocity calculation process is performed. According to the third embodiment, it is possible to match the simultaneity between the phase command and the phase detection time.

Further, according to the third embodiment, there is a feature that it can function even in the pulse pause period. Because the sample time Ts is updated for each interrupt signal, ΔT_est (second time difference) and Δθ_est (predicted amount of phase) are also updated continuously. Therefore, even during the pulse pause period, the correction component of Δθ_est increases with respect to the phase detection θ_det that holds the previous value, so that the corrected phase detection value θ_destest that is the combined result of these is updated. Work to continue.

As a result, the component of (delay time 2) described in the section "Problems to be solved by the invention" can be suppressed. As a result, in the speed control system to which the speed PI control is applied, only the integral term can be approximated so that the influence of the delay time of speed detection becomes zero.

Further, by moving the Kps or 1/Kps terms scattered at each location in FIG. 7, it is possible to convert into an equivalent circuit as shown in FIG. In FIG. 7, the PI control calculation is performed using the torque unit, but when the torque unit is divided by the proportional gain Kps, it becomes the unit of speed (speed difference). Therefore, in FIG. 8, the symbols of the proportional term and the integral term are also included. It is replaced with "τ"→"Δω". In addition, the torque limiter value is also multiplied by (1/Kps) and converted into a unit of speed in order to obtain matching by moving Kps (speed limiter 35).

Explaining the part of FIG. 8 different from FIG. 7, the output of the subtractor 2a becomes Δω_p=τ_p/Kps, the output of the adder 4b becomes (Δω_p+Δω_i), the output of the subtractor 2c becomes Δω_fb, and the low-pass filter 26 Δω_i=τ_i/Kps on the input side, and at the location where the torque limiter 5 was provided, the speed limiter value ±Δω_lim obtained by multiplying the torque limiter value ±τ_lim by 1/Kps is used. 35 is provided, and the output of the speed limiter 35 is multiplied by Kps before the low pass filter 15 to be converted into torque.

Although FIG. 7 and FIG. 8 are completely functionally equivalent, the number of operations such as multiplication can be reduced in FIG.

From the above, the second embodiment and the third embodiment have almost the same performance as the first embodiment. In the second embodiment, since only the time difference component smaller than the sample period dT is corrected, the minute portion is corrected. Is ignored, the characteristics are almost the same as those in the first embodiment.

Further, the difference between the second embodiment and the third embodiment is a part of the speed range where the pulse is stopped by decelerating, and the characteristics are the same in the speed range where the pulse is not stopped. The comparison between the simulation results of Example 1 and Example 2 showed that the difference was very small, and that Example 3 was able to confirm both the improvement effect of Example 2 and the improvement effect in the low speed range. As a result, an operation example of the system of the third embodiment will be shown.

First, the "case in which only the speed detection method portion of the second embodiment is combined with the conventional example 1" is taken as a conventional example, while the "method of the third embodiment" is used as a representative example of the proposed method, and these two types are used. The response characteristics of the methods are compared. As for the evaluation conditions, two types of speed command patterns were set: a condition of accelerating to the rated speed and a condition of decelerating in the low speed region.

The first evaluation condition was to accelerate from 0 to 50% and 100% in order to investigate the component of the delay time (1) shown in the column of "Problems to be solved by the invention", and to obtain a steady speed. We are investigating the effect of suppressing the amount of overshoot and the accumulation of error in the integral term when shifting to. FIG. 11 is a comparison of the speed control characteristics of the two types of methods, and FIG. 12 is an investigation of the characteristics of the proportional term and integral term of the speed control and the output torque command.

Comparing FIG. 11, in the case of accelerating from 0% to 50%, the overshoot amount is smaller in the third embodiment shown in (b), and there is no delay time in the PI control characteristics of FIG. The result is similar to the ideal speed detection characteristic (characteristic line (2)).

FIG. 12 compares the torque command elements of the proportional term and the integral term inside the speed control under the same conditions. Since the integral term itself does not exist in Conventional Example 1, the component (τpio−τ_p) obtained by subtracting the proportional component from the output torque is regarded as the integral term τ_i.

In Fig. (a), which is the characteristic when the conventional example 1 is used, there is an error that the integral term at the time of acceleration becomes large due to the velocity detection delay component, and this integral term is decreased when shifting to the steady speed. Therefore, τ_p swings to a large negative value. On the other hand, in the diagram (b) of the third embodiment, it can be confirmed that there is almost no error component in which the integral term increases during acceleration, and the accumulated amount of error due to the speed detection delay is suppressed. Therefore, the amount of τ_p term swinging negatively is small even when shifting to the steady speed.

Further, when accelerating from 50% to 100%, the torque command is limited to the torque limiter value (τ_lim=2.0 pu). When this torque limiter operates, even if the amount of accumulation of the integral term increases, it is limited by the feedback by the torque limiter, so that the characteristics of both speed and torque in FIGS. .. Since the characteristics are almost the same when the torque limiter is operating in FIGS. (a) and (b), it can be confirmed that both are operating normally as the speed type PI control. It was also confirmed that the control functions are equivalent.

As the second evaluation condition, in order to investigate the characteristics of the pulse pause period of the delay time (2) shown in the column of "Problems to be solved by the invention", after accelerating from 0 to 5%, the value was changed to 1%. We are investigating the stability of the speed control system and the effect of suppressing the error accumulation of the integral term by decelerating to generate a pulse pause state. Similar to FIG. 12, FIG. 13 compares the speed control characteristics of the two types of systems, and FIG. 14 illustrates the characteristics of the proportional term and integral term of the speed control and the output torque command. The rated speed of the rotating machine used was 1180 [rpm] and the encoder was set to low resolution with Npp=128 [p/r]. The pulse cycle of the encoder at 1% speed is 39.7 ms (the pulse interval between the A phase and the B phase is 9.9 ms), while the speed control cycle is 1 ms. Therefore, the characteristics of FIGS. 13 and 14 operate in the region including the pulse pause period.

When decelerating from 5% to 1% in FIGS. 13 and 14, torque correction stops when the speed detection recognizes zero when the pulse is stopped in FIG. 13A, and the actual speed tends to overshoot negatively. However, since the extremely low speed region continues, the pulse pause period becomes longer, and an abnormal value occurs in the speed detection (thick solid line). On the other hand, in the diagram (b), the actual speed during deceleration has little overshoot and can be controlled stably, and according to the method of the third embodiment, the correction operation for phase detection is performed even during the pulse pause period. It can be seen that the stability of speed control can be realized by being continued.

1a-1r... Sampler 2a-2i... Subtractor 3... Coefficient device 4a-4h... Adder 5... Torque limiter 11a-11i... Latch circuit 12a, 21... Divider 15, 26... Low pass filter 16... Edge detection part 17... Phase counter 18, 20a, 20b, 22, 23... Multiplier 19... Time counter 25... Phase limiter 30... Sampling cycle generator 35... Velocity limiter

Claims (5)

In the speed control system of the rotating machine to which the speed detection using the pulse encoder and the speed-type proportional-plus-integral control method are applied,
The torque command component (τ_p) of the proportional term of the proportional-plus-integral control method is obtained by multiplying the difference between the speed command value (ω_ref) and the detected speed value (ω_det) by the proportional gain (Kps),
The torque command component (τ_i) of the integral term of the proportional-plus-integral control method is added to the speed command value (ω_ref) and the correction amount (Δω_fb) of the speed command value, and the phase command value ( (Θ_ref)′) is calculated, and a proportional gain (Kps) and a coefficient gain (dT/d) corresponding to an integration time constant are calculated with respect to the difference between the phase command value ((θ_ref)′) and the phase detection value (θ_det). It is calculated by multiplying
The torque command component (τ_p) of the proportional term and the torque command component (τ_i) of the integral term are added, and the addition output is passed through the torque limiting unit to output the torque command (τ_pio) of the proportional-integral control,
The correction amount (Δω_fb) of the speed command value is calculated as the torque command correction amount (Δτ_fb) by subtracting the input component of the torque limiting unit from the output component of the torque limiting unit. Then, the speed control system is obtained by multiplying the torque command correction amount (Δτ_fb) by the respective inverse numbers (1/Kps, Tis/dT) of the proportional gain and the coefficient gain corresponding to the integral time constant. .. The speed detection value (ω_det) detects the rising and falling edges of the output pulse of the pulse encoder, counts the detected edges and latches them as a pulse phase value, and the latest pulse phase value and edge A phase difference, which is the difference between the past pulse phase value before the detection timing, is calculated, and a time difference, which is the difference between the latest pulse generation time of the output pulse and the past pulse generation time before the edge detection timing, is calculated, The speed control system according to claim 1, wherein the calculated phase difference is obtained by dividing the calculated phase difference by the calculated time difference. The phase detection value (θ_det) is obtained by detecting each rising edge and falling edge of the output pulse of the pulse encoder to obtain edge detection timing, counting the output pulse at the edge detection timing, and latching as a pulse phase value. Then, it is obtained by reading the latched pulse phase value at the sample timing generated by the sample period generator,
The speed detection value (ω_det) is calculated by calculating a phase difference, which is a difference between the latest phase detection value of the obtained phase detection values (θ_det) and the past phase detection value before the edge detection timing, The clock signal is counted as time information, the time when the count value of the output pulse changes at the edge detection timing is latched, and the latched time is read at the sample timing to generate the pulse generation time (Tpp). And calculating a first time difference that is the difference between the latest pulse generation time and the past pulse generation time before the edge detection timing, and dividing the calculated phase difference by the calculated first time difference. Demanded by
A sample time (Ts) updated at the sample timing is measured from the time information obtained by counting the reference clock signal, and a clock difference (Ts) corresponding to the elapsed time from the pulse generation time (Tpp) to the sample time (Ts). -Tpp) as the second time difference (ΔT_est),
The second time difference is divided by the sampling period (dT) to obtain a correction ratio (ΔT_est/dT), and the correction ratio is added to a value obtained by adding the speed command value (ω_ref) and the correction amount (Δω_fb) of the speed command value. (ΔT_est/dT) is multiplied to obtain the phase difference correction component (Δθref_est),
The phase command value is obtained as a phase command value (θ_ref) approximate to the pulse generation time by subtracting the phase difference correction component (Δθref_est) from the phase command value ((θ_ref)′). The speed control system according to claim 1. The phase detection value (θ_det) is obtained by detecting each rising edge and falling edge of the output pulse of the pulse encoder to obtain edge detection timing, counting the output pulse at the edge detection timing, and latching as a pulse phase value. Then, it is obtained by reading the latched pulse phase value at the sample timing generated by the sample period generator,
The speed detection value (ω_det) is calculated by calculating a phase difference, which is a difference between the latest phase detection value of the obtained phase detection values (θ_det) and the past phase detection value before the edge detection timing, The clock signal is counted as time information, the time when the count value of the output pulse changes at the edge detection timing is latched, and the latched time is read at the sample timing to generate the pulse generation time (Tpp). And calculating a first time difference that is the difference between the latest pulse generation time and the past pulse generation time before the edge detection timing, and dividing the calculated phase difference by the calculated first time difference. Demanded by
A sample time (Ts) updated at the sample timing is measured from the time information obtained by counting the reference clock signal, and a clock difference (Ts) corresponding to the elapsed time from the pulse generation time (Tpp) to the sample time (Ts). -Tpp) as the second time difference (ΔT_est),
The speed detection value (ω_det) is multiplied by the second time difference (ΔT_est) to obtain the predicted amount (Δθ_est) of the phase that changes within the second time difference, and the predicted amount is used as the phase detection value (θ_det). By adding, the corrected phase detection value (θ_destest) at the interrupt time is obtained,
The speed control according to claim 1, wherein the phase detection value (θ_destest) is used in place of the phase detection value (θ_det) to obtain a difference from the phase command value ((θ_ref)′). system. The speed control system according to any one of claims 1 to 4, wherein a low-pass filter is provided on the torque command output side of the proportional-plus-integral control.

Images