JP2002311040A - Speed detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a speed detector capable of detecting an accurate speed even when a duty imbalance and a phase error exist in a bi-phase pulse of an encoder, and responding to a present motor control device by only replacing the speed detector. SOLUTION: The speed detector includes a state determining means for determining four states from an A-phase state, a B-phase state, and output of a code detecting circuit, and four means for storing a time between pulses corresponding to each of the states, calculates a reference value of the time between the pluses by measuring the time between the pulses of the output pulse of a quadrupling circuit and housing in the four means for storing a time between pulses, calculates a time correcting value by comparing data housed in the four means for storing a time between pulses, and corrects the value of a timer storing means 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed detecting device for detecting a speed of a motor by using a signal of an encoder that outputs two-phase pulses.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional speed detecting device for calculating a speed from an encoder pulse. Normally, the speed detection generates a latch signal for each sampling period of the speed control from the control device, and the detection device temporarily stores data obtained by counting the pulses of the encoder at the timing when the latch signal is input, The stored data is transferred according to a read request from the speed control. In FIG. 3, 1
4 is an encoder output pulse signal, 13 is a code signal output from the quadruple circuit, 12 is a quadruple pulse signal, 2 is a count circuit, 3 is an output signal from the counter circuit (2), and a counter value 15 is stored. Is a counter storage unit that outputs 4 is a pulse generating circuit for outputting a reference clock, 5
Is a timer circuit 1 which receives the pulse signal and the latch signal 18 from the pulse generation circuit (4) and measures time. Reference numeral 6 denotes a timer storage unit 1 for storing a signal output from the timer circuit 1. 7 is a quadrupled pulse signal 12
Timer circuit 2 for inputting a clock signal, a latch signal 18 and a reference clock signal output from pulse generating circuit 4 and measuring time
It is. The output of the timer circuit 2 (7) is stored in the timer storage means 2. . The counter circuit (2) inputs the code signal (13), the quadrupled pulse signal, and the latch signal (18) output from the quadruple circuit (1), and measures pulse up / down.

Next, the operation will be described. Conventionally, when the number of pulses that change within the sampling time of speed control is small, such as when using a low-resolution encoder with a small number of pulses or at the time of low-speed operation, detection of the configuration shown in FIG. I was using a bowl. That is, the A and B phases of the output pulse from the encoder are input and multiplied by 4, and then counted by the counter circuit. The pulse generation circuit is a reference clock for measuring time, and the five timer circuits 1
7 is used as an input signal of the timer circuit 2. 7, the value of the timer circuit 2 is reset by the quadrupled pulse signal,
The time since the last quadrupled pulse is input is counted. The counter circuit, the timer circuit 1, and the timer circuit 2 store the current values in the counter storage means (3), the timer storage means 1 of the timer storage means 8, and the timer storage means 2 of the timer storage means 8 in response to a latch signal output from the control device. Remember. The control device reads data stored in the counter storage means (3), the timer storage means 1 (6), and the timer storage means 2 (8) and calculates the speed. The calculation method is shown in Fig. 2.
The method is performed as shown in FIG. That is, the quadrupled count value N (n) at the time of latching from the counter storage means (3), the timer value T1 (n) from the timer storage means 1 (6), and the timer value immediately before latching from the timer storage means 2 (8). The time T2 (n) from the quadrupled pulse to the latch time is read and compared with the previous values (N (n-1), T1 (n-1), T2 (n-1)), and the following equation ( As shown in 1) to (3), the time ΔT and the number of pulses ΔN between the pulse immediately before the previous latch and the pulse immediately before the current latch are obtained, and the encoder pulse frequency F is calculated to obtain the motor speed. I was ΔN = N (n) −N (n−1) (1) ΔT = (T1 (n) −T1 (n−1) −T2 (n) + T2 (n−1)) / Ft (2) F = ΔN / ΔT (3) where Ft is the basic clock frequency of the timer

[0004]

According to the conventional speed detection method, when the two-phase pulse of the encoder has a pulse duty imbalance or a phase error between the two-phase pulses, an encoder having a small number of pulses can be used. Detection and control are performed at a fast sampling cycle that reduces the number of pulses per cycle, and when extremely low speed operation is required, the effect of speed detection error increases and torque ripples occur in the motor. There was a problem. To solve this problem, Japanese Patent Application Laid-Open No. H10-90293 proposes a method of detecting a phase error of a pulse and converting it into the number of pulses to make correction. However, in this method, since not only the detector but also the calculation method is changed, it cannot be used as a replacement for the current speed detection device. Therefore, an object of the present invention is to provide an encoder
Even if the phase pulse has a pulse duty imbalance or a phase error between the two-phase pulses, accurate speed detection is possible, and the current motor control device can be handled only by replacing the speed detection device. An object of the present invention is to provide a speed detecting device.

[0005]

Means for Solving the Problems Two-phase pulses A and B of an encoder for outputting two-phase pulses different in phase by 90 degrees.
A quadruple circuit and a quadruple circuit for inputting a phase, detecting a sign from the states of the A-phase and B-phase pulses, and generating pulses at the rising and falling timings of the A-phase and the B-phase are generated. UP-DOWN by inputting pulse and sign
Counter circuit for counting, counter storage means for latching the value of the counter circuit and storing the counter value, pulse generating circuit for outputting rectangular waves at fixed time intervals, and timer circuit for inputting and counting pulses of the pulse generating circuit 1 and a timer storage means 1 for latching the value of the timer circuit 1 and storing the timer value, and inputting and counting pulses of the pulse generation circuit, and inputting an output pulse of the quadruple circuit to reset the counter value. In a speed detecting device comprising a timer circuit 2 and a timer storage means 2 for latching a value of the timer circuit 2 and storing a timer value,
It has state discriminating means for discriminating four states from the phase state and the output of the code detection circuit, and four inter-pulse time storage means corresponding to each state, and the time between pulses of the output pulse of the quadruple circuit. Is measured and stored in the four inter-pulse time storage means to calculate a reference value of the inter-pulse time, and is compared with the data stored in the four inter-pulse time storage means to calculate a time correction value; A speed detecting device, wherein the value of the timer storage means 2 is corrected. 2. The speed detecting device according to claim 1, further comprising a unit that stops the correction according to the magnitude of the inter-pulse time. The time between pulses of the output pulse of the quadruple circuit was measured and stored in the four inter-pulse time storage means. A reference value of the inter-pulse time was calculated using the four stored values, and the stored value was stored. A time error of each pulse is obtained from four values and the reference value, a ratio of the time difference to a value stored in the four inter-pulse time storage means is stored in an error storage means, and the ratio is stored in the error storage means. 2. The speed detection device according to claim 1, wherein a timer value correction amount is obtained from a product of the calculated value and the average value, and the value of the timer storage means is corrected.
The data set in the error storage means is a ratio of the time difference to the value stored in the four inter-pulse time storage means.
4. The speed detecting device according to claim 3, wherein the value is averaged for each of the two areas. 4. The speed detection device according to claim 3, further comprising a unit that stops storing the error storage unit. The count value and the timer value 1 at the latching time and the timer value 2 from the latching time to the generation of the quadrupled pulse immediately before the latching are output, and the timer value 2 outputs the result obtained by adding the correction of the pulse detection time. I do. As a correction method, the inter-pulse time of a pulse obtained by multiplying the input two-phase pulse by four is measured for four types for each state of the two-phase pulse, and a time error amount is calculated from the average value of the measured results and the current state. Then, the timer value 2 is corrected.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described. FIG. 1 shows a configuration block diagram of the present invention. The same reference numerals as in FIG. 3 of the conventional example denote the same parts, and a duplicate description will be omitted. In FIG. 1, the parts different from the conventional FIG. 3 are a state determination means (9), an inter-pulse time storage means (10), a correction value calculation circuit (11), an OR circuit (19), and an addition circuit (20).
Is provided. Based on the A-phase and B-phase encoder output pulse signals (14) and the code signal (13) output from the quadruple circuit 1, the state determination means 9 sends the A-phase and B-phase data to the inter-pulse time storage means (10). Outputs the previous state obtained from the phase signal LOW-HIGH. Time between pulse storage means (10)
Is a signal output from the state determination means and the timer circuit 2
The signal output from (7) is input and data corresponding to the previous state is output to the correction value calculation circuit 11. The correction value calculation circuit (11) outputs a correction value calculated based on the output signal from the inter-pulse time storage means and the code signal output from the quadruple circuit to the addition circuit 20. The addition circuit 20 adds the output signal of the timer storage means 2 (8) and the output signal of the correction value calculation circuit (11) to obtain a timer 2 value (1
Make 6). The OR circuit 19 outputs the latch signal (18) and 4
The multiplication pulse signal (12) is input, and the logical sum thereof is output as a latch signal of the timer circuit 2.

Next, the operation will be described. The two-phase output pulses A and B of the encoder are input, and the edges of each phase A and B are extracted by a quadruple circuit to generate quadrupled pulses, and the rotation direction (sign) is obtained from the state of the A and B phases. The counter circuit counts UP-DOWN using the obtained quadrupled pulse and the sign.
The pulse generation circuit is a reference clock for measuring time, and is used as an input signal of the timer circuit 1 and the timer circuit 2. The value of the timer circuit 2 is reset by the quadrupled pulse signal, and counts the time since the last quadrupled pulse was input. The latch signal is an output of the control device and is input to the counter circuit, the timer circuit 1, and the timer circuit 2, and stores the values in the counter storage unit, the timer storage unit 1, and the timer storage unit 2, respectively. The state determination means determines four states obtained from the LOW-HIGH of the A and B phase signals using the A and B phase signals and the code, and obtains a previous state from the code. The timer circuit 2 is latched by the quadrupled signal and the latch signal or, and the latched data is stored in the timer storage means 2 in the case of latching by the latch signal, and by the previous state when latched by the quadrupled pulse. Are stored in the four pulse time storage means.

The correction value calculation circuit will be described with reference to FIG. Assuming that the results stored in the four inter-pulse time storage means are S1, S2, S3, and S4, respectively,
Find S (n-1). S (n-1) = (S1 + S2 + S3 + S4) / 4 (4) In FIG. 4, since the state at the time of latch (n-1) is the S3 area,
The value of the timer 2 from the end of the two areas to the latch time is stored in the timer storage means 2 (T2 (n-1)). The correction amount Terr (n-1) for this data is obtained by Terr (n-1) = S (n-1) × 2− (S1 + S2) (5) based on S1, and the timer 2 value T2 ′ after the correction is obtained. (n-1) is obtained by the following equation. T2 '(n-1) = T2 (n-1) + Terr (n-1) (6) At the next latch (n), the average value S (n) is obtained in the same manner.
A correction value Terr (n) is obtained based on 1 and T2 (n) is corrected by correcting T2 (n). S (n) = (S1 + S2 + S3 + S4) / 4 (7) Terr (n) = S (n) × 3− (S1 + S2 + S3) (8) T′2 (n) = T2 ( n) + Terr (n) (9) Terr (n) is obtained using data from S1 to S3 since the latch (n) point is in the S4 area.

If the calculation of the correction amount is in the reverse rotation, the correction amount is obtained by using the value obtained by adding S3 and S2 in the order of updating based on S4. For example, if the latch time is in the S2 region, the correction amount Terr is expressed by the following equation using S4 and S3. S = (S1 + S2 + S3 + S4) / 4 (10) Terr = S * 2-(S4 + S3) (11) When the motor speed increases, S1, S2, S3, and S4 approach 0. Therefore, the correction hardly works, but the error becomes small because the encoder pulse between the latches increases. Since the motor speed becomes slow and the timer circuit may overflow, it is necessary in this case not to perform the correction itself. Although the maximum value that the timer circuit 2 can take is the limit of the error correction circuit of the detection device according to the present invention, the effect is small since it only returns to the conventional method. Claim 3
Then, the ratio between the correction amount Terr and the average value is stored in the error storage unit as an error correction count of the current area, and the timer value correction amount is obtained from the product of the value stored in the error storage unit and the average value. In this way, error correction is performed.

Assuming that the average value of the four areas is S and the errors in each area are Terr1, Terr2, Terr3, and Terr4, the error correction counts kerr1, kerr2, kerr3, and kerr4 in each area are the error correction counts in the S1 area: kerr1 = Terr1 / S (12) Error correction count for S2 area: kerr2 = Terr2 / S (13) Error correction count for S3 area: kerr3 = Terr3 / S (14) Error correction count for S4 area: kerr4 = Terr4 / S (15) Becomes This is calculated each time a quadrupled pulse arrives, and the result of averaging (eg, first-order lag processing) is stored in the error storage means. Assuming that the data stored in the error storage means are K1, K2, K3, and K4, the correction to T2 can be obtained by the average value S and the error correction count. In the case of the S2 area, T2 ′ = T2 + S × K2 (16) Here, K1, K2, K3, K4 are obtained by rotating the motor at a constant speed in advance and stored in the error storage means, and when actually used, stop storing in the error storage means, If the correction is performed using the value obtained in advance, accurate error correction can be performed even when the motor speed fluctuates greatly.

The control device latches the quadrupled count value N (n) at the time of latching from the counter storage means, the timer value T1 (n) from the timer storage means 1, and the quadrupled pulse immediately before the latch from the timer storage means 2. The value T2 '(n) obtained by adding the correction to the time up to the time point is read and compared with the previous values (N (n-1), T1 (n-1), T2 (n-1)), and (1) It is calculated by the formulas (2) and (3).

[0012]

As described above, according to the present invention, two A-phase and B-phase pulses of the encoder for outputting two-phase pulses having a phase difference of 90 degrees are inputted, and the A-phase and the B-phase pulses are inputted. Detecting a sign from the state of the pulse and generating a pulse at the rising and falling timings of the A-phase and the B-phase 4
A multiplying circuit, a counter circuit for inputting pulses and codes generated by the quadruple circuit and counting up and down, a counter storing means for latching the value of the counter circuit and storing the counter value, and a rectangular wave at a constant time interval. A pulse generating circuit to be output, a timer circuit 1 for inputting and counting the pulses of the pulse generating circuit, a timer storage means 1 for latching the value of the timer circuit 1 and storing the timer value, and a pulse for the pulse generating circuit. And a timer circuit 2 for inputting an output pulse of the quadruple circuit and resetting a counter value, and a timer storage means 2 for latching the value of the timer circuit 2 and storing the timer value. State determining means for determining four states from the A-phase and B-phase states and the output of the code detection circuit, and four inter-pulse times corresponding to each state. Having a storage means, measuring the time between pulses of the output pulse of the quadruple circuit, storing the measured time in the four-pulse time storage means and calculating a reference value of the inter-pulse time, Since the time correction value is calculated by comparing with the data stored in the storage means and the value of the timer storage means 2 is corrected, the duty imbalance of the pulse to the two-phase pulse of the encoder or the two-phase pulse Even when there is a phase error between the two, the correction of the timer value enables accurate speed detection. Furthermore, when the speed detection device according to the present invention is applied to the existing control device, the timer value is corrected in advance in the speed detection device, so that the speed calculation is not corrected,
You will be able to calculate the exact speed.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating a conventional method of calculating a speed from an encoder pulse.

FIG. 3 is a block diagram of a conventional speed detection device.

FIG. 4 is a diagram illustrating a method for correcting an encoder pulse according to the present invention.

[Explanation of symbols]

 1 4 Multiplying circuit 2 Counter circuit 3 Counter storing means 4 Pulse generating circuit 5 Timer circuit 1 6 Timer storing means 1 7 Timer circuit 2 8 Timer storing means 2 9 State discriminating means 10 Inter-pulse time storing means 11 Correction value calculating circuit 12 4 Multiplier pulse signal 13 Code signal 14 Encoder output pulse signal 15 Counter value 16 Timer 2 value 17 Timer 1 value 18 Latch signal 19 OR circuit 20 Adder circuit

Claims (5)

[Claims] An encoder which outputs two-phase pulses having phases different from each other by 90 degrees receives two-phase pulses A and B, and detects a sign from the states of the A-phase and B-phase pulses to detect the A-phase and B-phase pulses. A quadruple circuit that generates pulses at the rising and falling timings of the phase and the B phase, a counter circuit that inputs the pulse and sign generated by the quadruple circuit and counts up and down, and latches the value of the counter circuit Counter storing means for storing a counter value, a pulse generating circuit for outputting a rectangular wave at fixed time intervals, a timer circuit 1 for inputting and counting pulses of the pulse generating circuit, and a timer for latching the value of the timer circuit 1 Timer storage means 1 for storing a value and a timer for inputting and counting pulses of the pulse generation circuit, and for inputting an output pulse of the quadruple circuit to reset a counter value A speed detection device comprising a path 2 and a timer storage means 2 for latching a value of the timer circuit 2 and storing a timer value, wherein four states are obtained from the A-phase and B-phase states and the output of the sign detection circuit. And four inter-pulse time storage means corresponding to each state. The time between pulses of the output pulse of the quadruple circuit is measured and stored in the four inter-pulse time storage means. And calculating a time correction value by comparing the reference value of the inter-pulse time with the data stored in the four inter-pulse time storage means, and correcting the value of the timer storage means 2. Speed detector. 2. The speed detecting apparatus according to claim 1, further comprising means for stopping the correction according to the magnitude of the inter-pulse time. 3. The time between pulses of the output pulse of the quadruple circuit is measured and stored in the four inter-pulse time storage means, and a reference value of the inter-pulse time is calculated using the four stored values. Calculating a time error of each pulse from the stored four values and the reference value; storing a ratio between the time difference and a value stored in the four inter-pulse time storage means in an error storage means; 2. The speed detection device according to claim 1, wherein a timer value correction amount is obtained from a product of the value stored in the storage unit and the average value, and the value in the timer storage unit is corrected. 4. The data set in the error storage means,
4. The speed detecting apparatus according to claim 3, wherein a ratio between the time difference and a value stored in the four pulse time storage means is a value averaged for each of four regions. 5. The speed detecting device according to claim 3, further comprising means for stopping storage of said error storing means.