JP2009164938A - Speed determining method, speed determining circuit and speed determining device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide: a speed determining method which determines a transmission speed faster than a conventional art; a speed determining circuit; and a speed determining device. <P>SOLUTION: The speed determining device comprises: delay elements 2, 3 for generating two signals having a delay difference equivalent to an integral multiple of a pattern cycle of a preamble signal included in an input signal into an input terminal 1; a coincidence detector 4 for comparing logics of the two signals outputted from the delay elements 2, 3; an integration circuit 6 for integrating an output signal of the coincidence detector 4; and a comparator 7 for comparing a signal obtained by the integration circuit 6 with a threshold value Vref to output a determination result. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a method, a circuit, and an apparatus for determining a transmission speed of a signal being transmitted in a signal transmission system in which it is not known which signal has a plurality of transmission speeds (bit rates). In addition, the present invention relates to a method, circuit, and apparatus for determining a transmission speed at high speed in a signal transmission system in which the transmission speed changes at high speed.

  With the spread of the Internet, services with various transmission speeds are provided by telecommunications carriers. However, since different transmission apparatuses are used for different transmission speeds, maintenance operation costs are increasing. In order to prevent this cost increase, there is a demand for a single transmission device. A transmission apparatus capable of supporting a plurality of transmission speeds has been proposed, and a mechanism for determining the transmission speed inside the apparatus (Patent Document 1) and switching the light receiving sensitivity according to the speed has also been proposed (Patent Document 2).

  These speed judgment circuits for judging the transmission speed are roughly classified into two types. Output the edge part of the signal (the logic code switching part of “0” / “1”) as a pulse with a fixed time width, and integrate it over time to specify the signal switching frequency (ie, transmission speed) (Patent Document 1: hereinafter referred to as an edge detection method) or a method for specifying a transmission rate by detecting a low-frequency component of the same sign continuous signal included in a signal (Patent Document 2: hereinafter, a low frequency) It is called a detection method). In both systems, after specifying the transmission rate, it is assumed that the transmission rate is constantly used at the specified transmission rate, and it is not intended to follow the transmission rate that changes every moment at high speed. This is due to the following reason.

  The edge detection method detects an edge portion of a signal, but the density of the edge varies depending on the same sign sequence included in the signal. Even if the signal is a low-speed signal, a certain level of edge density can be obtained. For this reason, in order to improve the determination accuracy, it is necessary to perform statistical determination over a certain amount of time (generally, a time of about 10,000 to 1 million bits), so the integration time of the edge signal Will become longer. The low-frequency detection method detects low-frequency components as the name suggests, so the band of the low-pass transmission filter needs to be low, and the time constant of this filter is as large as the integration circuit in the edge detection method. It becomes an order.

In recent years, point-to-multipoint networks that handle multiple users with a single in-station device have become widespread, and with the diversification of transmission speeds, there is an increasing demand for accommodating users with different transmission speeds. For the above reason, it is difficult to realize a function for determining an immediate transmission rate for a signal whose transmission rate is switched at high speed using a conventional speed determination circuit.
JP 2000-40960 A WO 2005/078927

  As described above, since the speed determination circuit of the prior art takes time to determine, in the signal transmission method in which the transmission speed changes at high speed with time, the transmission speed cannot be determined at high speed.

  An object of the present invention is to provide a speed determination method, a speed determination circuit, and a speed determination device that can determine a transmission speed at a higher speed than the prior art.

In order to achieve the above object, the speed judging method of the invention according to claim 1 judges the speed of the input signal by discriminating the repetition of the same pattern in the unique preamble signal included in the input signal. It is characterized by.
The invention according to claim 2 is the speed determination method according to claim 1, wherein the repetition of the same pattern is converted into a continuous signal of the same sign, and the threshold signal is determined by integrating the continuous signal of the same sign, whereby the preamble signal is obtained. The signal speed is discriminated within the reception time.
According to a third aspect of the present invention, there is provided a speed judging circuit comprising: delay means for generating two signals having a delay difference corresponding to an integral multiple of a pattern period of a specific preamble signal included in the input signal from the input signal; A coincidence detecting means for comparing the logics of the two signals output from the means, an integrating means for integrating the output signal of the coincidence detecting means, and a signal obtained by the integrating means is compared with a threshold value and a determination result is output. And a comparison means.
According to a fourth aspect of the present invention, there is provided a speed determination circuit that generates two signals having a delay difference corresponding to an odd multiple of one half of a pattern period of a specific preamble signal included in the input signal from the input signal. A non-coincidence detection unit that compares the logic of the two signals output from the delay unit, an integration unit that integrates the output signal of the non-coincidence detection unit, and a signal obtained by the integration unit is compared with a threshold value. And a comparison means for outputting the determination result.
The invention according to claim 5 is the speed determination circuit according to claim 3 or 4, wherein the integration means is set with an integration time constant corresponding to a preamble signal reception time of a signal having a transmission speed to be determined. It is characterized by being.
According to a sixth aspect of the present invention, there is provided a speed judging apparatus comprising: a plurality of speed judging circuits according to the third, fourth, or fifth aspect connected to a common input terminal; It is characterized in that a plurality of speeds can be determined by setting different integration time constants.
According to a seventh aspect of the present invention, there is provided a speed judgment device comprising a storage circuit for storing the judgment result of the speed judgment circuit according to the third, fourth, fifth or sixth aspect, the storage circuit before the judgment result is changed. The determination result is held.
The invention according to claim 8 is the speed determination apparatus according to claim 7 quoting claim 6, wherein among the plurality of speed determination circuits to be used, two or more speed determination circuits are transmission rates that they are responsible for. When the determination is made at the same time, priority is given to the determination of the speed determination circuit in charge of determining the fastest signal among the two or more speed determination circuits.
The invention according to claim 9 is the speed determination device according to claim 7, wherein one speed determination circuit according to claim 3 is a speed determination circuit for a low speed signal, and one speed determination circuit according to claim 4 is provided. As a high-speed signal speed determination circuit, each of which is connected to a common input terminal, and pulse compression means for compressing the determination output signal of the speed determination circuit according to claim 3 at the rising edge portion is provided. And

  According to the present invention, instead of integrating and determining a logic code including “0” and “1” generated from a random code to some extent as in the conventional circuit, when the signal transmission speed changes, This is to determine the repetition of the same pattern of the known preamble signal added to the head part. More specifically, the repetition of the same pattern is converted into the same code continuous signal, and is longer than the same code continuous length included in the signal. However, the integration time is generated by generating a continuous signal of the same sign (with a length of about several tens of bits to several thousand bits) that is one to three digits shorter than the time constant required for the conventional circuit. Since it can be shortened to the same length as the same code continuous signal length, the speed can be determined at high speed within the preamble signal reception time.

<First embodiment>
FIG. 1 shows the configuration of a speed determination circuit according to the first embodiment of the present invention. In the figure, 1 is an input terminal, 2 is a delay element, 4 is a coincidence detection circuit (exclusive NOR circuit), 5 is a termination circuit, 6 is an integration circuit (time constant is τ ₀ ), 7 Denotes a comparison circuit, 8 denotes a power source or ground, 9 denotes a reference potential input terminal, and 10 denotes an output terminal (the alphabetical explanation in the figure is described in the explanatory text of FIG. 2). In this embodiment, for the sake of simplicity, the speed of the transmitted signal is assumed to be high and low.

First, the delay elements 2 and 3 connected to the nodes A and B of the coincidence detection circuit 4 are such that the delay time difference between the delay elements 2 and 3 is the repetition period of the same pattern of the preamble signal of the high-speed signal input to this circuit. The length is adjusted to an integer multiple of. In the figure, for the sake of convenience, an example is shown in which both delay elements 2 and 3 are connected. However, as long as the delay time of one delay element is equal to the integral multiple of the length, only one of the delay elements may be used. Moreover, although the input side terminals of the delay elements 2 and 3 are shown as being connected to the input terminal 1, they may be physically separated from each other. Further, when a differential input signal is input instead of an in-phase input signal, the same effect can be obtained by changing the coincidence detection circuit 4 to an exclusive OR circuit. The integration circuit 6 can be omitted if the comparison rotation 7 has a response speed equivalent to the time constant (τ ₀ ) of the integration circuit 6.

FIG. 2 is a time chart showing the operation of the first embodiment of the present invention. The reference numerals in the figure indicate the potentials of the nodes indicated by the same reference numerals shown in FIG. FIG. 2A shows the operation when a high speed signal is input to the first embodiment, and FIG. 2B shows the operation when a low speed signal is input. As shown in FIG. 2A, here, the preamble period is 6 bits of “110010”, and a delay time difference D _{0 corresponding} to 6 bits (one time of the preamble pattern period) is provided between the delay elements 2 and 3. When the operation is shown. The signals of the nodes A and B are input to the coincidence detection circuit 4 with a delay time difference D ₀ , and the output is output to the node C as a potential. The part that moves from the no-signal state to the head part of the preamble outputs the code “0” due to the mismatch for one period, but the preamble part is the same code continuation of the code “1” (part indicated by τ ₀ in the figure). I understand that

The integration circuit 6 is designed so that its time constant is about τ _0, so that it reacts to the same sign sequence having a length of the preamble and exceeds the threshold value (reference potential: Vref) of the comparison circuit 7 at the node D. Potential can be output. After that, when a random signal in the payload portion is input, the coincidence output outputs coincidence between the signals with a mark ratio of 1/2, so the output signal also becomes the mark ratio with a probability of 1/2, and integration of the node D The output is half of “1” when the same sign is continuous (strictly, (VH + VL) / 2, where VH represents the HI potential of the logical code “1” and VL represents the LOW potential of the code “0”). Drops to potential. As a result, a pulse signal having a finite width having a rising edge in the middle of the preamble is output to the output terminal 10 of the comparison circuit 7.

  On the other hand, as shown in FIG. 2B, when a low speed signal is input, the delay time difference between the nodes A and B is the preamble cycle of the low speed signal (here, the same pattern as the high speed signal and the speed is 3 minutes). Therefore, the coincidence output of the preamble portion does not have the same sign continuation of “1” (in this case, the signal has a mark rate of 1/3). For this reason, since the output of the integration circuit 6 does not exceed the threshold value of the comparison circuit 7, no pulse signal is output to the output terminal 10 of the comparison circuit 7.

  As described above, by using the configuration of the first embodiment, a speed determination circuit that outputs a pulse when receiving a preamble portion of a signal of a specific bit rate without reacting to a lower-speed signal is configured. I can do it. However, if the low-speed signal contains the same sign continuation as the preamble length of the high-speed signal, the integrated value of the coincidence output of the same sign continuation part may exceed the threshold value, so the same sign continuation length of the low-speed signal It is effective only when the preamble length of the high-speed signal is sufficiently long. In the figure, the length of the no-signal state before the signal input is negligibly short. Therefore, the initial value of the node D is the output potential ((VH + VL) / 2) for the payload portion of the previous signal. However, when there is no signal state longer than the preamble length of the high-speed signal between the signals, the operation is the same as the same code continuity. However, in this case, since the determination result is output in the non-signal portion that is not the preamble portion, there is no particular problem.

<Second embodiment>
FIG. 3 shows a configuration of a speed determination circuit according to the second embodiment of the present invention. In the figure, components similar to those in FIG. 1 are denoted by the same reference numerals, 11 and 12 are delay elements, and 13 is an integration circuit (time constant is τ ₁ ). Also in this embodiment, there are two types of transmitted signal speeds, high and low. The configuration of FIG. 3 is substantially the same as the configuration of FIG. 1 except that the delay time difference between the delay elements 11 and 12 is adjusted to a length that is an integral multiple of the pattern period of the preamble signal of the low-speed signal. In the drawing, for the sake of convenience, an example is shown in which both delay elements 11 and 12 are connected. However, if the delay of one delay element is equal to the integral multiple of the length, only one of the delay elements may be used. Moreover, although the input side terminals of the delay elements 11 and 12 are shown as being connected to the input terminal 1, they may be physically separated from each other. Further, when a differential input signal is input instead of an in-phase input signal, the same effect can be obtained by changing the coincidence detection circuit 4 to an exclusive OR circuit. The integration circuit 13 can be omitted if the comparison circuit 7 has a response speed equivalent to the time constant (τ ₁ ) of the integration circuit 13.

FIG. 4 is a time chart showing the operation of the second embodiment of the present invention. The reference numerals in the figure indicate the potentials of the nodes indicated by the same reference numerals shown in FIG. FIG. 4A shows the operation when a low speed signal is input to the second embodiment, and FIG. 4B shows the operation when a high speed signal is input. As shown in FIG. 4A, the preamble period is 6 bits of “110010” here, and a delay time difference D _{1 corresponding} to 6 bits (one time of the preamble pattern period) is provided between the delay elements 11 and 12. When the operation is shown. As in the description of FIG. 2A, it is clear that a pulse signal having a finite width having a rising edge in the middle of the preamble is output to the output terminal 10 of the comparison circuit 7.

On the other hand, when a high-speed signal is input, if the preamble period of the low-speed signal is not an integral multiple of the preamble period of the high-speed signal, the coincidence output of the preamble part is the same sign continuous as described in FIG. Therefore, the output of the integration circuit 13 does not exceed the threshold value of the comparison circuit 7. However, as shown in FIG. 4B, when the preamble period of the low-speed signal is an integral multiple (three times) of the preamble period of the high-speed signal, the coincidence output becomes the same code sequence. If the time constant τ ₁ of the integration circuit 13 is set to a value substantially equal to the preamble length of the low-speed signal, the preamble length of the high-speed signal generally becomes shorter in inverse proportion to the transmission speed, so that τ ₀ <τ ₁ . Assuming that the integrated value of the coincidence output decreases in the payload portion, the continuous code having a length of about τ ₀ does not sufficiently exceed the threshold value, and finally the threshold value is exceeded by the continuous code having a length of about τ _1. By setting the threshold voltage (reference potential Vref) in this way, it is possible to adjust so as not to output a pulse signal having a finite width having a rising edge in the middle of the preamble with respect to the input of the high-speed signal.

  As described above, by using the configuration of the second embodiment, a speed determination circuit that outputs a pulse to a preamble portion of a signal having a specific bit rate without reacting to a higher-speed signal is configured. I can do it. Similar to the first embodiment, when the high-speed signal includes the same code continuation as much as the preamble length of the low-speed signal, the integrated value of the coincidence output of the same code continuation part may exceed the threshold value. This is effective only when the preamble length of the low-speed signal is sufficiently longer than the same-code continuous length of the signal. 4, the length of the no-signal state before the signal input is negligibly short as in FIG. 2, and the initial value of the node D is the output potential ((VH + VL) / 2) for the payload portion of the previous signal. It was. However, if there is a no-signal state longer than the preamble length of the low-speed signal between the signals, it operates in the same way as the same sign continuation, but the determination result is output in the no-signal part that is not the preamble part. So there is no problem as well. However, in this case, if the preamble period of the low-speed signal is an integral multiple of the preamble period of the high-speed signal at the same time, there is a possibility that the determination result pulse is output so as to be applied to the preamble portion of the high-speed signal following the no signal. A countermeasure against the determination malfunction in this case will be described in the description of the fourth and subsequent embodiments.

  As is apparent from the description of the operations of the first and second embodiments, an integration circuit having a delay time difference that is an integral multiple of the preamble period of a signal of a specific bit rate at the input section and having a time constant of about the preamble length is provided. If used, it is possible to output a finite width pulse having a rising edge when receiving the preamble portion of the signal of the specific bit rate without reacting to a signal higher or lower than the specific bit rate. In other words, since it can only be determined whether or not the bit rate is a specific bit rate, it is necessary to perform determination using a plurality of speed determination circuits of the present invention in order to specify the bit rate of the input signal. . Further, since the output pulse is turned off in the payload portion, a storage circuit for holding the determination result is required until the determination result of the next signal is obtained. These will be described later.

<Third embodiment>
FIG. 5 shows the configuration of the speed determining apparatus according to the third embodiment of the present invention. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals, 14 and 15 are speed judgment circuits of the first or second embodiment of the present invention, 16 is a reset set flip-flop circuit (RS-FF), Reference numeral 17 denotes an inverting output terminal. FIG. 6 is a time chart showing the operation of the third embodiment, and the reference numerals in the figure indicate the potentials of the nodes indicated by the same reference numerals shown in FIG. Assume that the speed determination circuits 14 and 15 are circuits for determining different speed signals (14 in FIG. 6 is a speed determination circuit for a low speed signal). When each speed determination circuit 14, 15 outputs a pulse signal as a determination signal at the preamble portion of each speed signal, signals as shown in FIG. 6 are obtained at the output terminal 10 and the inverted output terminal 17, and the flip-flop 16 is held. With this output signal, it is possible to determine which speed signal is being input.

<Fourth embodiment>
FIG. 7 is a time chart showing the malfunction of the third embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 6 denote the same reference numerals, and 18 denotes a malfunctioning portion. As described above, when a no-signal state longer than the preamble length of the low-speed signal exists between the signals, there is a possibility that a determination result pulse is output to the no-signal portion. In this case, since “1” is simultaneously input to the S terminal and the R terminal of the flip-flop circuit 16, there is a possibility of malfunction.

  Further, the integration circuit 13 of the low-speed signal speed determination circuit 14 has a longer time constant than the integration circuit 6 of the high-speed signal speed determination circuit 15, so that the high-speed signal speed determination circuit 15 outputs depending on the setting of the time constant. The falling edge after the long no-signal state (at the head portion of the high-speed signal) output by the low-speed signal speed determination circuit 14 is slower than the falling edge after the completion of the preamble of the high-speed signal. In this case, an error occurs in the determination result of the flip-flop 16 (reference numeral 18 in FIG. 7).

  FIG. 8 shows the configuration of the speed determination device according to the fourth embodiment of the present invention. In the figure, the same elements as those in FIG. 5 are denoted by the same reference numerals, 19 and 20 are delay elements, 21 is a negation circuit, and 22 is a logical product circuit (the alphabetical explanation in the figure is described in the explanatory text of FIG. 9). ). In FIG. 8, delay elements 19 and 20 for correcting the deviation of the falling edge due to the time constant difference of the integration circuit are attached to the output portions of the speed determination circuits 14 and 15 to compensate for the malfunction (falling). Edges are aligned). In the figure, for the sake of convenience, an example in which both delay elements 19 and 20 are connected is shown. However, if one of the delay elements has the same falling edge, only one of the delay elements may be used. Further, when “1” is input to the R terminal so that the prohibition input is not input to the flip-flop circuit 16, the input on the S terminal side is forcibly converted to “0” using the NOT circuit 21 and the AND circuit 22. is doing. This is because when “1” is simultaneously input to the S terminal and the R terminal, the high-speed signal is being input.

  FIG. 9 is a time chart showing the operation of the fourth embodiment of the present invention. Reference numerals in the figure indicate node potentials indicated by the same reference numerals shown in FIG. It can be seen that a correct determination result can be obtained because there is no longer a no-signal state from the S terminal side input and an erroneous determination output immediately after the no-signal state. The relative time difference between the determination signal and the input signal due to the insertion of the delay elements 19 and 20 may be corrected on the signal side using a delay or the like.

  FIG. 10 is a time chart showing a malfunction of the fourth embodiment of the present invention. The reference numerals in the figure are the same as those in FIG. If there is a no-signal state longer than the preamble length of the low-speed signal and the preamble period of the low-speed signal is an integral multiple of the preamble period of the high-speed signal at the same time, There is a possibility of outputting a pulse. In this case, the falling edge output from the speed determination circuit 14 of the low-speed signal causes an erroneous determination beyond the correction by the delay elements 19 and 20 of the fourth embodiment.

  FIG. 11 is a time chart showing the operation of the application example of the fourth embodiment of the present invention. The reference numerals in the figure indicate the same as in FIG. 10, and reference numeral 23 denotes a time difference between falling edges of pulses output by the speed judgment circuit when a low speed signal is input after a no-signal state longer than the preamble length of the low speed signal. , Indicate. In this application example, the value of the delay time difference between the delay elements 19 and 20 is corrected by adding the delay time corresponding to the preamble length of the high-speed signal to the value used in FIG. As a result, after the no-signal state longer than the preamble length of the low-speed signal, the time difference 23 of the falling edge of the pulse output by the speed judgment circuit when the low-speed signal is input is sufficiently reduced by the AND circuit 22 and the flip-flop 16. It can be seen that a malfunction does not occur if the time difference is such that it operates.

<Fifth embodiment>
FIG. 12 shows the configuration of the speed determination circuit according to the fifth embodiment of the present invention. In the figure, components similar to those in FIG. 1 are denoted by the same reference numerals, 24 and 25 are delay elements, and 26 is a mismatch detection circuit (exclusive OR circuit). Since the coincidence detection circuit 4 has been used up to the fourth embodiment, the coincidence detection circuit 4 outputs the same sign continuation of “1” for the same sign continuation or no signal state longer than the preamble, causing erroneous determination. It was. In order to solve this problem, in this circuit, the delay time difference caused by the delay elements 24 and 25 is adjusted to a length that is an odd multiple of one half of the pattern period of the preamble signal of the high-speed signal input to this circuit. ing.

  The condition under which this circuit operates effectively is that the preamble signal pattern of the high-speed signal is inverted in polarity at half of its period, and the inversion code of the first half pattern is the latter half pattern. In this case, when a delay difference that is an odd multiple of one half of the preamble period is given, the input signal of the mismatch detection circuit 26 becomes a complementary signal (differential signal), so that the output is the same sign sequence of “1”. Become. Since the same sign continuation of “0” is output to the input of the same sign continuation such as no signal, an erroneous determination does not occur unless the same pattern as the preamble continues in the payload portion as long as the preamble.

FIG. 13 is a time chart showing the operation of the fifth embodiment of the present invention. In the figure, components similar to those in FIG. In the figure, an alternating signal of “1010” is used as the simplest preample pattern. FIG. 13A shows an operation for a high-speed signal, and FIG. 13B shows an operation for a low-speed signal. As shown in FIG. 13A, since the preamble period is 2 bits here, a delay time difference D ₂ of 1 bit (one half of the preamble pattern period) is provided between the delay elements 24 and 25. Shows the operation when Node signals A and B are input to the mismatch detection circuit 26 with a delay time difference D _2, its output is outputted as the potential of the node C. It can be seen that the preamble part is the same code continuation of the code “1” (the part indicated by “0” in the figure). By designing the integration circuit 6 so that its time constant is τ ₀ , the integration circuit 6 can react to the same sign sequence having a length of the preamble and output a potential exceeding the threshold value of the comparison circuit 7. After that, when a random signal in the payload portion is input, the mismatch output outputs a mismatch between the signals with a mark ratio of 1/2, so the output signal also becomes a mark ratio with a probability of 1/2, and its integrated output is It drops to an average potential that is half of the continuous “1” sign. As a result, a pulse signal having a finite width having a rising edge in the middle of the preamble is output to the output terminal 10 of the comparison circuit 7.

  On the other hand, as shown in FIG. 13B, when a low speed signal is input, the delay difference between the nodes A and B is the preamble period of the low speed signal (here, the same pattern as the high speed signal and the speed is 3 minutes). Therefore, the output of the mismatch detection circuit 26 in the preamble part is not “1” in the same sign sequence (here, the signal has a mark ratio of 1/3). ing). For this reason, since the output of the integration circuit 6 does not exceed the threshold value of the comparison circuit 7, no pulse signal is output to the output terminal 10 of the comparison circuit 7.

  As described above, by using the configuration of the fifth embodiment, not only functions equivalent to those of the first embodiment can be realized, but also the same code sequence included in the payload and a long no-signal state between signals are included. Misjudgment does not occur.

<Sixth embodiment>
FIG. 14 shows the configuration of the speed determination circuit according to the sixth embodiment of the present invention. 3 and 12 are denoted by the same reference numerals, and 27 and 28 are delay elements. This embodiment, like the fifth embodiment (FIG. 12), solves the problem of erroneous determination caused by using the coincidence detection circuit 4 in the second embodiment (FIG. 3). 27 a delay time difference D ₃ caused by 28, is adjusted to the length of one of the odd multiple of half of the pattern period of the preamble signal of the low-speed signal input to the circuit. The conditions under which this circuit operates effectively are the same as in the fifth embodiment (FIG. 12), where the polarity of the low-speed preamble signal pattern is inverted at half the period, and the inversion code of the first half pattern is the latter half pattern. It is that.

  FIG. 15 is a time chart showing the operation of the sixth embodiment of the present invention. In the figure, components similar to those in FIG. In the figure, as in FIG. 13, the alternating signal “1010” is used as the simplest preamble pattern. FIG. 15A shows an operation for a low-speed signal, and FIG. 15B shows an operation for a high-speed signal. In FIG. 15A, a finite-width pulse signal having a rising edge in the middle of the preamble is output to the output terminal 10 of the comparison circuit 7 in the same manner as in FIGS. 4A and 13A. It is clear that

On the other hand, when a high-speed signal is input, if the preamble period of the low-speed signal is not an odd multiple of the preamble period of the high-speed signal, the output of the preamble portion mismatch detection circuit 26 is the same as described with reference to FIG. Since the same sign is not continuous, the output of the integrating circuit 13 does not exceed the threshold value of the comparing circuit 7. However, when the preamble period of the low-speed signal is an odd multiple of the preamble period of the high-speed signal, as described with reference to FIG. If the time constant τ ₁ of the integrating circuit 13 is almost equal to the preamble length of the low-speed signal, the preamble length of the high-speed signal generally decreases in inverse proportion to the transmission speed, so that τ ₀ <τ ₁ . Assuming that the integrated value of the output of the mismatch detection circuit 26 decreases in the payload portion, a continuous code having a length of about τ ₀ does not sufficiently exceed the threshold value, and a continuous code of the same code having a length of about τ ₁ is used. If the threshold voltage (reference potential Vref) is finally set so as to exceed the threshold, it is possible to adjust so as not to output a finite-width pulse signal having a rising edge in the middle of the preamble with respect to the input of the high-speed signal.

  As described above, by using the configuration of the sixth embodiment, not only functions equivalent to those of the second embodiment can be realized, but also the same code sequence included in the payload and a long no-signal state between signals are included. Misjudgment does not occur.

<Seventh embodiment>
FIG. 16 shows the configuration of the speed determination device according to the seventh embodiment of the present invention. In the figure, the same components as those in FIG. 5 are denoted by the same reference numerals, and reference numerals 29 and 30 denote speed judging circuits of the fifth embodiment (FIG. 12) or the sixth embodiment (FIG. 14) of the present invention. FIG. 17 is a time chart showing the operation of the seventh embodiment, and the reference numerals in the figure indicate the potentials of the nodes indicated by the same reference numerals shown in FIG. Assume that the speed determination circuits 29 and 30 are circuits for determining different speed signals (in FIG. 16, 29 is a low-speed signal determination circuit). When each speed determination circuit outputs a pulse signal to the preamble portion of each speed signal as a determination signal, signals as shown in FIG. 17 are obtained at the output terminal 10 and the inverted output terminal 17. With this output signal, it is possible to determine which speed signal is being input. It can be seen that this embodiment does not cause an erroneous determination for a long no-signal state as in the fourth embodiment.

<Eighth embodiment>
FIG. 18 shows the configuration of the speed determining apparatus according to the eighth embodiment of the present invention. The reference numerals in the figure are the same as those in FIGS. In this embodiment, the determination circuit 15 of the first embodiment (FIG. 1) and the determination circuit 29 of the sixth embodiment (FIG. 14) are used. As shown in FIG. 19, since no erroneous determination occurs at the S terminal to which the output of the speed determination circuit 29 is input, the same effect as that of the fourth embodiment (FIG. 8) can be obtained and operated in combination. It can be seen that no erroneous determination occurs even in the case.

<Ninth embodiment>
FIG. 20 shows the configuration of the speed determining apparatus according to the ninth embodiment of the present invention. In the figure, the same components as those in FIG. 18 are denoted by the same reference numerals, 31 is a negation circuit, 32 and 33 are delay elements, and 34 is an AND circuit. In this embodiment, the speed determination circuit 14 of the second embodiment (FIG. 3) and the speed determination circuit 30 of the fifth embodiment (FIG. 12) are used. The speed determination circuit 14 makes an erroneous determination when the long no-signal state, the same sign continuation, and the low-speed signal preamble period is an integral multiple of the high-speed signal preamble period. In this embodiment, the delay elements 32 and 33 cause a certain delay time difference (a time difference in which the flip-flop 16 can react), and the AND circuit 34 leaves the output pulse of the speed determination circuit 14 except for the rising edge portion. Misjudgment is avoided by compressing to the width of the time difference. As is apparent from the time chart of FIG. 21, it can be seen that no erroneous determination occurs.

<Tenth embodiment>
FIG. 22 shows the configuration of the speed determination device according to the tenth embodiment of the present invention. In the figure, the same components as those in FIG. 18 are denoted by the same reference numerals, and reference numerals 35, 36 and 37 denote the first embodiment (FIG. 1), the second embodiment (FIG. 3) or the fifth embodiment (FIG. 12) of the present invention. Or, the speed judgment circuit of the sixth embodiment (FIG. 14), 38 is an OR circuit, 39, 40, 41 are output terminals, and 42, 43, 44 are inverted output terminals. In this embodiment, a combination of three or more speed determination circuits is shown. FIG. 22 shows an embodiment in which the two speed determination circuits of the third embodiment (FIG. 5) are used, assuming that the speed determination circuits 35, 36, and 37 are premised on the specification under conditions that do not cause malfunction. Can be expanded to those using a plurality of determination circuits. If the logical sum of the speed determination circuit outputs other than the speed determination circuit input to the S terminal is input to the R terminal of each flip-flop 16, the transmission speed can be determined from the output signal of each flip-flop 16.

<Eleventh embodiment>
FIG. 23 shows the configuration of the speed determination device according to the eleventh embodiment of the present invention. In the figure, the same components as those in FIG. 22 are denoted by the same reference numerals, 45, 46 and 47 are the speed judgment circuits 48, 49, 47 of the first embodiment (FIG. 1) or the second embodiment (FIG. 3) of the present invention. Reference numeral 50 denotes a delay element. When using a plurality of speed determination circuits of the first embodiment and the second embodiment using coincidence determination, the circuit shown in the fourth embodiment (FIG. 8) is expanded to have a configuration like this embodiment. Take it. The falling edges of the pulses output from the plurality of speed determination circuits 45, 46, 47 are aligned using the delay elements 48, 49, 50, and the plurality of speed determination circuits 45, 46, 47 output "1" simultaneously. In this case, forbidden input can be avoided by setting the output of the speed judgment circuit of the fastest signal among them to "1" and forcing the rest to "0". In FIG. 23, reference numeral 47 is a speed determination circuit for determining the fastest signal, and reference numeral 45 is a speed determination circuit for determining the slowest signal. The low-speed speed determination circuit 45 takes a negative logical sum of the outputs of the medium-speed speed determination circuit 46 and the high-speed speed determination circuit 47 and further obtains a logical product of the determination output of the speed determination circuit 45 as a determination output. The medium speed determination circuit 46 negates the output of the high speed determination circuit 47 and uses a logical product with the determination output of the speed determination circuit 46 as a determination output. That is, the specific speed determination circuit performs a negative logical sum of the outputs of all the speed determination circuits that determine a signal faster than the determination speed, and performs a logical product with the determination output of the specific speed determination circuit. A signal may be used as a determination output.

<Twelfth embodiment>
FIG. 24 shows the configuration of the speed determination device according to the twelfth embodiment of the present invention. In the figure, the same components as those in FIGS. 20 and 23 are denoted by the same reference numerals, 51 and 53 are speed determination circuits of the fifth embodiment (FIG. 12) or the sixth embodiment (FIG. 14) of the present invention, and 52 is the main circuit. The speed judgment circuit of 1st Example (FIG. 1) or 2nd Example (FIG. 3) of invention is shown. When only one speed determination circuit of the first embodiment or the second embodiment using coincidence determination is used, and all other speed determination circuits are configured by the speed determination circuit of the fifth embodiment or the sixth embodiment. If the configuration of this embodiment is used, the same effect as that of the ninth embodiment (FIG. 20) can be obtained.

<Other embodiments>
In each of the embodiments described above, for the sake of convenience, the same preamble pattern is used for the high-speed signal and the low-speed signal, but it is not necessarily the same. The delay element may be a delay circuit or a transmission line as long as it gives a delay, and does not depend on the circuit configuration or material. Examples of using a reset set flip-flop circuit as a memory circuit and an example using a logic circuit that avoids forbidden input have been shown. However, if the logic circuit operates in the same way, a circuit with a different configuration may be used. Similar effects can be obtained. In the drawing showing the circuit configuration, for convenience, the interface of the element circuit is shown as a single-ended configuration, but it may be a differential interface. In particular, a part using a negation circuit after branching can be omitted by using a differential output interface.

  As described above, the repetition of the same pattern of a known preamble signal is discriminated. More specifically, the repetition of the same pattern is converted into a continuous signal of the same sign, and the continuous length of the same code included in the signal is determined. Although it is long, the integration time is reduced by generating the same sign continuous signal (having a length of about several tens of bits to several thousand bits) which is about 1 to 3 digits shorter than the time constant required for the conventional circuit. Since it can be shortened to the same length as the generated same code continuous signal length, the speed can be determined at high speed within the preamble signal reception time. Further, by holding a pulse signal having a finite width as a determination result in the memory circuit, the determination result can be held until the determination result is changed.

It is a figure which shows the structure of the speed determination circuit of 1st Example of this invention. It is a time chart which shows operation | movement of 1st Example of this invention. It is a figure which shows the structure of the speed determination circuit of 2nd Example of this invention. It is a time chart which shows operation | movement of 2nd Example of this invention. It is a figure which shows the structure of the speed determination apparatus of 3rd Example of this invention. It is a time chart which shows operation | movement of 3rd Example of this invention. It is a time chart which shows the malfunctioning of 3rd Example of this invention. It is a figure which shows the structure of the speed determination apparatus of 4th Example of this invention. It is a time chart which shows operation | movement of 4th Example of this invention. It is a time chart which shows the malfunctioning of 4th Example of this invention. It is a time chart which shows the operation | movement of the application example of 4th Example of this invention. It is a figure which shows the structure of the speed determination circuit of 5th Example of this invention. It is a time chart which shows operation | movement of 5th Example of this invention. It is a figure which shows the structure of the speed determination circuit of 6th Example of this invention. It is a time chart which shows operation | movement of 6th Example of this invention. It is a figure which shows the structure of the speed determination apparatus of 7th Example of this invention. It is a time chart which shows operation | movement of 7th Example of this invention. It is a figure which shows the structure of the speed determination apparatus of 8th Example of this invention. It is a time chart which shows the operation | movement of the 8th real deer example of this invention. It is a figure which shows the structure of the speed determination apparatus of 9th Example of this invention. It is a time chart which shows the operation | movement of 9th Example of this invention. It is a figure which shows the structure of the speed determination apparatus of 10th Example of this invention. It is a figure which shows the structure of the speed determination apparatus of 11th Example of this invention. It is a figure which shows the structure of the speed determination apparatus of 12th Example of this invention.

Explanation of symbols

1: input terminal, 2: 3: delay element, 4: coincidence detection circuit (exclusive NOR circuit), 5: termination circuit, 6: integration circuit (time constant is τ ₀ ), 7: comparison circuit, 8: Power supply or ground, 9: reference potential input terminal, 10: output terminal, 11, 12: delay element, 13: integrating circuit (time constant is τ ₁ ), 14, 15: first or second embodiment of the present invention Example speed determination circuit, 16: reset set flip-flop circuit (RS / FF), 17: inverted output terminal, 18: malfunctioning part, 19, 20: delay element, 21: negation circuit, 22: AND circuit, 23 : Time difference between falling edges of pulses output by the determination circuit when a low-speed signal is input after a no-signal state longer than the preamble length of the low-speed signal, 24, 25: delay element, 26: mismatch detection circuit (exclusive OR circuit), 27, 2 : Delay element, 29, 30: speed judgment circuit of the fifth or sixth embodiment of the present invention, 31: negation circuit, 32, 33: delay element, 34: AND circuit, 35, 36, 37: book Speed judging circuit of the first embodiment, the second embodiment, the fifth embodiment or the sixth embodiment of the invention, 38: logical sum circuit, 39, 40, 41: output terminal, 42, 43, 44: inverted output terminal 45, 46, 47: Speed determination circuit according to the first or second embodiment of the present invention, 48, 49, 50: Delay element, 51, 53: According to the fifth or sixth embodiment of the present invention. Speed determination circuit 52: Speed determination circuit according to the first or second embodiment of the present invention.

Claims (9)

  A speed determining method, wherein the speed of the input signal is determined by determining repetition of the same pattern in a unique preamble signal included in the input signal. The speed determination method according to claim 1,
A speed determination method comprising: converting a repetition of the same pattern into a continuous signal of the same sign, integrating the continuous signal of the same sign, and determining a threshold value to determine a signal speed within a preamble signal reception time.   The delay means for generating two signals having a delay difference corresponding to an integral multiple of the pattern period of the inherent preamble signal included in the input signal from the input signal is compared with the logic of the two signals output from the delay means. A speed detecting means comprising: a coincidence detecting means; an integrating means for integrating an output signal of the coincidence detecting means; and a comparing means for comparing a signal obtained by the integrating means with a threshold value and outputting a determination result. Judgment circuit.   Delay means for generating two signals having a delay difference corresponding to an odd multiple of one-half of the pattern period of the inherent preamble signal included in the input signal from the input signal, and the two outputs from the delay means A non-coincidence detection unit that compares the logic of the signal, an integration unit that integrates the output signal of the non-coincidence detection unit, and a comparison unit that compares the signal obtained by the integration unit with a threshold value and outputs a determination result. A speed judgment circuit characterized by the above. In the speed determination circuit according to claim 3 or 4,
An integration time constant corresponding to a preamble signal reception time of a transmission speed signal to be determined is set in the integration means.   A plurality of speed determination circuits according to claim 3, 4 or 5 are connected to a common input terminal, and the delay difference of each speed determination circuit and the integration time constant of the integration means are set to different values. A speed determination apparatus characterized in that a plurality of speeds can be determined.   7. A speed circuit comprising: a storage circuit that stores the determination result of the speed determination circuit according to claim 3, wherein the storage circuit holds a previous determination result until the determination result is changed. Judgment device. In the speed determination device according to claim 7, which refers to claim 6,
Among two or more speed determination circuits to be used, when two or more speed determination circuits determine at the same time as the transmission speed that they are responsible for, they determine the fastest signal among the two or more speed determination circuits. A speed judgment device that prioritizes judgment of a speed judgment circuit. The speed determination device according to claim 7,
One speed determination circuit according to claim 3 is a speed determination circuit for a low speed signal, and one speed determination circuit according to claim 4 is connected to a common input terminal as a speed determination circuit for a high speed signal. 4. A speed determining apparatus comprising pulse compression means for compressing a pulse width of a determination output signal of the speed determination circuit according to claim 3 at a rising edge portion.

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