JPS59161119A - Phase comparator - Google Patents

Abstract

PURPOSE:To obtain exactly an analog signal corresponding to a phase difference of two input signals by combining an integration circuit and a sample holding circuit. CONSTITUTION:An integration circuit 32 starts charging by an input signal of one of a terminal 35 or 36, for instance, at the time point of rise of the terminal 36, and stops charging at the time point of rise of a signal of the terminal 35. On the other hand, a controlling circuit 34 generates a discharge control signal synchronizing with a signal of the terminal 36, and a sampling time point control signal, and sends them out to the integration circuit 32 and a sample holding circuit 33, respectively. As a result, the integration circuit 32 repeats charging and discharging at every one period of the signal of the terminal 36, and by synchronizing with it, the sample holding circuit 33 sample-holds a result of integration. In this way, an analog signal corresponding to a phase difference of two input signals is obtained exactly from a terminal 38.

Description

Detailed Description of the Invention (Technical Field) The present invention enables a phase-locked oscillator (PLO) using a digital phase comparator to expand the degree of freedom in design and the range of application regarding the operating characteristics of PT and 0. This relates to the configuration of a phase comparator.

(Background Art) Exclusive OR (E
There are those that use a low-pass filter in the X-OR.

FIG. 1 shows an example of a case where a low-pass filter is used in the circuit.
-OR, circuit, 2 is a low-pass filter, terminals 3 and 4 are input signal terminals whose phases are to be compared;
The signals shown in 1) and (11) are applied. terminal 5
is a pulse train with a pulse width corresponding to the phase difference of the input signals at terminals 3 and 4, that is, (+li of bl) in the same figure.
The signal shown in is obtained. Here, V, , V, , indicate the level corresponding to 0.1 of the output pulse train. terminal 6
is the output of low-pass filter 2 (fit) in the same figure (b)
An analog output corresponding to the low frequency component VL,j shown by the dotted line, that is, the phase difference between the two input signals, is obtained.

This phase comparison characteristic has a phase difference of 2 as shown in the same figure (C).
The characteristic is that the triangular waveform repeats every integer multiple of π.

FIG. 2 shows an example in which n, -s flip-flops are used. Figure (a) shows its configuration; 7 is an It, -S frithop flop, 2 is a low-pass filter, and 8 and 9 are (I
)) Input terminals for input signals shown in (1) and (11),
10 is the output terminal of R, -8 flip-flop 7.
This is the pulse train shown in (iii) of b>. 11 is the output terminal of the low-pass filter 2 (ittl
The output shown by the dotted line VL is obtained. The phase comparison characteristic is such that a toothed waveform repeats every integer multiple of the phase difference of 2π, as shown in FIG.

These phase comparators have the following drawbacks.

In other words, the sensitivity of the phase comparator is (2 Vl)/π for the 18X-011° circuit type, (V2-Vl)/2rr for the IL-S flip flow type circuit type, but V2
-V exceeds the power supply voltage limit of the phase comparator. cost, power consumption, etc.), PT
・The degree of freedom in the design of 0 will be restricted.

Furthermore, when a PLO is configured using these phase comparators, there are the following drawbacks. FIG. 3 shows an example of the configuration of TIT,0. In this figure, 12 is a reference oscillator (oscillation frequency fREF), 13 is a frequency divider (frequency division ratio 1/NR
), 1/l is the phase comparator shown in FIGS. 1 and 2, 15 is a loop filter, and 16 is a voltage control excavator (VCO).

oscillation frequency fv), 17 is a frequency divider (frequency division ratio 1/Ny
), terminals 18 and 19 are input terminals of phase comparator]4,
20 is an output terminal of 14, 21 is an output terminal of loop filter 15, and 22 is an output terminal of VCOI 6. When configuring such a PLO, the cutoff frequency (3 dB lowering bandwidth fL) of the low-pass filter 2 shown in FIG. 1 or 2 is set to (iii) in FIG.
) of (++++) fundamental repetition frequency (fEX
or 1 ns), the cutoff frequency (1) of the input/output phase transfer function (G(?)) of the LO loop is
The phase comparator shown in FIGS. 1 and 2 can only be applied when the IB reduction bandwidth fp is sufficiently higher than 3 (IB reduction bandwidth fp). In other words, when fL cannot be made sufficiently lower than fEX or fvts, the fEx or fR8 component and its harmonics ``rt'' In other words, the unnecessary wave components are not sufficiently attenuated by the low-pass filter 2 and are passed to the next loop filter 15. When fL is set to a sufficiently low level (if this is not possible, the loop filter is also unable to sufficiently attenuate the unnecessary wave components,
added to. Therefore, in the output of V C (,), spurious components are generated on both sides of the oscillation frequency fv at frequencies separated by fv, x or fL8 and an integral multiple thereof.

In addition, if fL cannot be set to a sufficiently higher frequency than fP, the band limitation of the low-pass filter 2 will adversely affect the PLO's operating characteristics, such as deterioration of the transfer function G(f), instability of frequency pull-in operation, and increase in pull-in time. Such phenomena occur, making it impossible to realize the PLO operation as designed.

Next, FIG. 4 shows an example in which a charge pump is used as a phase frequency comparator. Figure (a) shows its configuration, where z3 is a phase frequency comparator, another is a charge pump circuit, and 16 is a P
This is a low-pass filter such as a loop filter used when configuring an LO. Terminals 26 and 27 are input terminals of the phase frequency comparator, respectively (i) and (
A signal as shown in ii) is applied.

The output terminal path 29 of the phase frequency comparator z3 has one of the input terminals 26 and 27 depending on which signal is leading in phase, for example (1) (ti) in FIG.
If the 26 side is leading, a pulse train shown in (m) in FIG. A direct current maintained at a low level (V, ) is outputted to the other output terminal 29 as shown in (IV) in (1) of the same figure. On the other hand, if the input terminal 27 side is ahead of the 5 side, the output signals of A and 29 will be switched. Furthermore, if the input terminals 26 and 27 are in the same phase, both A and 29 are kept at a low level (V, ). For example, if there is a high level (■2) period in the % signal, the charge pump circuit charges the capacitor included in the low-pass filter 16 during that period, and vice versa. If there is a high level period in the signal, the capacitor is discharged during that period, and if both the signal and 29 are low level, neither charging nor discharging occurs, and the charge on the capacitor is kept constant. A capacitor voltage corresponding to the amount of charge is output to the output terminal 31 of the low-pass filter 16.

The phase comparison characteristic of this circuit is as shown in FIG. 4(C).

In the case of this phase comparator, the FIX-OR, circuit, and R-
As in the case of the .87 lip flop circuit, there is a drawback that the upper limit of its sensitivity is limited by the power supply voltage.

Furthermore, when configuring PT and O using this phase comparator, there are the following drawbacks. In other words, when the frequency of one of the input signals of the phase comparator is switched, a phase difference occurs between the input signal and the other input signal. Since the VCO control voltage is gradually changed while charging or discharging the capacitor, the control voltage is
It takes about one hour for the oscillation frequency to match the oscillation frequency.

Furthermore, even when using an analog phase comparator (such as a double-balanced mixer), the output of the phase comparator includes the sum of the two input signals, that is, the dual frequency component of the input frequency. It requires a filter for filtering, and has almost the same drawback as an Ex-on type phase comparator.

(Problem to be solved by the invention) The present invention provides two phase comparators to eliminate these drawbacks.
An integrator that repeats charging and discharging every period of one of the two input signals or every integer multiple of the period, and a sampling and holding circuit that repeatedly samples and holds the integration result in synchronization with the integrator. The drawings will be described in detail below.

(Structure and operation of the invention) FIG. 5 shows an embodiment of the invention. Figure (a)
is its configuration, 32 is an integrator, 33 is a sampling hold circuit, 34 is a control signal generation circuit, terminals 35 and 36 are input signals of the phase comparator, 37 is an output terminal of the integrator 32,
38 is an output terminal of the sampling hold circuit; 39 is an output signal terminal for controlling the start point and period of discharge of the integrator 32; /IO is an output terminal for a signal for controlling the sampling point of the sampling hold circuit 33; It is. An example of the input signals at the terminals 35 and 36 is shown in (1) and (11) in FIG. (1 of Figure 5 (bl)
Charging is started at t81) in 1), and at the rising edge of the signal at terminal 35 (t81) in FIG.
el) to stop charging. In the control circuit 34, based on the signal at the terminal 36, a signal as shown in FIG.
A discharge control signal shown in (m) of )) and a sampling time control signal shown in Ov) are generated and sent from the output terminal 39 to the integrating circuit 32 and from the output terminal 40 to the sampling and holding circuit 33, respectively. Here, the discharge control signal (+:+
), jdsl is the discharge start point, tdel is the discharge end point, and these are the te of the input signal (1) and the input signal (1).
1) is set at an appropriate time between the charging start time js20 of the next cycle, and the integration result in the integrating circuit 32 indicates that discharging starts from the time jdslO and ends by the time jdel. do. Similar charging and discharging are repeated in subsequent cycles, and a signal as shown in (v) is obtained at the output terminal 37 of the integrating circuit 32. Here V
l is the output voltage after discharging until charging starts, which is V6
1 is the output voltage after being charged until discharging is started. In the sampling circuit 33, tQa+ of the sampling pulse train shown in (iV) (this is tel of the pulse train of the input signal (1) and the discharge control pulse (iiD)
The output signal (v) of the phase comparator is sampled at an appropriate time between tdel and held until the next sampling time l5a2. As a result, an analog output corresponding to the phase difference between the input signal (11) and the input signal (1) during one cycle up to 1sl-js2 is obtained at the output terminal 38 of the sampling and holding circuit 33. The same process is repeated in subsequent cycles. (vl) in FIG. 5(b) shows the output signal of the sampling and hold circuit. It is possible to immediately obtain an analog output corresponding to each cycle. In addition, if there is no deterioration in the hold characteristics in the sampling and hold circuit, the input frequency component of the phase comparator and its integral multiple components as described in the above-mentioned phase comparator using the EX-OR circuit, etc. It never appears in the output. In the sampling and hold circuit used in the present invention, it is sufficient to bold the sampling result for a period corresponding to one cycle of the input signal of the phase comparator, so the circuit is easy to implement.

Further, the phase comparison characteristic of the phase comparator according to the present invention is h5 in FIG. 5(C). Here, ■2 indicates the maximum voltage of the phase comparator output. Also, the phase θ corresponding to v2 is expressed by the following formula: 0−−2π(lsl Lsal)/(ts21s+)
The input signal (1) of the phase comparator is the sampling pulse OV
) corresponds to the phase difference with the input signal (11) when delayed to the point in time. From this, phase comparator sensitivity 1 (P is Kp =
(V2 Vl)/θ. Therefore, we move the sampling time forward and (lsl
If the phase comparator is designed so that Lsal ) becomes smaller, the sensitivity of the phase comparator can be increased as desired.

In the above description, it is clear that exactly the same effect can be obtained even if the charging operation and discharging operation are switched. In addition, the operations such as charging and discharging are not the same as those shown in Figure 5 (bl), but other operations can be used as long as the integration results corresponding to the phases of the two input signals of the phase comparator can be obtained. It is clear that the same effect can be obtained even with the principle.Also, if the input phase amount and the value of the integration result do not change linearly, the line between 0 and 0 in Figure 5 (C) is a perfect straight line. However, there is no significant difference in the advantages obtained by using this phase comparator.

FIG. 6 shows another embodiment of the invention.

In the embodiment of FIG. 5, a frequency divider (dividing ratio 1/
M). In this case, the integrator 32, the sampling hold circuit 33, and the control circuit 34 are connected to the terminal 43.
, /I/l The charging/discharging and sampling/holding should be repeated every M times the frequency of the input signal (can be operated. By doing this, the change range of the phase comparator output level can be changed to the case shown in Fig. 5. It is possible to reduce only the sensitivity of the phase comparison to 1/M while keeping the same value.This circuit configuration can be used without reducing the frequency locking range of the PLO (when you want to reduce its loop gain, or This is effective when it is necessary to realize a phase comparator at a lower frequency.When actually configuring a synthesizer using a primary loop PLO, the phase comparator is configured as shown in Figure 6, and the frequency divider The frequency division ratio (1,/M) of 41.42 is j
1 (τ, = 1. M is determined so that / -.

In addition, if this phase shifter is used, its sensitivity can be increased by 1 simply by changing its design parameters, so from this point of view as well, the degree of freedom in designing the PLO can be increased without using a DC amplifier. be able to.

(Effects of the Invention) As explained above, if the phase comparator of the present invention is used, it is not necessary to use a band-limiting element such as a low-pass filter. It is possible to immediately and accurately obtain an analog output corresponding to Ex-o circuit type, R-
When an 8-flip-flop circuit type or analog type phase comparator is used, the leakage of spurious components into the CO output due to the low-pass filter used therein, deterioration of the transfer function Gσ), and frequency pull-in operation It is possible to realize T,0 without causing any adverse effects such as instability or an increase in the pull-in time (T, the operating characteristics as calculated by the theory).

For example, when realizing a -order loop PT, O (the configuration is such that the loop filter 15 is removed in Fig. 3), a band limit is applied to the phase difference signal of the two input waves of the phase comparator. Since the VCO is controlled by a signal that directly corresponds to the phase difference, it is possible to realize the PLO of the primary loop as in theory.

Utilizing this, if a frequency synthesizer with -order loop PLO is constructed, the frequency switching speed is fast (and the transfer function G (force cutoff frequency jp is low (therefore, S/
N (good output signal-to-noise power ratio) can be obtained. That is, in the -order loop PLO, there is an advantage that when the frequency of either one of the signals input to the phase comparator is switched, the PLO loop pull-in phenomenon is only phase pull-in. In other words, even if the frequency is switched, the phase comparison immediately after the frequency can be compared without causing the synchronization phenomenon seen in a secondary loop PLO using a loop filter or a PLO configured using a charge pump. The phase difference between the two input waves of the comparator is determined by the center value of the oscillation frequency of the VCO and the other input side of the phase comparator (VCO
The phase difference should gradually converge to a predetermined steady-state phase error determined by the relationship with the frequency of the other side. τ is equal to 1/K when K is the loop gain of PLO, and it is also equal to 1/2πfP when fP is the cutoff frequency (3 dB reduction width) of the transfer function Gσ). This value is equal to the quadratic loop P with the same jp
It takes much less time than LO or PLO using a charge pump. Furthermore, since this PLO is a primary loop, the frequency pull-in range when the frequency is switched corresponds to the oscillation frequency range of the VCO corresponding to the minimum and maximum voltages in the phase comparator output, that is, the frequency range in which synchronization can be maintained.

[Brief explanation of drawings]

Figures 1 (a) to (C) are explanatory diagrams of conventional EX-0, R, type phase comparators, and Figures 2 (a) to (c) are R-8 flip-flop type conventional phase comparators. Explanatory diagram, Figure 3 is P
LO configuration diagram, Figure 4 (al to (C) is an explanatory diagram of a conventional phase comparator using a phase frequency comparator and a charge pump, and Figures 5 (a) to (C) are one implementation of the present invention An illustration of an example,
FIG. 6 shows another embodiment of the invention. DESCRIPTION OF SYMBOLS 1...Ti:X-011, circuit, 2...Low pass filter, 3.4...Input terminal of phase comparator, 5...Output terminal of phase comparator, 6...Low pass filter Output terminal, 7...R, -
8 flip-flop circuit, 8.9... input terminal of phase comparator, 10... output terminal of phase comparator, 11... output terminal of low-pass filter, 12... reference oscillator, 13... Frequency divider, 14... Phase comparator, ]5... Loop filter, 16... Voltage controlled oscillator (VCO), 17... Frequency divider, 18,
19... Input terminal of phase comparator, 20... Output terminal of phase comparator, 21... Output terminal of loop filter, 22... Output terminal of voltage controlled oscillator (VCO), 23... Phase frequency comparator, 24... Charge pump circuit, 26, 2
7... Input terminal of phase frequency comparator, path, 29...
Output terminal of phase frequency comparator, addition...output terminal of charge pump circuit, 31...output terminal of loop filter, 32...integrator circuit, 33...sampling hold circuit, 34...control circuit 35 , 36... Input terminal of the integrating circuit, 37... Output terminal of the integrating circuit, ; 38... Output terminal of the sampling hold circuit, 3
9...Discharge control signal output terminal of control circuit, 40...
sampling point control signal output terminal of the control circuit, 41;
/12... Frequency divider, 43, 44... Input terminal for frequency division. Patent applicant Nippon Telegraph and Telephone Public Corporation Patent application agent Megumi Yamamoto - Figure 2

Claims (1)

[Claims] In a phase comparator that provides an analog output corresponding to the phase difference between two input signals, one of the input signals
A phase comparator comprising: an integrating circuit that repeats charging and discharging at every integer multiple of the cycle; a sample-hold circuit that repeats sample-holding of integration results in synchronization with the integrating circuit; and an output terminal connected to the output of the integrating circuit. .