JPH04222118A - Phase locked oscillator - Google Patents

Abstract

PURPOSE:To improve a transient response characteristic by duplexing a loop gain so as to compare phases by the rise and fall of a reference signal. CONSTITUTION:A 2/N frequency divider 3 frequency-divides the output of a VCO 1 into 2/N so that the output of the VCO 1 can be coincident with the reference signal. The phases of the reference signal and the output from the frequency divider 3 are compared at a first phase comparator 31 by the rise of the reference signal and the phases of the reference signal and the output from the 2/N frequency divider are compared by a second phase comparator 32 by the fall of the reference signal. Afterwards, the outputs of the both phase comparators 31 and 32 are added at an OR gate 33, and this added output is supplied through a low-pass filter 4 to the VCO 1. Thus, a frequency dividing ratio can be made to 2/N, the loop gain can be made double and as the result, the transient response characteristic can be improved.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a voltage controlled oscillator (VC
O), relates to a phase-locked oscillator consisting of a frequency divider, a phase comparator, and a low-pass filter.

Among highly stable oscillators, phase-locked oscillators are
Due to its stability and various dedicated ICs, highly stable oscillators are easily provided and used in various fields, but as a result, the quality and characteristics requirements for phase-locked oscillators tend to become stricter.

By the way, if there is a frequency difference between the reference signal and the VCO, a frequency divider is required, but in this case,
The loop gain is reduced by an amount corresponding to the frequency division ratio, and the characteristics of the phase-locked oscillator are deteriorated. Therefore, it is necessary to prevent such deterioration of characteristics.

0004

2. Description of the Related Art FIG. 5 is a block diagram of a conventional phase-locked oscillator. In FIG.
), 102 uses the output of the VCO 101 as a reference signal [Fig. 7(a)
1/N frequency divider 103 that divides the output of the VCO 101 by 1/N (N is a natural number) in order to match the frequency of the VCO 101 (see )).
is a phase comparator that compares the phase between the output of the 1/N frequency divider 102 [see FIG. 7(b)] and the reference signal. here,
As shown in FIG. 6, the phase comparator 103 is composed of a D flip-flop, and a reference signal is input to the clock end of the D flip-flop, and a 1/1 signal is input to the clear end of the D flip-flop.
The output of the N frequency divider 102 is input. Note that a high level signal (H) is input to the preset end of the D flip-flop.

104 is the output of the phase comparator 103 [FIG.
(c)], removes high frequency components and supplies the output as the control voltage of the VCO 101
loop filter).

With this configuration, the output of the VCO 101 is frequency-divided by 1/N by the 1/N frequency divider 102, and then phase-compared with the reference signal by the phase comparator 103 at the rising edge of the reference signal. The phase comparison result is passed through the low-pass filter 104.
The voltage is input as a control voltage to the VCO 101 via. As a result, the output of the VCO 101 becomes the same frequency as the reference signal.

[0007]

[Problems to be Solved by the Invention] However, in such a conventional phase synchronized oscillator, phase comparison is performed at the rising edge of the reference signal, so one point in the circuit is
The /N frequency divider reduces the loop gain to 1/N, which causes deterioration in characteristics such as a narrow tracking range.

The present invention was devised in view of these problems, and improves the characteristics by making it possible to perform phase comparison at the rising and falling edges of the reference signal and doubling the loop gain. The purpose of this invention is to provide a phase-locked oscillator.

[0009]

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. In this FIG.
is a frequency divider that divides the output of the VCO 1 in order to match the frequency of the output of the VCO 1 with the frequency of the reference signal. Here, this frequency divider 2 is configured as a 2/N frequency divider.

Reference numeral 3 denotes a phase comparator that compares the phase of the output of the frequency divider 2 and the reference signal.
A first phase comparator 31 performs phase comparison at the rising edge of the reference signal, a second phase comparator 32 performs phase comparison at the falling edge of the reference signal, and the output of the first phase comparator 31 and the second an adder 33 that adds the output of the phase comparator 32;
It is made up of.

Reference numeral 4 denotes a low-pass filter that removes high frequency components from the output of the phase comparator 3 and supplies the output as a control voltage for the VCO 1.

0012

[Operation] In the above-described phase synchronized oscillator of the present invention, the first phase comparator 31 compares the phases of the reference signal and the 2/N frequency divider output at the rising edge of the reference signal, and at the same time, at the falling edge of the reference signal. The second phase comparator 32 compares the phases of the reference signal and the 2/N frequency divider output. That is, 1 of the reference signal
Two phase comparisons are made during the period. Thereafter, the adder 33 adds the outputs of both phase comparators 31 and 32, and the added output is passed through the low-pass filter 4 to the VCO1.
supplied to

[0013]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. The phase-locked oscillator shown in FIG. It is equipped with a bandpass filter (loop filter) 4.

Here, the VCO 1 can vary the output frequency by controlling the control voltage, and the 2/N frequency divider 2
VCO1 to match the output of VCO1 with the frequency of the reference signal.
The frequency of the output is divided by 2/N.

Further, the phase comparator 3 compares the phase between the output of the 2/N frequency divider 2 and the reference signal, and as shown in FIG. A first phase comparator 31 performs phase comparison at the rising edge of the reference signal, a second phase comparator 32 performs phase comparison at the falling edge of the reference signal, and a second phase comparison between the output of the first phase comparator 31 and the second phase comparator 32 The OR gate 33 serves as an adder that performs an addition operation (in this example, an OR operation) with the output of the device 32.

Here, D flip-flops are used as the first and second phase comparators 31, and a reference signal [FIG. 4 ( (a)] is input, and the output of the 2/N frequency divider 2 (see FIG. 4(c)) is input to the clear terminal. Further, a reference signal is inputted to the clock terminal of the D flip-flop constituting the second phase comparator 32 via an inverting circuit 34 [FIG.
(b)], and the output of the 2/N frequency divider 2 (see FIG. 4(c)) is input to the clear end. Note that a high level signal (H) is input to the preset end of each D flip-flop. The Q end of the D flip-flop is the output end, and the output PD1 of the first phase comparator 31 is as shown in FIG. 4(d), and the second
The output PD2 of the phase comparator 32 is as shown in FIG. 4(e). Further, the output of the OR gate 33 (output of the phase comparator 3) is as shown in FIG. 4(f).

Note that the low-pass filter 4 removes high frequency components from the output of the phase comparator 3 and outputs the output to the VCO.
This voltage is supplied as one control voltage.

With the above configuration, the reference signal and the 2/N frequency divider output are connected to the first phase comparator 3 at the rising edge of the reference signal.
1, and at the falling edge of the reference signal, the reference signal and the 2/N frequency divider output are connected to the second phase comparator 3.
2, that is, phase comparison is performed twice during one period of the reference signal. After that, the outputs of both phase comparators 31 and 32 are added together at the OR gate 33 (logical sum operation).
After that, this addition output is passed through a low-pass filter 4 to V
CO1 is supplied. As a result, the output of the VCO 101 becomes the same frequency as the reference signal.

In this way, since phase comparison is performed at the rising and falling edges of the reference signal, the frequency division ratio can be set to 2/N, thereby doubling the loop gain, and as a result, This is intended to improve transient response characteristics, such as reducing lock-up time and expanding capture range.

[0021]

[Effects of the Invention] As detailed above, according to the phase synchronized oscillator of the present invention, the phase comparison is performed at the rising edge and falling edge of the reference signal, so the frequency division ratio can be set to 2/N. , the loop gain can be doubled,
As a result, there are advantages of improving transient response characteristics such as reducing lock-up time and expanding capture range.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a block diagram of a phase comparator in one embodiment of the present invention.

FIG. 4 is a time chart of one embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a block diagram of a phase comparator in a conventional example.

FIG. 7 is a time chart of a conventional example.

[Explanation of symbols]

1 Voltage controlled oscillator (VCO) 2 2/N frequency divider 3 Phase comparator 4 Low pass filter 31 First phase comparator 32 Second phase comparator 33 Adder (OR gate) 34 Inversion circuit 101 Voltage controlled oscillator (VCO) 102 1/N frequency divider 103 Phase comparator 104 Low pass filter

Claims (1)

[Claims] Claims: 1. A voltage controlled oscillator (1) whose output frequency can be made variable by a control voltage; A frequency divider (2) that divides the frequency, a phase comparator (3) that performs a phase comparison between the output of the frequency divider (2) and the reference signal, and a high frequency component is removed and the output is sent to the voltage controlled oscillator (1).
In the phase-locked oscillator, the frequency divider (2) is provided with a low-pass filter (4) that supplies a control voltage of 2/
It is configured as an N frequency divider, and the phase comparator (3
) is the first phase that performs phase comparison at the rising edge of the reference signal.
a phase comparator (31), a second phase comparator (32) that performs phase comparison at the falling edge of the reference signal, and a phase comparison between the output of the first phase comparator (31) and the second phase comparator (32); Vessel (32
) and an adder (33) for adding the output of the phase synchronized oscillator.