JP2560982B2 - Clock extraction circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock extraction circuit in a digital communication device which performs data transmission using stuffy sync conversion and requires reduction of destaff jitter in the clock extraction of the receiving side destuff sync conversion section.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a general phase locked loop (PLL) used in a clock extraction circuit of a conventional de-stuff sync converter. In this conventional clock extraction circuit, the loop band of the phase locked loop (PLL) is
That is, the output jitter is suppressed by making the band (f1) of the low-pass filter as narrow as possible so that the output of the voltage controlled oscillator (VCO) does not follow the jitter component of the input clock. Therefore, in the conventional clock extraction circuit, there is a limit to narrowing this loop band due to the relationship of the synchronization characteristics such as the frequency synchronization range, and there is no choice but to allow a certain amount of output jitter.

[0003]

This conventional clock extraction circuit does not pose a problem when the input jitter tolerance of the subsequent transmission line is sufficient as compared with the output jitter. There is a problem in that it is necessary to specify the jitter tolerance, and the usage limit of each system comes out accordingly. Further, in the conventional clock extraction circuit that does not have such a regulation, when the input jitter tolerance is insufficient, the subsequent clock extraction system cannot follow this output jitter, and a data reading error occurs in the subsequent system. There was a problem that would occur.

An object of the present invention is to provide a clock extraction circuit capable of reducing jitter.

[0005]

According to the present invention, in a clock extraction circuit provided with a first phase-locked circuit and a second phase-locked circuit, the first phase-locked circuit includes a first voltage control circuit. An oscillator, a first phase comparator for performing a phase comparison between the input clock signal and the output of the first voltage controlled oscillator, and a first low pass filter for band limiting the output of the first phase comparator. The second phase-locked loop circuit is
2 voltage-controlled oscillator, and the output of the first voltage-controlled oscillator
The second phase comparison of the output of the second voltage controlled oscillator
Wider than the band of the phase comparator and the first low pass filter
A second phase comparator which has a band and limits the band of the output of the second phase comparator;
The output of the first low-pass filter and the second low-pass filter are branched
The amount of jitter reduction that adjusts the level and inverts the phase
Control circuit, the output of the jitter reduction amount control circuit and the second low range
The output of the filter is synthesized and the second voltage controlled oscillator
It is equipped with an adder circuit that outputs a phase synchronization control signal,
Of the first voltage controlled oscillator including the
The first low-pass filter that is the jitter information of the output of the oscillator
And the output of the second phase synchronization circuit for automatic phase synchronization
The output clock is reduced by reducing the jitter component of the control signal.
Clock extraction characterized by reducing the jitter of the clock signal.
The output circuit is obtained.

[0006]

[0007]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The input clock signal 1 is the first phase locked loop (PL
L) 3 is input to the first phase comparator 5 and is phase-compared with the output signal of the first voltage controlled oscillator (VCO) 6, and its output is band-limited by the first low-pass filter 7, Of the voltage controlled oscillator (VCO) 6 of FIG. When the input clock signal 1 has low-frequency jitter (destuff jitter), the output of the first low-pass filter 7 has a jitter component within that band. Information on the jitter component is sent to the jitter reduction amount control circuit 12 of the second phase locked loop (PLL) 4.

Next, the operation of the second phase locked loop 4 will be described. The second phase comparator 8, the second voltage controlled oscillator 9, and the second low pass filter 10 constitute a second phase locked loop circuit 4. The input signal to the second phase locked loop 4 is the output signal of the first phase locked loop 3, that is, the output signal of the first voltage controlled oscillator 6. The pass band (f2) of the second low-pass filter 10 is the first low-pass filter 7
Since it is sufficiently wider than the pass band (f1) of the second phase synchronization circuit 4 unless the output signal of the jitter reduction amount control circuit 12 is added in the adder circuit 11, the second phase synchronization circuit 4 receives the first input signal.
The output signal of the phase-locked loop 3 is completely followed. Also,
The output signal of the first voltage controlled oscillator 6 is input to the second phase comparator 8 as an input signal of the second phase locked loop 4.

In the present invention, the jitter reduction amount control circuit 12 phase-inverts (reverse-phases) the jitter component contained in the input signal of the second phase-locked loop 4 and adds it to the adder circuit 11. Interrupts the loop of the phase synchronization circuit 4 of. That is, by canceling the jitter component in the automatic phase synchronization control signal applied to the second voltage controlled oscillator 9,
The jitter component included in the output of the voltage controlled oscillator 9 can be reduced. At this time, the output level of the jitter reduction amount control circuit 12 which interrupts is the second phase synchronization circuit 4
It is set under the condition that the phase synchronization of is not lost.

Further, only the operating principle of the adder circuit 11 is shown. As a concrete means, the output of the jitter reduction amount control circuit 12 is set to the fixed bias side of the second voltage controlled oscillator 9, that is, the reference voltage side. Means for adding are also included.

[0012]

As described above, according to the present invention, the phase-locked loops (PLLs) are connected in two stages, and in the latter-staged phase-locked loops (PLLs), the jitter extracted in the previous stage is added to the automatic phase-locking control signal. Since the components are added in reverse phase, it is possible to reduce the jitter of the voltage controlled oscillator (VCO) output.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clock extraction circuit of the present invention.

FIG. 2 is a block diagram showing an embodiment of a conventional clock extraction circuit.

[Explanation of symbols]

 1 Input Clock Signal 2 Output Clock Signal 3 First Phase-Locked Circuit 4 Second Phase-Locked Circuit 5 First Phase Comparator 6 First Voltage-Controlled Oscillator 7 First Low-Pass Filter 8 Second Phase Comparator 9 Second Voltage Controlled Oscillator 10 Second Low Pass Filter 11 Adder Circuit 12 Jitter Reduction Amount Control Circuit

Claims (1)

(57) [Claims] 1. A clock extraction circuit comprising a first phase locked loop and a second phase locked loop, wherein the first phase locked loop is a first voltage controlled oscillator, an input clock signal and the first phase locked loop. A first phase comparator for comparing the phases of the outputs of the voltage controlled oscillators, and a first low-pass filter for band limiting the output of the first phase comparator.
Of the second voltage controlled oscillator, a second phase comparator for performing phase comparison between the output of the first voltage controlled oscillator and the output of the second voltage controlled oscillator, and the first low pass filter. A second low-pass filter having a band sufficiently wider than that of the second phase-comparator for limiting the band of the output of the second phase comparator, and a jitter reduction amount for branching the output of the first low-pass filter and performing its level adjustment and phase inversion. A control circuit and an adder circuit for synthesizing an output of the jitter reduction amount control circuit and an output of the second low-pass filter and outputting an automatic phase synchronization control signal of the second voltage controlled oscillator are included. a first voltage controlled oscillator <br/> output and automatic phase synchronization of the first low-pass forte second phase locked loop given the output of the filter is a jitter information of the output of the first voltage controlled oscillator by reducing the jitter component of the control signal, out The clock extraction circuit, characterized in that to reduce the jitter of the clock signal.