JP2514955B2 - Phase synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a phase locked loop circuit used in a communication system.

(Prior Art) Phase-locked circuits have been widely used in communication systems in recent years because they can obtain an output signal that is phase-locked at the same frequency as an input signal and have a noise suppression effect. For example, it is used in a timing signal reproducing circuit, a carrier wave reproducing circuit in a receiver for digital signal transmission, a clock supplying device in a digital integrated network by a slave synchronization system, and the like.

FIG. 13 is a block diagram showing the structure of such a conventional phase locked loop circuit. As shown in FIG. 13, this phase locked loop circuit comprises a phase comparator 1, a loop filter 2 and a voltage controlled oscillator 3. The signal x from the transmission line is input to the input terminal 4.
(T) is input and the output signal v (t) of this phase locked loop is output from the output terminal 5. The phase comparator 1 outputs the signal x
The phases of (t) and the signal v (t) are compared and a signal u (t) corresponding to the phase difference is output. The loop filter 2 receives the signal u
The jitter of (t) is suppressed. The voltage controlled oscillator 3 oscillates at a frequency according to the output voltage of the loop filter 2.

 Next, the operation of this circuit will be described.

The signal x (t) from the transmission line input to the input terminal 4,
The output signal v (t) of the voltage controlled oscillator 3 is Is defined.

However, ω ₀ is the central angular frequency of the input signal, δ (t) is the input phase, A is the effective amplitude value of the input signal, and θ (t) is the output phase of the voltage suppression oscillator 3.

When a multiplier is used as the phase comparator 1, the low frequency component u (t) of the multiplier output is obtained as u (t) = Asin (δ (t) −θ (t)) (3).

Here, when the phase difference δ (t) −θ (t) is small, linear approximation is established, and is approximated as u (t) = A (δ (t) −θ (t)) (4). From the above equation, a voltage proportional to the phase difference between x (t) and v (t) is output. u (t) is input to the voltage controlled oscillator 3 after the jitter is suppressed by the loop filter 2. The output frequency of the voltage controlled oscillator 3 changes in proportion to the input voltage. Output v (t) of voltage controlled oscillator 3
Is fed back to the phase comparator 1 and the signal x (t)
And signal v (t) are controlled so that synchronization is established.

In addition, this phase synchronization circuit is as described in Chapter 3 and Chapter 4 of "How to use PLL-IC" published by Koho, 1976.
It is represented by an equivalent block diagram as shown in FIG. In the figure, δ (s) and θ (s) represent an input phase and an output phase, respectively, and reference numeral 6 represents an attenuator. Reference numeral 7 F (s) is the transfer function of the loop filter 2 and reference numeral 8 is
K / s is represented by using the Laplace exchange for each transfer function of the voltage controlled oscillator 3. A represents the effective amplitude value of the input signal.

And the closed loop transfer function H (s) of the circuit shown in FIG.
Is Then, the element that determines the characteristic of the phase locked loop is derived from the above equation.

By the way, when a low-pass filter is used as the loop filter 2 described above, the transfer function F (s) is expressed as F (s) = 1 + a / s (6). In this case, the above-mentioned closed loop transfer function H (s) of the fifth equation is And has a secondary characteristic.

On the other hand, when using the phase-locked loop to track the modulated signal,
It is required to remove the noise component without attenuating the signal component. That is, the transfer characteristic of the phase locked loop is
It is required to be flat in the pass band and have sufficient attenuation capability in the suppression band.

Therefore, the above-described generally used phase-locked loop having the secondary characteristic cannot sufficiently meet such a demand.

For this reason, it is possible to meet such a demand by using a phase-locked circuit of the third order or higher order.
In that case, as described in Chapter 4 of the document "How to Use PLL-IC", there is a problem in that the input level is likely to be unstable. That is, it cannot be used in an environment with a low SN ratio where the input level tends to be low,
It wasn't practical. Further, such a high-order phase locked loop has a problem that the transient response characteristic is slow.

(Problems to be Solved by the Invention) Since the commonly used second-order phase-locked circuit does not have sufficient noise suppression capability, use a third-order or higher-order phase-locked circuit. Although the conventional high-order phase locked loop circuit has a high noise suppression ability, it has a problem in stability and a slow transient response characteristic.

Therefore, the communication system has high stability in an environment where the input signal-to-noise ratio (SN ratio) is low, and
A high-order phase locked loop circuit with high noise suppression capability is required,
On the other hand, in an environment where the input signal-to-noise ratio (SN ratio) is high, it is not necessary to have a large cough and noise suppression capability, and considering the transient response characteristics, a rather low-order phase locked loop circuit is required. Therefore, it is desirable that the order changes and the loop bandwidth changes in accordance with the SN ratio of the input.

The present invention has been made to solve such a problem, and an object thereof is to provide a stable phase-locked circuit whose order can be easily controlled.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention comprises at least three sets of phase-locked circuits each including at least a phase comparator, a loop filter and a voltage controlled oscillator. The received signal is used as an input to the first and second phase locked loops, and the first
The output of the phase comparator of the phase-locked loop is superposed on the input of the loop filter of the second phase-locked loop, and the output of the voltage-controlled oscillator of the second phase-locked loop is used as the input of the third phase-locked loop. The output of the phase comparator of the second phase locked loop is superimposed on the input of the loop filter of the third phase locked loop, and the output of the voltage controlled oscillator of the third phase locked loop is used as the output signal. Is characterized by.

(Operation) With the circuit configuration according to the present invention, it is possible to obtain a noise-suppressed output because it has stability and the transfer function from the input to the output can have a high order. Moreover, since the order can be controlled, the loop band can be easily controlled.

(Example) Hereinafter, the detail of the Example of this invention is described based on drawing.

FIG. 1 is a block diagram showing the configuration of a phase locked loop circuit according to an embodiment of the present invention.

The phase-locked loop circuit of this embodiment, as shown in FIG.
Of the first phase synchronization circuit 9
And the second phase-locked loop 10 are connected in parallel, and the third phase-locked loop 11 is connected in series at the subsequent stage.

The first phase synchronization circuit 9 includes a first phase comparator 12 and a first phase comparator 12.
The loop filter 13 and the first voltage controlled oscillator 14 of FIG. The input signal x (t) input to the input terminal 15 and the output signal v ₁ (t) of the first voltage controlled oscillator 14 are input to the first phase comparator 12. The output signal u ₁ (t) of the first phase comparator 12 is supplied to the first loop filter 13 and the second phase locked loop circuit 10 via the first attenuator 16 and the inverter 17.
Input to each side.

The second phase synchronization circuit 10 includes a second phase comparator 18, a first
Adder 19, second loop filter 20, and second voltage controlled oscillator 21. The input signal x (t) input to the input terminal 15 and the output signal v ₂ (t) of the second voltage controlled oscillator 21 are input to the second phase comparator 18. The output signal u ₂ (t) of the _second phase comparator 18 and the output signal u of the first phase comparator 12 via the first attenuator 16 and the inverter 17.
₁ (t) is added by the first adder 19 and input to the second loop filter 20. The output signal u ₂ (t) of the second phase comparator 18 is input to the third phase locked loop 11 side via the second attenuator 22.

The third phase locked loop circuit 11 includes a third phase comparator 23, a second phase
Adder 24, third loop filter 25, and third voltage controlled oscillator 26. The output signal v ₂ (t) of the second voltage controlled oscillator 21 in the second phase locked loop 10 and the output signal of the third voltage controlled oscillator 26 are supplied to the third phase comparator 23.
v ₃ (t) is input. Third output signal u ₃ (t) and the third output signal u ₃ of the phase comparator 23 (t) and a second output signal of the phase comparator 18 via the second attenuator 22 of the phase comparator 23
u ₂ (t) is added by the second adder 24 and input to the third loop filter 25. The output signal v ₃ (t) of the third voltage controlled oscillator 26 is output to the third phase comparator 23 as described above, and also output from the output terminal 27.
The output signal of 27 becomes the output signal of this phase locked loop.

Here, the input signal x (t) input to the input terminal 15,
Output signal v ₁ of the first voltage controlled oscillator 14 (t), the output signal v ₂ of the second voltage controlled oscillator 21 (t), the third output signal v ₃ of the voltage controlled oscillator 26 (t), respectively following Define like an expression.

Where A is the input signal amplitude effective value, ω ₀ is the input center angular frequency, δ (t) is the input phase, and θ ₁ (t) is the output phase of the output signal v ₁ (t) of the first voltage controlled oscillator 14. , Θ
₂ (t) is the output signal v ₂ of the second voltage controlled oscillator 21 (t)
, Θ ₃ (t) is the output phase of the output signal v ₃ (t) of the third voltage controlled oscillator 26.

 First, the operation of the first phase locked loop 9 will be described.

When a multiplier is used as the first phase comparator 12, the low frequency component u ₁ (t) of the output signal is u ₁ (t) = Asin (δ (t) −θ ₁ (t)) ... (12) Here, linear approximation is possible in a region where the phase difference δ (t) −θ ₁ (t) is small, and u ₁ (t) = A (δ (t) −θ ₁ (t)) (13) And a voltage corresponding to the phase difference is output.

u ₁ (t) is input to the first voltage controlled oscillator 14 after the jitter is suppressed by the first loop filter 13.

The output signal v ₁ (t) of the first voltage controlled oscillator 14 is fed back to the first phase comparator 12 and controlled so that the synchronization between the signal x (t) and the signal v ₁ (t) is established.

 Next, the operation of the second phase locked loop 10 will be described.

When a multiplier is used as the second phase comparator 18, the low frequency component u ₂ (t) of its output signal is u ₂ (t) = A (as in the case of the first phase locked loop 9). δ (t) −θ ₂ (t)) (14).

Then, the first attenuator 16 in which the attenuation ratio of the output signal u ₁ (t) of the first phase comparator 12 is G ₁ (0 ≦ G ₁ ≦ 1), and the inverter 17
The signal −G ₁ u ₁ (t) obtained by passing through and and the output signal u ₂ (t) of the second phase comparator 18 are input to the first adder 19. Then, the output signal w ₂ (t) of the first adder 19
Becomes w ₂ (t) = u ₂ (t) −G ₁ u ₁ (t) (15), and the jitter and the first jitter included in the output signal u ₂ (t) of the second phase comparator 18 Output signal u of phase comparator 12
_The jitter included in ₁ (t) is canceled. The w ₂ (t) is input to the second voltage controlled oscillator 21 after the jitter is suppressed by the second loop filter 20. The output signal v ₂ (t) of the second voltage controlled oscillator 21 is fed back to the second phase comparator 18 and is controlled so that the synchronization between the signal x (t) and the signal v ₂ (t) is established. It

 Next, the operation of the third phase locked loop 11 will be described.

When a multiplier is used as the third phase comparator 23, the low frequency component u ₃ (t) of its output signal is u ₃ (t) = A (as in the case of the first phase locked loop 9). θ ₂ (t) −θ ₃ (t)) (16)

The signal G ₂ u ₂ (t) obtained by passing through the second attenuator 22 having the attenuation ratio of the output signal u ₂ (t) of the second phase comparator 18 is G ₂ (0 ≦ G ₂ ≦ 1). ) And the output signal u _{3 of} the third phase comparator 23
(T) is input to the second adder 24. Then second
The output signal w ₃ (t) of the adder 24 becomes w ₃ (t) = u ₃ (t) + G ₂ u ₂ (t) (17).

The signal w ₃ (t) is input to the third voltage-controlled oscillator 26 after the jitter is suppressed by the third loop filter 25. The output signal v ₃ (t) of the third voltage controlled oscillator 26 is fed back to the third phase comparator 23, and the signal v ₂ (t)
Is controlled so as to establish synchronization with the signal v ₃ (t), and is used as the output signal of this entire system.
It is output from 27.

FIG. 2 is an equivalent block diagram focusing on the phase of the phase locked loop circuit of this embodiment. However, A is the input signal amplitude effective value and δ (s) is the input phase. In the figure,
θ ₁ (s) and K ₁ / s are the output phase and transfer function of the first voltage controlled oscillator 14, respectively. Also, θ ₂ (s) and K ₂ / s are
They are the output phase and the transfer function of the second voltage controlled oscillator 21, respectively. Further, θ ₃ (s) and K ₃ / s are the output phase and transfer function of the third voltage controlled oscillator 26, respectively. Also F
₁ (s), F ₂ (s), and F ₃ (s) are transfer functions of the first, second, and third loop filters 13, 20, and 25, respectively.

In the figure, the closed loop transfer function H (s) from the input terminal 15 to the output terminal 27 is Is asked.

Where the first, second and third loop filters 13, 2
When a general low-pass filter is used for 0 and 25, F ₁ (s) = 1 + a ₁ / s (19) F ₂ (s) = 1 + a ₂ / s (20) F ₃ (s) = 1 + a ₃ / s… (21)

At this time, H (s) is Is asked.

In the above formula (22), H (s) represents the transfer characteristics of the input signal and the output signal, and the first term on the right side of H (s) is 2
The second, second, and third terms show fourth-order and sixth-order characteristics, respectively. Since H (s) is a composite of stable secondary characteristics, it is stable regardless of its high order.

For simplification, if the damping ratios of the first and second attenuators are set to G ₁ = 1 and G ₂ = 1 (23), then H (s) in equation (22) is Is asked.

Here, A is the input signal amplitude effective value. That is, A =
When 1, Since H (s) does not include the constants of the first and second phase-locked loops 9 and 10, H (s) has a secondary wideband characteristic. On the other hand, as A decreases from 1, the influence of the second-order characteristic of the first term on the right side of H (s) decreases, and conversely, the influence of the sixth-order narrow-band characteristic of the second term on the right side increases. Therefore, the phase locked loop circuit of this embodiment can control the order of the transfer characteristic of the loop and the loop bandwidth by the magnitude A of the input amplitude.

Generally, when using a phase locked loop in a communication system, the input signal amplitude exceeds a certain value in order to suppress the saturation of the phase comparator and the loop gain from becoming too large. In many cases, an amplitude limiting circuit for preventing the above is installed before the phase synchronization circuit.

FIG. 3 is a block diagram showing an example of such an amplitude limiting circuit.

That is, the amplitude limiting circuit 28 shown in the figure comprises a soft limiter 29 having the characteristic shown in FIG. 4 and a bandpass filter 30 having the characteristic shown in FIG. 5, and the input signal from the transmission line is the soft limiter 29. Through the bandpass filter 30
It is designed to be input to the phase synchronization circuit.

FIG. 6 is a block diagram showing another example of the amplitude limiting circuit.

That is, the amplitude limiting circuit 31 shown in the figure comprises a hard limiter 32 having the characteristic shown in FIG. 7 and a bandpass filter 33 having the characteristic shown in FIG. 8. As in the above, the input signal from the transmission line is The signal is input to the phase locked loop circuit via the hard limiter 32 and the band pass filter 33.

It is also assumed that the amplitude limiting circuit 28 or the amplitude limiting circuit 31 whose maximum effective value of the output signal amplitude is 1 is installed in the preceding stage of the phase locked loop circuit of the above-described embodiment.

Then, when the signal amplitude A is equal to 1 or very close to 1, H (s) has a second-order broadband characteristic,
A fast transient response characteristic can be obtained. However, in the phase locked loop, when the signal amplitude A is large,
When the SN ratio is large, noise suppression capability is not required so much,
This is because the secondary characteristic is desirable.

As the signal amplitude A decreases from 1, that is, as the input signal-to-noise ratio (SN ratio) decreases, H
In (s), the 6th-order narrow band characteristic becomes dominant, and the noise suppression capability increases.

Therefore, the phase locked loop circuit of this embodiment can greatly change the bandwidth of the loop according to the input SN ratio, and can change the noise suppression capability.

Next, a phase locked loop circuit according to another embodiment of the present invention will be described, but before that, a phase locked loop circuit devised by the present inventor on which the phase locked loop circuit according to this embodiment is based will be described. .

FIG. 9 is a block diagram showing the configuration of this phase locked loop.

As shown in the figure, this phase locked loop circuit is composed of a first phase locked loop circuit 34, a second phase locked loop circuit 35, and a third phase locked loop circuit 36. The phase synchronization circuits 34, 35, 36 are connected in parallel.

The first phase synchronization circuit 34 includes a first phase comparator 37, a first phase comparator 37,
Loop filter 38 and a first voltage controlled oscillator 39. The input signal x (t) input to the input terminal 40 and the output signal v ₁ (t) of the first voltage controlled oscillator 39 are input to the first phase comparator 37. The output signal u ₁ (t) of the first phase comparator 37 is sent to the first loop filter 38, and to the second phase locked loop 35 side via the first attenuator 41 and the first inverter 42. Each is entered.

The second phase synchronization circuit 35 includes a second phase comparator 43, a first
Of the adder 44, the second loop filter 45, and the second voltage controlled oscillator 46. The input signal x (t) input to the input terminal 40 and the output signal v ₂ (t) of the second voltage controlled oscillator 46 are input to the second phase comparator 43. The output signal u ₁ of the first phase comparator 37 via the output signal u ₂ (t) and the first attenuator 41 and the first inverter 42 of the second phase comparator 43 (t) first Is added by the adder 44 of the above and is input to the second loop filter 45. The output signal u ₂ (t) of the second phase comparator 43 is output to the second attenuator 47 and the second inverter 48.
Is input to the third phase-locked loop 36 side via.

The third phase synchronization circuit 36 includes a third phase comparator 49, a second phase comparator 49
Adder 50, third loop filter 51, and third voltage-controlled oscillator 52. The input signal x (t) input to the input terminal 40 and the output signal v ₃ (t) of the third voltage controlled oscillator 52 are input to the third phase comparator 49. The output signal u ₃ of the third phase comparator 49 (t) and the output signal u ₂ of the second phase comparator 43 via the second attenuator 47 and the second inverter 48 (t), the The signals are added by the second adder 50 and input to the third loop filter 51. The output signal of the third voltage controlled oscillator 52 is output to the third phase comparator 49 as described above and also output from the output terminal 53, and the output signal of the output terminal 53 is the output signal of the phase locked loop circuit. Become.

Here, the input signal x (t) input to the input terminal 40,
Output signal v ₁ of the first voltage controlled oscillator 39 (t), the output signal v ₂ of the second voltage controlled oscillator 46 (t), the third output signal v ₃ of the voltage controlled oscillator 52 (t), respectively following Define like an expression.

Here, A is the effective value of the input signal amplitude, ω ₀ is the input central angular frequency, δ (t) is the input phase, θ ₁ (t) is the output phase of the output signal v ₁ of the first voltage controlled oscillator 39, and θ ₂ (T) is the output phase of the output signal v ₂ (t) of the second voltage controlled oscillator 46,
θ ₃ (t) is the output signal v of the third voltage controlled oscillator 52
₃ (t) phase.

 First, the operation of the first phase synchronization circuit 34 will be described.

When a multiplier is used as the first phase comparator 37, the low frequency component u ₁ (t) of the output signal is u ₁ (t) = Asin (δ (t) −θ ₁ (t)) ... (30) Here, linear approximation is possible in a region where the phase difference δ (t) −θ ₁ (t) is small, and u ₁ (t) = A (δ (t) −θ ₁ (t)) (31) And a voltage corresponding to the phase difference is output.

After the jitter is suppressed by the first loop filter 38, u ₁ (t) is input to the first voltage controlled oscillator 39.

The output signal v ₁ (t) of the first voltage controlled oscillator 39 is
Of the signal x (t) and the signal v ₁ (t) are controlled so that the synchronization is established.

Next, the operation of the second phase locked loop 35 will be described. Second
When a multiplier is used as the phase comparator 43 of, the low frequency component u ₂ (t) of the output signal is u ₂ (t) = A (δ ( t) −θ ₂ (t)) (32)

Then, the output signal u ₁ (t) of the first phase comparator 37 passes through the first attenuator 41 and the first inverter 42 whose attenuation ratio is G ₁ (0 ≦ G ₁ ≦ 1). The obtained signal −G ₁ u ₁ (t) and the output signal u ₂ (t) of the second phase comparator 43 are input to the first adder 44. Thus, the output signal w of the first adder 44
₂ (t) becomes w ₂ (t) = u ₂ (t) −G ₁ u ₁ (t) (33), and the jitter included in the output signal u ₂ (t) of the second phase comparator 43. And the output signal u of the first phase comparator 37
_The jitter included in ₁ (t) is canceled. The jitter of w ₂ (t) is suppressed by the second loop filter 45, and then input to the second voltage controlled oscillator 46.

The output signal v ₂ (t) of the second voltage controlled oscillator 46 is
Is fed back to the phase comparator 43 of the signal x (t),
The signal v ₂ (t) is controlled so that synchronization is established.

 Next, the operation of the third phase locked loop 36 will be described.

When a multiplier is used as the third phase comparator 49, the low frequency component u ₃ (t) of the output signal is the first phase locked loop circuit.
Similarly to the case of 34, u ₃ (t) = A (δ (t) −θ ₃ (t)) (34).

Then, the attenuation ratio of the signal u ₂ (t) of the second phase comparator 43 is
The output of _{G 2 (0 ≦ G 2 ≦} 1) of the second attenuator 47 and the second inverter 48 and the signal -G ₂ u ₂ obtained through the (t) and a third phase comparator 49 The signal u ₃ (t) is input to the second adder 50. Then, the output signal w ₃ (t) of the second adder 50 becomes w ₃ (t) = u ₃ (t) −G ₂ u ₂ (t) (35), and the third phase comparator The jitter included in the output signal u ₃ (t) of 49 and the jitter included in the output signal u ₂ (t) of the second phase comparator 43 are canceled, and the jitter characteristic is improved.
The w ₃ (t) is input to the third voltage controlled oscillator 52 after the jitter is suppressed by the third loop filter 51. Third
The output signal v ₃ (t) of the voltage-controlled oscillator 52 is fed back to the third phase comparator 49, and the signal x (t) and the signal v ₃ (t) are fed back.
It is controlled so that the synchronization of (t) is established, and is output from the output terminal 53 as an output signal of the entire system.

FIG. 10 is an equivalent block diagram focusing on the phase of the phase locked loop configured as described above. However, A is the input signal amplitude effective value, and δ (s) is the input phase. In the figure, θ ₁ (s) and K ₁ / s are the output phase and the transfer function of the first voltage controlled oscillator 39, respectively. Also, θ ₂ (s), K ₂
/ s is the output phase and transfer function of the second voltage controlled oscillator 46, respectively. Further, θ ₃ (s) and K ₃ / s are the output phase and transfer function of the third voltage controlled oscillator 52, respectively. Also F ₁
(S), F ₂ (s) and F ₃ (s) are transfer functions of the first, second and third loop filters 38, 45 and 51, respectively.

In the figure, the closed loop transfer function H (s) from the input terminal 40 to the output terminal 53 is Is asked.

Where the first, second and third loop filters 38, 4
If a general low-pass filter is used as 5, 51, F ₁ (s) = 1 + a ₁ / s… (37) F ₂ (s) = 1 + a ₂ / s… (38) F ₃ (s) = 1 + a It becomes ₃ / s… (39).

At this time, H (s) is Is asked.

In the above equation (40), H (s) represents the transfer characteristics of the input signal and the output signal, and the first term on the right side of H (s) is 2
The second, second, and third terms show fourth-order and sixth-order characteristics, respectively. Since H (s) is a combination of stable second-order characteristics, H (s) is stable regardless of its higher order.

When G ₁ = 0 and G ₂ = 0, H (s) has only the first term on the right side of the equation (40) and has a secondary characteristic, and a fast transient response characteristic is obtained.

If G ₂ is increased with G ₁ = 0, the first right side
The term gradually decreases, the second term on the right side gradually increases, and the quartic characteristic becomes dominant. And when G ₁ = 0 and G ₂ = 1 the right side of H (s) is only the second term,
It has a fourth-order characteristic.

Next, when G ₁ is gradually increased with G ₂ = 1
The second term on the right side of (s) gradually decreases, the third term on the right side gradually increases, and the sixth-order characteristic becomes dominant.

When G ₁ = 1 and G ₂ = 1 are satisfied, the right side of H (s) has only the third term and has a sixth-order characteristic. Summarizing the above, H (s) = secondary characteristic G ₁ = 0, G ₂ = 0 H (s) = intermediate characteristic between second and fourth order G ₁ = 0, 0 <G ₂ <1 H (s ) = Quaternary characteristics G ₁ = 0, G ₂ = 1 H (s) = Intermediate characteristics between 4th and 6th order 0 <G ₁ <1, G ₂ = 1 H (s) = 6th order characteristics G ₁ = 1, G ₂ = 1.

By controlling G ₁ and G ₂ in this way, H (s) is 2
It changes from the next wide band characteristic to the sixth narrow band characteristic.

For example, the higher the order of the phase locked loop circuit, the greater the noise suppression effect, but the slower the transient response. Therefore, the values of G ₁ and G ₂ may be set so that the phase locked loop circuit can obtain desired characteristics, for example, noise characteristics in the loop, response speed, and the like.

BACKGROUND ART Conventionally, circuit constants of a phase synchronization circuit, for example, filter constants have been adaptively and automatically controlled according to an input signal and a state inside the phase synchronization circuit. Such automatic control is performed by the above-described phase synchronization circuit. Can also be applied in. For example, when a signal is input, G ₁ = G ₂ = 0 is set so that this phase locked loop circuit has a second-order characteristic, and a fast pull-in response is realized. There is a method of increasing the noise suppression effect by setting G ₁ = G ₂ = 1 so that the sixth order characteristic is obtained when synchronized with the signal.

Also, measure the frequency difference between the input signal and the output signal of this phase locked loop.If the frequency difference is large, set G ₁ and G ₂ to have wideband characteristics to speed up the pull-in, and make the frequency difference small. So that it has a narrow band characteristic
A method of changing G ₁ and G ₂ is also possible.

This phase-locked circuit was constructed by connecting three sets of phase-locked circuits in parallel. Based on this, as shown in FIG. 11, there are n phase-locked circuits PLL1 and PLL2 having secondary characteristics.
… It is possible to connect PLLn in parallel. That is, in this case, n−1 attenuators (G ₁ , G ₂ , G ₃ , ..., Gn
By changing each attenuation ratio in ( ₁ ), the transfer function H (s) from the input signal to the output signal of the n-th phase locked loop PLLn changes from the 2nd order to the 2nth order.

That is, H (s) is quadratic G ₁ = 0, G ₂ = 0, ... Gn-2 = 0, Gn-1 = 0 between 2nd and 4th orders G ₁ = 0, G ₂ = 0, ... Gn- 2 = 0, 0 <Gn-1 <1 4th order G ₁ = 0, G ₂ = 0, ... Gn-2 = 0, Gn-1 = 1 between 4th order and 6th order G ₁ = 0, G ₂ = 0, ... 0 <Gn-1 <1 , Gn-1 = 1 6 primary _{G 1 = 0, G 2 =} 0, ... Gn-2 = 1, Gn-1 = 1 2n-2 primary G ₁ = 0, G ₂ = 1 ... Gn-2 = 1, Gn-1 = 1 2n-2 order and 2n between: _{0 <G 1 <1, G} 2 = 1 ... Gn-2 = 1, Gn-1 = 1 2n Next G ₁ = _1, the _{G 2 = 1 ... Gn-2} = 1, Gn-1 = 1. Therefore, a wider range of order control becomes possible,
In the 2n order, an output with suppressed noise can be obtained.

Another embodiment of the present invention based on such a phase locked loop will be described below.

FIG. 12 is a block diagram showing the configuration of a phase locked loop circuit according to another embodiment of the present invention.

That is, as shown in the figure, the phase-locked loop of this embodiment is composed of N sets of phase-locked loops PLL1, PLL2 ... PLLN, and the first phase-locked loops PLL1 to N-1. Up to PLLN-1 are connected in parallel, and the Nth phase-locked loop PLLN is connected in series after the N-1th phase-locked loop PLLN-1. Therefore, according to the phase-locked loop circuit configured in this way, the noise suppression capability can be further improved compared to the above-mentioned phase-locked loop circuits. In addition, all the above-mentioned circuit explanations are based on analog circuits. , The circuit configuration by the digital signal processing type that realizes the operation by the multiplication, addition, and delay of binary data after the AD conversion of the input signal by using the conventional technology described in the document "How to use PLL-IC" Conceivable. Also in that case, the loop order control and the band control can be easily performed as in the above-described embodiment.

[Effects of the Invention] As described above, according to the present invention, it is possible to realize a stable high-order phase locked loop and obtain an output with suppressed noise. In addition, the order can be easily controlled, and the loop band can be controlled according to the input signal-to-noise ratio.

[Brief description of drawings]

1 is a block diagram showing the configuration of a phase locked loop circuit according to an embodiment of the present invention, FIG. 2 is an equivalent block diagram focusing on the phase of the phase locked loop circuit shown in FIG. 1, and FIG. 3 is an amplitude limiting circuit. FIG. 4 is a block diagram showing the configuration of an example of the configuration, FIG. 4 is a characteristic diagram of a soft limiter in the amplitude limiting circuit shown in FIG. 3, and FIG. 5 is a characteristic diagram of a bandpass filter in the amplitude limiting circuit shown in FIG. FIG. 7 is a block diagram showing the configuration of another example of the amplitude limiting circuit, FIG. 7 is a characteristic diagram of a hard limiter in the amplitude limiting circuit shown in FIG. 6, and FIG. 8 is a bandpass filter of the amplitude limiting circuit shown in FIG. FIG. 9 is a block diagram showing the configuration of a phase locked loop which is the basis of another embodiment of the present invention, and FIG. 10 is an equivalent block diagram focusing on the phase of the phase locked loop shown in FIG. , Fig. 11 shows the configuration of the phase-locked loop of the application example of Fig. 10. Block diagram, FIG. 12 is a block diagram showing a configuration of a phase synchronizing circuit according to another embodiment of the present invention,
FIG. 13 is a block diagram showing the configuration of a conventional phase locked loop,
FIG. 14 is an equivalent block diagram focusing on the phase of the phase locked loop circuit shown in FIG. 9 ... First phase-locked circuit 10 ... Second phase-locked circuit 11 ... Third phase-locked circuit 12 ... First phase comparator 13 ... First loop filter 14 ... First Voltage-controlled oscillator 16 ... First attenuator 17 ... Inverter 18 ... Second phase comparator 19 ... First adder 20 ... Second loop filter 21 ... Second voltage-controlled oscillator 22 …… Second attenuator 23 …… Third phase comparator 24 …… Second adder 25 …… Third loop filter 26 …… Third voltage controlled oscillator

Claims (2)

(57) [Claims] 1. At least three sets of phase-locked circuits each comprising at least a phase comparator, a loop filter, and a voltage-controlled oscillator, wherein a received signal is input to the first and second phase-locked circuits,
A predetermined output corresponding to the output of the phase comparator of the first phase locked loop is superimposed on the input of the loop filter of the second phase locked loop, and the output of the voltage controlled oscillator of the second phase locked loop is obtained. Third
And a predetermined output corresponding to the output of the phase comparator of the second phase-locked circuit is superimposed on the input of the loop filter of the third phase-locked circuit to obtain the third phase-locked circuit. A phase locked loop circuit characterized in that the output of the voltage controlled oscillator of the circuit is used as the output signal. 2. A plurality of phase-locked circuits receiving a received signal as input, and a set of phase-locked circuits receiving the output of a voltage-controlled oscillator of a predetermined set of these phase-locked circuits. The phase locked loop circuit according to claim 1, wherein: