JPH02250429A - Phase synchronizing oscillator - Google Patents

Abstract

PURPOSE:To attain phase synchronization with a synchronous signal at high speed with a simple constitution by comparing the phases of an oscillated output, a synchronous signal and the output of a 2nd delay means and selecting one among the outputs of a 1st delay means. CONSTITUTION:A comparator section 105 compares the phase of the output of an oscillation section 101, the output of an input section 103, and the output of a 2nd delay element of a 2nd delay section 104 respectively and a selection section 106 selects an optional output among the output of the input section 103 and the output of a 1st delay element of the 1st delay section 102 by using the output of the comparator section 105. Thus, no low pass filter is required and the oscillator is constituted of logic circuits only, miniaturization is facilitated by circuit integration, the response speed is fast and the stable phase synchronizing oscillator is realized.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a phase-locked oscillator.

2. Description of the Related Art In recent years, phase-locked oscillators have been used in fields such as memory control.

The conventional phase-locked oscillator described above will be described below with reference to the drawings.

The conventional one-phase synchronization type firing device is PLL (Phase
It is common to use a Locked Loop device.

FIG. 4 is a block diagram showing the configuration of a conventional phase-locked oscillator.

401 is a voltage control oscillation unit (hereinafter referred to as vCO) that oscillates at a predetermined frequency fN, 402 is an input unit that inputs a synchronization signal of frequency fo that is a phase reference, and 403 is a VCO.
401 (a dividing unit which divides the ll force by 1/Atm to obtain a signal with a frequency of fH'; 404 is a phase comparison unit which compares the phase of the output of the input unit 402 and the output of the frequency dividing unit 403; 405
is a low-pass filter (hereinafter referred to as LPF) for smoothing the error signal, which is the output of the phase comparator 404, to a DC potential.
). 406 is an output unit for outputting the output of the VCO 401 to the outside.

In the phase-locked oscillator configured as above,
The frequency fN discovered by the VCO 401 is sent to the frequency divider 403
The frequency is divided by 1/A and becomes the frequency and fH. A phase comparison unit 404 compares the phases of this fu' and a synchronization signal having a frequency fo inputted from the input unit 402. If fHo is a leading phase with respect to fo, a period “L” corresponding to the amount of phase lead is determined.
” is output, converted to DC potential V^ through LPF405, and supplied to VC04011::VCO401
lowers the oscillation frequency in response to this potential V^. Also i
If fu' is a delayed phase with respect to H, the phase comparator 404 outputs "H" for a period corresponding to the amount of phase delay, and the LPF 4
Convert to DC potential VB through VC0401i
:: Supply. vC0401 increases the oscillation frequency in response to this potential Va.

By constantly applying a closed loop and comparing the phases in this way, it is possible to obtain an oscillation output whose phase matches that of the input synchronization signal.

Problems to be Solved by the Invention However, in the conventional configuration as described above, in order to execute the intended operation, it is necessary to provide the LPF 405, and also to increase the response speed (and increase the VCO 401).
It is necessary to have a sufficient pull-in range, which imposes large circuit constraints, making it difficult to provide an inexpensive, compact, and high-speed phase-locked oscillator.

In view of the above, an object of the present invention is to provide a phase-locked oscillation device that has a simple configuration and can perform phase synchronization with a synchronization signal at high speed.

Means for Solving the Problems In view of the above, the present invention includes a first delay section constituted by a plurality of first delay means connected in series to the oscillation output;
a second delay section constituted by a plurality of second delay means connected in series to the synchronization signal;
and a selection section that selects one of the oscillation output and the output of the first delay means based on the comparison result of the comparison section. .

Operation The present invention, with the above-described configuration, can realize a phase-locked oscillation device that does not require a low-pass filter, can be configured entirely by logic circuits, can be easily miniaturized by using an IC, has a fast response speed, and is stable.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a phase-locked oscillator according to an embodiment of the present invention. In FIG. 1, 101 is an oscillation unit that oscillates a predetermined frequency, and 102 is a first delay element 10.
2+ and the first delay element 102 are connected in series.
103 is an input section into which a synchronization signal is input;
4 from the second delay element 1041 to the second delay element 104
．． A second delay section 105 is connected in series with the excavation section 10.
1 output, the output of the input section 103, and the second delay section 104
A comparison unit 106 compares the phase with the output of each second delay element constituting the input unit 103, and a comparison unit 106 compares the phase with the output of each second delay element constituting the first delay unit 102. Based on each output of the comparison unit 105, an arbitrary one is selected by the selection unit,
Reference numeral 107 denotes an output section that outputs the output of the selection section 106 to the outside.

FIG. 2 shows a specific configuration example of the block diagram shown in FIG. 1.

In FIG. 2, 200 is an excavation section composed of an inverting buffer 201, a feedback resistor 202, a crystal oscillator 203, and oscillation frequency adjustment capacitors 204 and 205, 206 is an input section into which a synchronization signal is input, and 207 is an input section. Delay element 208 and delay element 20 that delay the output of 208 for a predetermined time
9 is the second delay section connected in series, 210 is the input of the second delay section 207, the output of the delay element 208 in the second delay section 2C) 7, the output of the delay element 209, and the oscillation section 2
Comparison elements 211 and 2 each compare the phase with the output of 00.
This is a comparison section composed of 12°213. The comparison element here is a D-type flip-flop (hereinafter referred to as D-type flip-flop).
(referred to as FF). Delay elements 215 and 216.2 214 delay the output of the oscillation unit 200 by a predetermined time.
17 and 218 are connected in series, a first delay section 219
220 is a selection unit that selects one output from the output of each delay element constituting the first delay unit 214 and the output of the oscillation unit 200 according to the output result of each comparison element constituting the comparison unit 210; This is an output section that outputs the output of the section 219 to the outside.

The phase-locked oscillator of this embodiment configured as described above will be described in detail below.

FIG. 3 is a timing chart for explaining the operation of FIG. In the figure, (a) shows the synchronization signal input to the input section 206, and (b) shows the delay element 208 in the second delay section 207.
(C) is the output of the delay element 20 in the second delay section 207.
9, (d) is the output of the oscillation unit 200, (e)
(f), (g), and (h) are delay elements 215, 216, 217, and 218 in the first delay section 214, respectively.
The output of (i) is the output of the selection unit 219.

Synchronization signal (a) input from the outside and second delay section 2
The outputs (b) and (C) of 07 are respectively input to the clock terminals of the D-FF constituting the comparator 210. Then, the output ω) of the oscillation unit 200 is input to the data input terminal of each D-FF. At time T1 when the synchronization signal rises, D-
The Q output of FF211 is "L" D-FF212. D-FF
The Q output of 213 is unstable. At time T2, D
- Q output section of FF211 - Q output of FF212 together
The Q output of D-FF213 is undefined, and at time T3, the Q outputs of D-FF211, 212, and 213 are all “L”.
This information is input to the selection input of the selection section 106, and the output (g
) and output it as output (i). In this case, the output (i) at time T4 when the synchronization signal falls and the synchronization signal (
The phase difference with a) is TI. If the oscillation phase or oscillation frequency of the oscillation unit 200 changes slightly before the next synchronization signal is input, for example, the Q output of the D-FF 211 at time T6 changes from the previous "L" to "H". Change. Therefore, the selection in the selection section 106 is switched from the previous signal (g) to signal (f). Time T again? r'r
Since the outputs of the D-FFs 212 and 213 at
The output (f) is output as the output signal (i). In this case as well, the phase difference between the output (i) and the synchronization signal (a) at time T9 when the synchronization signal falls is t times, and the phase relationship is exactly the same as when the first synchronization signal is input. can be kept.

As described above, according to the phase-locked oscillator of this embodiment,
Stable phase synchronization method that does not require a low-pass filter and does not require consideration of the time constant of the low-pass filter, can be assembled entirely with logic circuits, is easy to integrate into an IC, and has a fast response speed. An oscillation device can be realized.

Note that although a crystal oscillation element is used in the oscillation section 101 in this embodiment, an RC type or LC type oscillator may also be used. Also,
Although a D-FF is used in the comparing section 105, an R-8 type flip-flop, a J-type flip-flop, or the like may be used.

Effects of the Invention As described above, the present invention does not require a low-pass filter, which was necessary in the past, and can realize a high-speed, highly stable, and compact phase-locked oscillator, and its effects are extremely large.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a phase-locked oscillator according to an embodiment of the present invention, FIG. 2 is a block diagram showing a specific configuration example of FIG. 1, and FIG. 3 is a block diagram of a specific configuration example of FIG. 2. A timing chart for explanation and FIG. 4 is a block diagram of a conventional phase-locked oscillator. 101...Oscillation section, 102...First delay section, 103...Input section, 104...
・Second delay section, 105... Comparison section, 106.
... Selection section, 107... Output section.

Claims (1)

[Claims] A phase-locked oscillator device comprising an input section that inputs a synchronization signal from the outside, an oscillation section that oscillates a signal of a predetermined frequency, and an output section that outputs an oscillation output whose phase is synchronized with the synchronization signal, A first delay section configured by a plurality of first delay means connected in series to the output of the oscillation section, and a plurality of second delay means connected in series to the output of the input section. a second delay section; a comparison section that performs phase discrimination between the output of the oscillation section, the output of the input section, and the output of each second delay means forming the second delay section;
a selection section that selects one of the outputs of the oscillation section and the outputs of each first delay means constituting the first delay section and outputs it to the output section according to a comparison result of the comparison section; A phase-locked oscillator characterized by having: