JPS63146613A - Delay circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay circuit that generates an output signal that is delayed by a precise length with respect to an input signal.

These circuits are commonly called "delay lines" and have many uses. For example, delay lines are commonly used in mud-separated phase-locked loops used in disk drive devices. Delay lines are also used to obtain optimal timing for controlling the high speed RAM devices that make up the main memory of almost all personal computers.

PRIOR ART AND PROBLEM TO BE SOLVED BY THE INVENTION One type of conventional delay line is comprised of multiple circuits, such as inverters, connected in series. Each inverter provides a delay of known length, and by tapping the outputs of different inverters along the delay line, outputs having different delays relative to each other are taken. Other types of delay lines include LC circuits and RC circuits. In order to obtain accurate delays, the parameters that affect the delays, such as process, temperature and voltage, must be very tightly controlled. It has proven very difficult to achieve accurate delays in integrated circuit delay lines. Obtaining and maintaining the desired delay is difficult due to the number of parameters involved and the fact that the parameters change over time. Not only is it difficult to obtain accurate delays, but efforts to achieve accurate delays by tightly controlling various parameters have increased the cost of manufacturing integrated circuits.

[Means for solving problems]

The present invention is directed to a delay line that includes a fuse lock lube to obtain and maintain accurate delay. The present invention provides that the delay due to integrated circuits is not very accurate, but
It takes advantage of the fact that the delays caused by The delay line of the present invention includes a plurality of matched variable delay circuits. These delay circuits perform a function similar to voltage controlled oscillators in phase-locked loop circuits. A reference frequency source (typically a fixed frequency crystal oscillator, but could also be a variable frequency source such as a voltage controlled oscillator) is connected to the input terminal of the delay line. A phase detector is provided to compare the phase of the output of the delay line with the phase of the input of the delay line. An error signal representative of the phase error is generated and applied to a control input of the delay line to change the length of the delay and eliminate the phase error.

In the absence of phase errors, the delay line introduces a delay equal to an integer number of periods of the reference frequency. If the reference frequency is very accurate (such as when using a crystal oscillator), then the delay provided by the delay line will also be accurate. Changes in parameters such as voltage and temperature changes that affect the delay line are compensated for. This is because the phase-locked loop circuit constantly modifies the control provided to the delay line to provide the desired delay.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a very precise periodic signal from a crystal oscillator 10 is used to obtain the precise desired delay. Variable frequency sources such as voltage controlled oscillators can be used in certain applications. The output of the crystal oscillator 10 will be named O8C.

The output O8C is given to the variable delay circuit 12.

Then, the variable delay circuit 12 generates a delayed output DOSC according to its output. The length of the delay provided by variable delay circuit 12 is controlled by a control signal provided on line 14.

Signals O8C and DOSC are applied to a phase detector 16 which provides an error signal on line 14 in response to detecting the phase difference between the two signals. Therefore, the DOSC signal is O
If the 8C signal is not delayed relative to the OSC signal by exactly one period or more, an error signal will be generated on line 14 because a phase error exists. The length of the delay is varied depending on the magnitude of the error signal. The phase detector 16 is
A harmonic error detection circuit may also be included so that the delay is equal to one period of signal O8C rather than many periods.

Crystal oscillator 10, variable delay circuit 12, and phase detector 1
6 constitutes a phase-locked loop circuit that causes the variable delay circuit 12 to delay exactly equal to one clock period of the output of the crystal oscillator. The control signal provided to line 14 and used to control the length of the delay may be provided to second delay line 18. Since the second delay line has the same circuit configuration as the variable delay circuit 12, the delay length is the same. The second delay line 18 has a number of delay output taps, each output tap has a different delay length, and the data signal D
Can be used to delay the ATA by the desired length.

For example, the delay line 18 used in the data separator can be used to precompensate writes and generate window signals used for data separation. For certain applications, delay circuit 12 may be used to obtain multiple control signals having a predetermined relationship. In those applications, delay line 18 is not used.

The operation of a particular embodiment of the invention will now be described with reference to FIGS. 2A and 2B. The delay circuit 12 is composed of a plurality of blocks D1 to D16 connected in series and an end block L. Each delay block D1-D16 is composed of a CMOS inverter pair. Each inverter pair has a modulated current source to vary its switching speed. Control signals VCP and VCN are provided to each block to modulate the supply of current to the CMOS inverters to vary the switching speed and the length of delay provided by the overall delay circuit.

The signal O8C from the crystal oscillator is sent to the buffer inverter 20
, 22 and the initial delay block Dx to the delay circuit. so that the delay in each block is the same,
End blocks are provided to shape the waveform of the signal so that each block of the delay circuit operates on the same type of signal.

A basic phase detection operation for detecting a phase error between the output of the oscillator and the output of the delay circuit 12 is performed by D-type flip-flops FFI and FF2. flip flop FFI
is clocked by a signal O8C (which signal O8C is provided via an inverter 20°22, an end block Dx, and an inverter 24°26; the delays of those inverters and end blocks account for the operation of this circuit. (ignored in explanation). Signal DO3C clocks flip-flop FF2 via inverter 28.30 (coordinating the delay due to passing through inverter 24.26). The inverter 24°26.28.30 acts as a buffer for the flip-flop power.

The outputs of flip-flops FFI and FF2 drive Nant gates 32 and 34. The outputs of these Nant gates are provided to charge pump 35 (Figure 2B). Generates charge pump control signals vCP and VCN. Nantes Gate 32
．． Depending on the output of 34, the charge pump MOS capacitor 36.38 is charged or discharged to the control voltage vC.
Change the values of P and VCN. These control voltages are applied to delay circuit 12 to vary the length of delay provided by each delay block. The delay is the shortest when the control voltage vCP is zero volts.

Correctly determine whether the delayed signal DO3C leads or lags the phase of the crystal oscillator signal O8C 3
To perform the cycle phase comparison, the present invention uses another D-type flip-flop FF3 and its associated control circuitry (methods other than three-cycle phase comparison can also be used). Therefore, the modification of control signals VCP and VCN is always in the correct direction. That is, when the delayed signal is ahead of the oscillator signal, the delay is lengthened, and when the delayed signal is behind the oscillator signal, the delay is shortened.

FIG. 6 is a timing diagram showing the three-cycle comparison operation of the circuit shown in FIG. The circuit is configured such that when power is first applied to the circuit, the delay time of the delayed signal is less than one period of the oscillator signal O8C. Then, the phase lock operation is performed using the signal O8C.
The phase locking operation increases the delay until locking is achieved with a delay of one period of . This eliminates locking on harmonics (two or more periods of signal O8C). The D-type flip-flop FF4 minimizes the delay time when the power is turned on. When power is applied to the circuit, a 1u power supply reset pulse FOR is applied to the set input terminal of flip-flop FF4, causing the Q output of that flip-flop to go high. Its Q output conducts transistor 72 (FIG. 2B), discharging capacitor 36 and making signal CP equal to zero.

A power-on reset signal FOR is applied to the reset input terminal of flip-flop FF3. Therefore, when power is applied to the circuit, the Q output of the flip-flop is lowered. Six inverters 40 are connected to the output terminal of the flip-flop, and the output N EWE ST of the last inverter is also zero. This signal is a flip-flop FFI.

It is applied to the set input terminal of FF2 and one input terminal of Nant gate 42. The Q output of flip-flop FF1 is applied to the other input terminal of Nant gate 42.

The signal N EWE S T is the flip-flop FFI and F
Functions to set F2. Initially, the signal N
EWE ST is low, flip-flops FFI and F
Keep the Q output of F2 high. Therefore, Nantes Gate 4
The output of 2 is also high. The first rising edge (sixth
signal O8C clocks the flip-flop FF3 via the inverter 20°22, the delay block Dx and the inverter 24°44, passing the high signal at the data input terminal to the Q output terminal. pass to. Since the signal N EWE ST applied to flip-flop FFI is low, flip-flop FFI is not clocked by the first rising edge of signal O8C.

After a short delay provided by inverter 40, signal N EWE S T goes high and connects flip-flop F
Set FI and FF2. The flip-flops are therefore free to be clocked by the next rising edge of the signal applied to their respective clock input terminals.

Flip-flop FFI is clocked by signal O5C and flip-flop FF2 is clocked by signal DOS-- C. Therefore, the first signal O8C connects flip-flops FFI and FF2 to flip-flop FF
3-, thereby setting the second O8C
A signal (shown as "Compare" in FIG. 6) clocks flip-flop FFI, allowing signal DOSC to clock flip-flop FF2. Since the D input terminals of these two flip-flops are grounded, the Q outputs of those flip-flops are made low. Since signal DO3C is shown arriving before the second O8C signal in FIG. 6, flip-flop FF2 is clocked first. When flip-flop FFI is clocked, its Q output goes high and Nant gate 42 is closed. Therefore, the following O
8C signal (shown as "set" in Figure 6)
makes the Q output of flip-flop FF3 low, and the low Q output, after a short delay time through inverter 40,
Lower the signal N EWE ST. For this purpose, the Q outputs of flip-flops FFI and FF2 are increased. Those flip-flops are connected to the next O8C signal (in Figure 6, “
(denoted as "enabled state").

Therefore, the signal N EWE ST is transmitted through the window (“
(denoted as “Comparison Window”). A comparison of signals O8C and DOSC is made in that window. The window begins shortly after the occurrence of the first rising edge of signal O8C and allows the phase of the next rising edge of signal O8C to be compared with the phase of signal DOSC. The window is closed in response to the third rising edge of signal O8C, and the operating cycle is then repeated. Due to the generation of the window, the delayed signal DO8
C can be compared with the next rising edge of signal O8C rather than with the rising edge corresponding to that delayed signal (for example, in FIG. (compared to the ``compare'' edge of signal O8C rather than the ``enable'' edge). In this way, a correct determination is made regarding the direction of any phase error.

In order to make it acceptable even if the signal DO5C contains a small amount of jitter, an inverter 40 is provided so that the signal NE
Delay the generation of WEST (the delay is caused by the delay circuit 12
shorter than the shortest delay of ).

The inclusion of this short delay further reduces the chance of incorrectly determining the direction of a phase error.

The actual phase comparison operation performed by the circuit shown in FIG. 2 for various signals will be explained with reference to FIG. Signal O
3C is shown in FIG. 7A.

This figure shows that the signal O8C has three cycles "Set", "
It is indicated by "enabling" and "comparison".

The Q output of the flip-flop FFI is applied to the Nant gate 34 through an inverter 48, and the Q output of the flip-flop FFI is applied to the input terminal of the Nant gate 32 through five inverters 50. Similarly, the Q output of flip-flop FF2 is applied to the input terminal of Nandts gate 32 through five inverters 52, and the Q output of flip-flop FF2 is applied to the input terminal of Nandts gate 34 through five inverters 54. Inverter 50 and 5
4 is slightly delayed to prevent a dead zone in the operation of the charge pump.

A situation in which the phase of the delayed signal DO3C leads the phase of the signal O8C is shown in FIG. 7B. In this situation, the rising edge of signal DOSC is connected to flip-flop FF2.
is clocked to make the output of the Nant gate 32 low. The signal is shown as pump-up in FIG. 2 and shown in FIG. 7C. The low output activates the charge pump to charge capacitor 36 and increase the delay by raising the voltage above VCP. At the same time, the control voltage VCN of capacitor 38 is lowered. The function of the charge pump will be explained later. When the "compare" O8C signal arrives, the Q of flip-flop FF1 goes high, causing the pump-up signal to return to a high level after a delay time through inverter 50 (FIG. 7C).

The seventh diagram shows that the phase of the delayed signal DO3C is equal to the phase of the signal O8.
This shows the situation where it is behind C. In this situation the charge pump is discharged, lowering the voltage vCP at capacitor 36. As a result, the voltage across capacitor 38 and the voltage VCN become higher. [Comparison J O3C signal clocks flip-flop FFI and causes its Q output to go low, causing the output of Nant gate 34 to go low. The output pump down of inverter 56 (FIGS. 2, 7E) is therefore higher and is applied to the charge pump.

That signal discharges capacitor 36, causing voltage VcP to go low and voltage VCN to go high. A lower voltage vcp shortens the delay of signal DO3C, thereby making its phase equal to the phase of signal O8C.

As shown in FIG. 7F, if for some reason the delayed signal does not occur, the circuit raises the pump down signal to lower the voltage vCP, thus shortening the delay of the delayed signal. As shown in FIG.
It is reset to a lower level at the edge. Therefore, the comparison cycle begins with the shortest delay.

The present invention is configured to track changes in the relatively long delay of the delay circuit caused by factors such as changes in temperature and power supply voltage.

The three-cycle phase comparison operation used to correctly determine the direction of a phase error is fast enough to correct such long phase errors that occur within the system.

In conventional phase-locked loop circuits, the frequency difference between the signals whose phases are being compared (the reference frequency and the output of the voltage-controlled oscillator) causes the phase and frequency Finally, the locking can be performed. In the delay circuit of the present invention,
Since the signals being compared are generated from the same signal source, their frequencies are exactly the same. If the phase correction is done in the wrong direction, the correct length of delay cannot be obtained because phase lock cannot be achieved.

Therefore, it is for that reason that a multi-cycle phase comparison operation is used to ensure that all phase modifications can be made in the correct direction.

Next, the operation of the charge pump will be explained with reference to FIG. 2B.

In this figure, the conductivity type of the various transistors is designated P or N. The charge pump operates to charge capacitor 36 in response to a low pump up signal and discharge capacitor 36 in response to a high pump down signal. In the absence of either of those signals, the voltage on capacitor 36 (and thus the length of the delay) remains approximately constant.

The charge pump includes a precision current source formed by two diode-connected transistors 58, 60 and a resistor 62. This current source provides a reference current that determines the rate of charge and discharge of the capacitor. Capacitor 36 is charged by transistor 64 which is coupled to the positive power supply. The transistor 64 is selectively coupled to the capacitor 36 by a transistor switch 66. The transistor switch 66 is rendered conductive when the pump up signal goes high. Transistor 64 is electric! Since they are connected to transistor 58 in a mirror configuration, the currents flowing through the two transistors are equal. Accordingly, a controlled reference current is provided to capacitor 36 in response to the pump-up signal going low.

Discharge of capacitor 36 is controlled in a similar manner.

The discharge takes place through transistor 68 which is connected in a current mirror to transistor 60. The transistor 60 is coupled to the capacitor 36 by a transistor 70 which is rendered conductive when the pump down signal is high. The discharge is also explained later, and the transistor 7
Sometimes it is done through 2.

The charging and discharging of capacitor 36 as described above operates to vary the control voltage vCP applied to the variable delay line to modify the delay provided by the delay circuit. Although in some applications one control voltage is sufficient to control the delay, in the detailed described embodiment of the invention a second control voltage is also generated and applied to the delay circuit. . As will be explained in detail later, the delay circuit is constituted by a modulated inverter. In these inverters, the positive and negative supply transistors are modulated to vary the switching time.

A voltage VCP is applied to modulate the positive supply transistor and a voltage VCP is applied to modulate the negative supply transistor.
CN is given.

To generate voltage VCN from voltage vCP, the circuit of FIG. 2B balances the current through transistor 74, 76 at a point corresponding to the switching threshold of the inverter of the delay circuit. This is done by providing an inverter 78.

The inverter is constructed to resemble a delay inverter with transistors 80 and 82 connected between transistors 74 and 76. The input terminal of this inverter is coupled to its output terminal and is compared by a comparator 84 to a switching threshold.

Its switching threshold is 2.5 volts, i.e.
It is set to half the positive supply voltage of 5 volts.

The comparator is comprised of transistors 86-94 and operates to drive the base of transistor 76 until the input at the base of transistor 90 equals the voltage at the base of transistor 88, or 2.5 volts. In this way, the current through transistors 74 and 76 is set equal to the switching threshold of inverter 78 (and thus the inverter of the delay circuit). The voltage applied to transistor 76 is also applied to charge capacitor 38, thus generating control voltage VCN.

The delay circuit of FIG. 2 is constructed to delay signal O8C by exactly one period. In the most common application of the embodiment described herein, the period is 200 nanoseconds. However, since the phase comparator compares the rising edge of signal O8C with the delayed signal DOSC, signal O8C
It is possible to perform phase locking in a large number of cycles of C. This situation is shown in FIG. The delay circuit 12 is
As shown in FIGS. 8A and 8B, it is desirable to provide a delay of one clock period. That is, the delay circuit delays the rising edge of signals O8C and DOSC such that for any two signals being compared, the rising edge of signal DOSC is one period before the rising edge of signal O8C being compared. It is desirable to lock at the edges. This is indicated by arrow 100.

However, as shown in FIG. 8C and D, the signal O
The delay circuit actually locks on the rising edge of signal DO3C after 8C. In that case, the control voltages VCP and VCN are inappropriately controlled so that the modulated inverter of the delay circuit provides a delay of two clock periods or more instead of one clock period of signal O8C. Even if the delay circuit provides an inappropriate delay, the frequency of signal DO5C remains equal to the frequency of signal O8C because the delay circuit changes the delay time, not the frequency, of signal O8C passing through it.

The present invention includes circuitry that detects an inappropriate delay of more than one clock period (a "harmonic" error) and allows the circuit to be reset to reapply a one clock period delay of signal O8C. This is flip-flop FF4,
This is performed by a logic circuit including a Nant gate 104 and NOR gates 106 and 108. This circuit adjusts the waveform of the signal passing through the delay circuit 12 at a particular time to match the waveform that would be achieved if an appropriate delay of one period of the signal O8C were made. This circuit operates to monitor the waveform of . If the two waveforms do not match, flip-flop FF4 generates an error signal. The error signal causes transistor 72 (FIG. 2B) to conduct, causing capacitor 36 to discharge. Control voltage VCP is then brought to zero, resetting the circuit to its shortest delay.

The initial phase lock achieves a one period delay since any subsequent phase modification can only lengthen the delay. It should be noted that flip-flop FF4 also causes transistor 72 to become conductive when power is most fully applied to the circuit to start the shortest delay.

Therefore, the output of flip-flop FF4 is shown as harmonic error/initialization.

The operation of delay circuit 12 is such that signals travel through delay circuit 12 such that they are summed at each stage. The overall delay at the final output is equal to the sum of the delays in the various stages. At any given time, the output of each stage is either a high level or a low level. For example, signal O
At the beginning of 8C, given the correct one period delay, delay blocks D1-D8 are at high level and blocks D9-D16 are at low level. In contrast, if the delay of the entire delay circuit is two periods, blocks D1-D4 and D9-D12 are at high levels, and blocks D5-D8 and D13-D16 are at low levels. By monitoring the state of various blocks of the delay circuit at particular times, a determination can be made as to whether the correct delay is being applied. The logic circuit shown in FIG. 2A performs this function. Flip-flop FF4 is clocked by the rising edge of signal O8C and passed through buffer inverters 24 and 110.

At this point, the outputs of blocks D2-D5 of delay circuits must be high, and their outputs inverted and provided to NOR gates 106, 108 are at a low level. Therefore, the output of the Nant gate 104 is also low, and the Q output of the flip-flop FF4 is low. However, assuming there is a harmonic error, the output of block D5 is low;
The inverted version of it given to Noah Gate 106 is high. For this purpose, the output of the Nant gate 104 is made high, so the Q output of the flip-flop FF4 is made high. This causes transistor 2 (FIG. 2B) to become conductive, discharging capacitor 36. The circuit is then reset to the shortest delay. Thus, the phase comparison operation lengthens the delay until phase lock occurs, at which point the delay is one cycle of signal O8C.

FIG. 3 shows the individual blocks D of the delay circuit 12. Each block consists of a pair of CMOS inverters coupled to supply transistors that are modulated by control signals VCP and VCH. The first inverter is transistor 1
12.114 included. Transistor 112 is coupled to transistor 116, which is coupled to a positive power supply. Similarly, transistor 114 is coupled to transistor 118, and transistor 118 is grounded.

The second inverter includes transistors 120, 122 connected to the positive power supply and ground by transistors 124, 126, respectively. MOS capacitors 128, 130 are provided to locally stabilize the voltage. Control voltage VCP and VC
By modulating N, the current supplied to the inverter is varied, thereby changing the switching speed of the inverter. The output of the second inverter is given to the input terminal of the next delay block, and can also be given as the output of the delay circuit via the buffer inverter 132. This inverted output is provided to the logic circuitry for harmonic detection for blocks D2-D5 and is the overall delayed output signal DO5C from block D16.

As shown in Figure 4, the last block of the delay circuit is
It consists of one modulated inverter including transistors 134, 136 and modulated transistors 138, 140. The purpose of this last block is that the output waveform D is the last block in the delay circuit.
The purpose is to ensure that the OSC is not affected.

The circuit of FIG. 2 uses a control voltage VCP to effect the desired delay.
This is for generating VCN.

However, since the signal oSC must be applied to the delay circuit 12 in order to be able to generate the control voltage, a second delay circuit 18 is provided to actually delay the data input signal. This delay circuit includes seven blocks DA-DC, which are the same as the blocks in delay circuit 12, as shown in FIG. Therefore, the control voltages vCP and VC
N gives blocks DA-DC the same delay as blocks D1-D16. Of course, the length of this delay is locked to the desired value by operation of the phase-locked loop circuit.

In the situation where a 200 nanosecond delay is provided by delay circuit 12, the length of the delay for each block of delay circuit 12.18 is 12.5 nanoseconds. The data signal is provided to delay circuit 18 via buffer inverter 142, and the outputs of the various blocks of delay circuit can be used to provide various desired signals. For example, to generate a window signal for data separation, the outputs of blocks DB and DC can be used to provide two signals with precise delays relative to each other. In this example, the two blocks are 5 blocks apart, so the total delay is 60 nanoseconds. Similarly, other outputs can be used to obtain delays of various lengths for purposes of pre-compensating writes. An inverter 144 is provided to obtain a signal with the appropriate polarity for application to subsequent logic circuits. Delay circuit 18 as input
It should be noted that the data signal provided to is not used as an undelayed signal to be provided to another circuit. Rather, two of the delayed signals are used since the delay between blocks is precisely known.

In summary, the present invention provides a phase-locked loop delay circuit that provides accurate delays as operating parameters such as temperature and temperature change, and whose processing can be widely varied during fabrication. The delay circuit includes a variable delay line in a phase-locked loop circuit, and phase-locked operation is used to generate a control voltage to control the length of delay provided by the delay line. Another delay line containing the same delay block is used to delay the data signal. The invention is particularly useful in devices where a crystal oscillator or other reference timing source is already included in the circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the circuit of the present invention, FIGS. 2A and 2B are block diagrams of portions of the circuit of the present invention, FIG. 3 is a block diagram of one delay block of the delay circuit, and FIG. is a block circuit diagram of the last element of the delay circuit, and FIG. 5 is a block circuit diagram of the delay circuit to which the data signal is applied.
6 to 8 are timing waveform diagrams related to the operation of the circuit of the present invention. 10... Crystal oscillator, 12.18... Variable delay circuit, 16... Phase detector, 20.22.24, 26, 28, 30, 40° 44.5
0,52.54 medium inverter, 104...Nant gate, 106.108...Noah gate, D1-D16. Dx, L...delay block. Procedural Manual (Method) December 25, 1988 Mr. Commissioner of the Patent Office
-Be, X. 1. Indication of the case Patent Application No. 251433 filed in 1988 2. Title of the invention Delay circuit 3. Relationship with the person making the amendment Patent applicant Western, Digital, Corporation 4, Agent
Person 2-11-2 Ginza, Chuo-ku, Tokyo 104 December 2, 1988 (shipment date December 22, 1988) 6. Drawings subject to amendment 7, Contents of amendment

Claims (29)

[Claims] (1) A reference frequency source that generates a periodic input signal, a variable delay circuit that receives the input signal and generates an output signal delayed with respect to the input signal, and a variable delay circuit that determines the phase between the input signal and the output signal. and a controller for varying the length of the delay provided by the delay circuit to achieve the desired phase relationship, so as to obtain a signal with an accurate delay relative to the digital input signal. Features a delay circuit. (2) the delay circuit includes a control input terminal receiving a control voltage to control the length of the delay; and the controller includes means for generating the control voltage as a function of a phase difference between the input signal and the output signal. A delay circuit according to claim (1). (3) The controller includes means for determining whether the phase of the input signal leads or lags the phase of the output signal, and changing the control voltage in the first direction or the second direction depending on the determination. A delay circuit according to claim (2), characterized in that: (4) The means for generating the control voltage includes a charge pump having a capacitor that is charged or discharged, and the determining means includes a capacitor in the charge pump when the phase of the input signal leads the phase of the output signal. The present invention is characterized by generating a first signal that causes the charge pump to charge the capacitor in a first direction, and generating a second signal that causes the charge pump to charge the capacitor in the opposite direction when the phase of the input signal lags the phase of the output signal. A delay circuit according to claim (3). (5) means for determining receives an input signal and an output signal, generates a first signal during a time between a rising edge of the input signal and a next rising edge of the output signal; 5. A delay circuit according to claim 4, further comprising a phase detector for generating the second signal during the time between the second rising edge of the input signal and the next rising edge of the input signal. (6) A phase detector comprises: a first D-type flip-flop set by the rising edge of the input signal; a second D-type flip-flop set by the rising edge of the output signal; a first logic gate operatively coupled to receive an output and generate the first signal; and a first logic gate operatively coupled to receive an output from each flip-flop and generate the second signal. 5. The delay circuit according to claim 5, further comprising a second logic gate coupled thereto. (7) The delay circuit according to claim (6), further comprising a harmonic controller that delays the output signal with respect to the input signal by a predetermined number of cycles of the input signal. (8) the predetermined number is 1, and the harmonic controller includes means for monitoring the output signal to determine whether the output signal has a desired timing relationship to the input signal; 8. A delay circuit according to claim 7, further comprising means for modifying the operation of the circuit to achieve a one period delay when detected. (9) The means for modifying includes means for resetting the delay circuit to obtain the shortest delay, such that the delay circuit is then operated to achieve a one period delay of the input signal. 9. The delay circuit according to claim 8, wherein the delay circuit increases the delay time of the delay circuit. (10) The delay circuit according to claim (2), wherein the delay circuit includes a plurality of inverters connected in series and means for modulating the switching speed of the inverters. (11) Each inverter is comprised of a CMOS transistor pair, and the means for modulating includes additional transistors coupled between the inverters and the power supply connection to modulate the switching speed of those inverters by modulating the current supplied to the inverters. 11. The delay circuit according to claim 10, wherein a control voltage is applied to an additional transistor that modulates the delay circuit. (12) means for providing a periodic digital input signal of a reference frequency; variable delay means for receiving the input signal and generating an output signal delayed with respect to the input signal; receiving and outputting the input signal and the output signal; It is characterized by comprising a phase lock controller that controls the delay means so that the phase of the signal is fixed with respect to the input signal, and provides a signal with an accurate delay with respect to the periodic digital input signal. delay circuit. (13) The delay circuit according to claim (12), wherein the controller includes means for delaying the output signal with respect to the input signal by a predetermined number of cycles of the input signal. (14) The controller compares the phase of the input signal with the phase of the output signal, generates a first error signal when the phase of the input signal leads the phase of the output signal, and generates a first error signal when the phase of the input signal leads the phase of the output signal. a phase comparator that generates a second error signal when the phase lags behind the phase of the second error signal; and a corrector that generates a control signal that controls the length of delay of the delay means in response to the error signal. A delay circuit according to claim (13). (15) the corrector includes a charge pump having a capacitor charged in a first direction in response to a first error signal and charged in a second direction in response to a second error signal; Claim (14) characterized in that the voltage across the terminals of the capacitor is a control signal for controlling the delay means.
Delay circuit described in section. (16) Claim (15) characterized in that the delay means includes a plurality of inverters connected in series, and means for changing the delay of the delay means by changing the switching speed of the inverters. Delay circuit as described. (17) each inverter is comprised of a pair of CMOS transistors, and the means for changing includes a plurality of first supply transistors coupled between the first power supply connection and the inverter to control the current supply to the inverter. , the supply transistors being driven by a control signal from a capacitor. (18) the means for modifying includes a plurality of second supply transistors coupled between the first power supply connection and the inverter to control the current supply to the inverter; 18. The delay circuit according to claim 17, further comprising means for generating a second control signal for driving the delay circuit. (19) The first supply transistor is a MO of the first conductivity type.
the second supply transistor is a MOS transistor of a second conductivity type, and the means for generating the second control signal determines the value of the second control signal as a function of the value of the first control signal. 19. The delay circuit according to claim 18, wherein the delay circuit is configured to control the delay circuit. (20) The means for generating the second control signal includes a first control MOS transistor driven by the control signal, a second control MOS transistor, and a second control MOS transistor connected to the gate of the second control transistor.
a current controller for driving the second control transistor such that the current flowing through the second control transistor has a predetermined relationship with the current flowing through the first control transistor; 19. The delay circuit according to claim 19, wherein the voltage of the capacitor is the second control signal. (21) CMOS whose input terminal is connected to the output terminal
an inverter; a comparator that compares the output of the inverter with a reference voltage and drives a second control MOS transistor until the output of the inverter is equal to the reference voltage;
21. The delay circuit according to claim 20, wherein the S transistor and the second control MOS transistor are connected to supply current to the inverter. (22) The delay circuit according to claim (21), wherein the reference voltage is approximately equal to the switching voltage. (23) a reference frequency means that generates a periodic output signal; a first variable delay circuit that receives the output of the reference frequency means and generates an output signal having a delay determined by a control signal; and a reference frequency means. Compare the phase of the output signal of the variable delay circuit with the phase of the output signal of the variable delay circuit, generate a control signal to fix the output signal of the variable delay circuit to the phase of the output of the reference frequency means, and send the control signal to the variable delay circuit. a second variable delay circuit that receives a digital input signal and generates an output signal delayed with respect to the input signal, the control signal being applied to the second delay circuit to delay the input signal; The change in delay of the first delay circuit in response to changes in the control signal controls the length of the delay circuit in the second delay circuit in response to the same change in the control signal.
A delay circuit characterized in that the delay length of the delay circuit is proportional to the delay length of the delay circuit. (24) having a reference frequency source that generates a periodic reference signal, a first input terminal that receives the reference signal, and a control input terminal that receives a control signal, having the same frequency as the reference signal and determined by the control signal; a variable delay circuit for generating a periodic output signal delayed with respect to a reference signal by a length of time; and determining the direction of a phase error between the reference signal and the output signal;
comprising means for changing the control signal in a direction that reduces the phase error, and comparing the phase between the reference signal and the output signal;
a controller for providing a control signal to the delay circuit to vary the length of the delay to achieve a desired phase relationship, the controller comprising: a controller for providing a control signal to the delay circuit to vary the length of the delay to achieve a desired phase relationship; A delay circuit characterized by: (25) The controller includes means for setting the control signal to an initial value, resulting in a delay that brings the initial phase error into a known orientation.
4) Delay circuit described in section 4). (26) The controller compares the phases of the reference signal and the output signal, generates a first error signal when an error is detected in the phase in the first direction, and generates a second error signal.
a phase detector that generates a second error signal when an error in orientation is detected; and a charge pump that receives the error signals and generates a control signal in response to the error signals. A delay circuit according to claim (24). (27) The phase detector comprises: a first D-type flip-flop clocked by the rising edge of the reference signal; a second D-type flip-flop clocked by the rising edge of the output signal; and a second D-type flip-flop clocked by the rising edge of the output signal. Enabling the flip-flop in response to one rising edge allows the first flip-flop to be timed by the next rising edge of the reference signal, and allows the first flip-flop to be timed by the next rising edge of the output signal. 27. The delay circuit according to claim 26, further comprising: a phase comparison controller for generating an error signal; and logic means connected to the output terminal of the flip-flop to generate an error signal. (28) The phase comparison controller includes a third D-type flip-flop clocked by the rising edge of the reference signal, and the output of this third flip-flop enables the first flip-flop and the second flip-flop. 28. The delay circuit according to claim 27, wherein the delay circuit is set to the state. (29) the third flip-flop is configured to (a) enable the first flip-flop and the second flip-flop in response to a first rising edge of the reference signal to reference the first flip-flop; (b) responsive to a third rising edge of the reference signal occurring immediately after said next rising edge of the reference signal;
29. The delay circuit according to claim 28, wherein the delay circuit is configured to generate an output that resets the first flip-flop and the second flip-flop to a disabled state.