JPS57174928A - Adjusting circuit for delay time - Google Patents

Adjusting circuit for delay time

Info

Publication number
JPS57174928A
JPS57174928A JP6031281A JP6031281A JPS57174928A JP S57174928 A JPS57174928 A JP S57174928A JP 6031281 A JP6031281 A JP 6031281A JP 6031281 A JP6031281 A JP 6031281A JP S57174928 A JPS57174928 A JP S57174928A
Authority
JP
Japan
Prior art keywords
clock
point
output
delay time
vcd2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6031281A
Other languages
Japanese (ja)
Inventor
Hideyuki Obara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6031281A priority Critical patent/JPS57174928A/en
Publication of JPS57174928A publication Critical patent/JPS57174928A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Abstract

PURPOSE:To achieve a delay time adjusting circuit with high accuracy, by incorporating a voltage controlled delay circuit inputting a clock having equal clock with a specified delay time to a phase locked loop. CONSTITUTION:A clock oscillator 1 generting a clock having a period equal to a specified delay time is connected to an input point A of a VCD2. A phase locked loop is constituted by connecting a phase comparator 3, a charge pump circuit 4, a low pass filter 5, a DC amplifier 6 and a voltage fixing circuit 7, to the input point A and an output point B of the VCD2. If the clock frequency f1 at the point A and a clock frequency f2 at the point B are shifted, an output is given to the phase comparator 3 and a control voltage for the VCD2 is generated from the DC amplifier 6. The output of the DC amplifier 6 is constant when the phase of the f1 and f2 is equal and a fixed output is applied to the VCD2 with the circuit 7. Thus, a clock output with a specified delay can be obtained at the point B.
JP6031281A 1981-04-21 1981-04-21 Adjusting circuit for delay time Pending JPS57174928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6031281A JPS57174928A (en) 1981-04-21 1981-04-21 Adjusting circuit for delay time

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6031281A JPS57174928A (en) 1981-04-21 1981-04-21 Adjusting circuit for delay time

Publications (1)

Publication Number Publication Date
JPS57174928A true JPS57174928A (en) 1982-10-27

Family

ID=13138519

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6031281A Pending JPS57174928A (en) 1981-04-21 1981-04-21 Adjusting circuit for delay time

Country Status (1)

Country Link
JP (1) JPS57174928A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63146613A (en) * 1986-10-07 1988-06-18 ウエスタン、デジタル、コ−ポレ−ション Delay circuit
JP2012231460A (en) * 2011-04-25 2012-11-22 Fujitsu Ltd Method, circuit, and system for generating multiphase signal

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5537031A (en) * 1978-09-07 1980-03-14 Trio Kenwood Corp Phase synchronizing circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5537031A (en) * 1978-09-07 1980-03-14 Trio Kenwood Corp Phase synchronizing circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63146613A (en) * 1986-10-07 1988-06-18 ウエスタン、デジタル、コ−ポレ−ション Delay circuit
JP2012231460A (en) * 2011-04-25 2012-11-22 Fujitsu Ltd Method, circuit, and system for generating multiphase signal

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