JPS54129959A - Phase lock loop circuit - Google Patents

Phase lock loop circuit

Info

Publication number
JPS54129959A
JPS54129959A JP3763478A JP3763478A JPS54129959A JP S54129959 A JPS54129959 A JP S54129959A JP 3763478 A JP3763478 A JP 3763478A JP 3763478 A JP3763478 A JP 3763478A JP S54129959 A JPS54129959 A JP S54129959A
Authority
JP
Japan
Prior art keywords
signal
phase
circuit
vco
vco14
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3763478A
Other languages
Japanese (ja)
Inventor
Hiroo Fujita
Akira Tsuzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP3763478A priority Critical patent/JPS54129959A/en
Priority to DE19792912406 priority patent/DE2912406A1/en
Priority to US06/025,048 priority patent/US4244043A/en
Publication of JPS54129959A publication Critical patent/JPS54129959A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop

Abstract

PURPOSE:To focus a phase difference between reference input signal FS and voltage control oscillator VCO to zero, by equipping a PLL circuit with a method of controlling the phase of VCO by the output signal of a phase comparator circuit. CONSTITUTION:Reference input signal FS2(10) and output signal 11 of VCO14 are both inputted to phase comparator 3 and then a phase difference between both the signals is detected by circuit 3 to generate phase-difference pulse 12, which is supplied to charge pump circuit 4. circuit 4 gnerates a discharge pulse when the VCO signal leads the FS signal or a discharge pulse when the VCO signal lags the FS signal. Either charge or discharge pulse is applied to integrating circuit 5, whose output voltage is then applied to the control voltage terminal of VCO14, so that the oscillation frequency will vary with the phase. In this case, control voltage 13 from circuit 5 to VCO14 focuses to constant value VG through the phase control by applying the phase control signal from the output of circuit 3 to terminal 15 of VCO14, so that the phase difference between signal FS and the output signal of VCO will focus to zero.
JP3763478A 1978-03-31 1978-03-31 Phase lock loop circuit Pending JPS54129959A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP3763478A JPS54129959A (en) 1978-03-31 1978-03-31 Phase lock loop circuit
DE19792912406 DE2912406A1 (en) 1978-03-31 1979-03-29 FREQUENCY DIVIDER SYSTEM
US06/025,048 US4244043A (en) 1978-03-31 1979-03-29 Frequency division system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3763478A JPS54129959A (en) 1978-03-31 1978-03-31 Phase lock loop circuit

Publications (1)

Publication Number Publication Date
JPS54129959A true JPS54129959A (en) 1979-10-08

Family

ID=12503065

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3763478A Pending JPS54129959A (en) 1978-03-31 1978-03-31 Phase lock loop circuit

Country Status (1)

Country Link
JP (1) JPS54129959A (en)

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