KR880005599A - Phase-loked Loop Delay Lines - Google Patents

Phase-loked Loop Delay Lines Download PDF

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KR880005599A
KR880005599A KR870010215A KR870010215A KR880005599A KR 880005599 A KR880005599 A KR 880005599A KR 870010215 A KR870010215 A KR 870010215A KR 870010215 A KR870010215 A KR 870010215A KR 880005599 A KR880005599 A KR 880005599A
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signal
phase
control
delay
circuit
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KR870010215A
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Korean (ko)
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엠·제이·프로그렌 칼
웨슬리 쉬이러 제럴드
더불유·오엥 케네스
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어번 엘·콰텍
웨스턴 디지탈 코포레이숀
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Publication of KR880005599A publication Critical patent/KR880005599A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B19/00—Driving, starting, stopping record carriers not specifically of filamentary or web form, or of supports therefor; Control thereof; Control of operating function ; Driving both disc and head
    • G11B19/20—Driving; Starting; Stopping; Control thereof
    • G11B19/28—Speed controlling, regulating, or indicating
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/30—Time-delay networks
    • H03H9/38—Time-delay networks with adjustable delay time
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00097—Avoiding variations of delay using feedback, e.g. controlled by a PLL
    • H03K2005/00104—Avoiding variations of delay using feedback, e.g. controlled by a PLL using a reference signal, e.g. a reference clock
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/0013—Avoiding variations of delay due to power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Acoustics & Sound (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)

Abstract

내용 없음No content

Description

위상고정(phase-locked)루프 지연선Phase-Locked Loop Delay Lines

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 블록도표.1 is a block diagram of the present invention.

제2A도 및 2B도는 본 발명의 회로의 개략도표.2A and 2B are schematic diagrams of a circuit of the present invention.

제3도는 지연선 단일지연 블록의 개략도표.3 is a schematic diagram of a delay line single delay block.

Claims (29)

디지탈 입력신로에 관계하여 정확한 지연을 갖는 신호를 제공하기 위한 회로에 있어서 : 주기적 입력신호를 발생시키기 위한 기준 주파수 전원 : 입력신호를 수신하고 이 같은 입력신호에 대하여 지연된 출력신호를 발생시키는 가변 지연회로, 그리고 입력신호와 출력신호 사이의 위상을 비교하고 요구되는 위상 관계를 달성시키기 위해 지연회로에 위해 지연된 지연의 크리를 변화시키기 위한 제어수단을 포함함을 특징으로 하는 회로.A circuit for providing a signal having an accurate delay in relation to a digital input path, the circuit comprising: a reference frequency for generating a periodic input signal power supply: a variable delay for receiving an input signal and generating a delayed output signal for such an input signal Circuitry and control means for varying the amount of delay delayed for the delay circuit to compare the phase between the input signal and the output signal and to achieve the required phase relationship. 제1항에 있어서 : 지연회로과 지연의 크기를 조정하기 위한 제어전압을 수신하기 위한 제어입력을 포함함을 특징으로 하는 회로.The circuit of claim 1 including a delay circuit and a control input for receiving a control voltage for adjusting the magnitude of the delay. 제2항에 있어서, 제어수단이 입력신호의 위상이 출력신호의 위상에 앞서는지 혹은 뒤따르는지를 결정하고 이 결정에 응답하여 제1 또는 제2방향으로 제어전압을 변경시키기 위한 수단을 포함함을 특징으로 하는 회로.3. The apparatus of claim 2, wherein the control means comprises means for determining whether the phase of the input signal precedes or follows the phase of the output signal and for changing the control voltage in the first or second direction in response to the determination. Characterized by a circuit. 제3항에 있어서, 제어전압을 발생시키기 위한 수단이 충전되거나 방전되는 콘덴서를 갖는 충전펌프를 포함하며 콘덴서에 걸리는 전압제어 전압이고, 신호 위상의 앞서고 뒤섬을 결정을 위한 수단이 입력신호의 위상이 출력신호의 위상을 앞서는 때 충전펌프가 제1방향으로 콘덴서를 충전시키도록 제1신호를 발생시키고 입력신호의 위상이 출력신호의 위상에 뒤쳐지는 때 충전펌프가 반대방향으로 콘덴서를 충전시키도록 제2신호를 발생시킴을 특징으로 하는 회로.4. The method of claim 3, wherein the means for generating the control voltage comprises a charge pump having a capacitor that is charged or discharged and is a voltage control voltage across the capacitor, wherein the means for determining the leading and trailing phases of the signal phase comprises: Generate a first signal to charge the capacitor in the first direction when the output pump is out of phase, and cause the charge pump to charge the capacitor in the opposite direction when the phase of the input signal falls behind the phase of the output signal. A circuit characterized by generating two signals. 제4항에 있어서, 신호위상의 앞서고 뒤섬을 결정하기 위한 수단이 입력신호와 출력신호를 수신하며 입력신호의 상승에지와 출력신호의 다음 상승에지 사이의 시간 간격 중에 제1신호를 발생시키고 출력신호의 상승에지와 입력신호의 다음 상승에지 사이의 시간 간격 중에 제2신호를 발생시키는 위상 탐지기를 포함함을 특징으로 하는 회로.5. The apparatus of claim 4, wherein the means for determining the leading and trailing phases of the signal phase receives an input signal and an output signal and generates a first signal during a time interval between the rising edge of the input signal and the next rising edge of the output signal and outputting the output signal. And a phase detector for generating a second signal during a time interval between the rising edge of and the next rising edge of the input signal. 제5항에 있어서, 위상탐지기가 입력신호의 상승에지에 의해 세트되는 제1D타입 플립플롭과 출력신호의 상승에지에 의해 세트되는 제2D타입 플립플롭을 포함하며, 제1논리게이트가 각 플립플롭으로부터의 출력을 수신하고 전술한 제1신호를 제공하도록 열결되고, 제2논리게이트가 각 플립플록으로부터의 출력을 수신하며 전술한 제2신호를 제공하도록 연결됨을 특징으로 하는 회로.6. The apparatus of claim 5, wherein the phase detector comprises a first type flip flop set by the rising edge of the input signal and a second type flip flop set by the rising edge of the output signal, wherein the first logic gate is each flip flop. Circuitry coupled to receive an output from and provide the first signal described above, and wherein a second logic gate is coupled to receive the output from each flip-flop and provide the second signal described above. 제6항에 있어서, 입력신호의 사전결정된 기간의 숫자만큼을 입력신호에 대하여 출력신호가 지연되도록 하기 위한 조화 제어수단(harmonic control means)을 포함함을 특징으로 하는 회로.7. The circuit according to claim 6, comprising harmonic control means for causing the output signal to be delayed with respect to the input signal by a number of predetermined periods of the input signal. 제7항에 있어서, 사전 결정된 기간의 숫자가 1이며, 조화 제어수단이 입력신호와 요구되는 타이밍 관계를 갖는지를 결정하기 위해 출력신호를 모니터하기 위한 수단과 만약 부적합한 파형이 탐지되면 1주기의 지연을 달성시키기 위해 회로의 동작을 바로잡기 위한 수단을 포함함을 특징으로 하는 회로.8. A method according to claim 7, wherein the number of predetermined periods is one, means for monitoring the output signal to determine if the harmonic control means has the required timing relationship with the input signal and a delay of one cycle if an inappropriate waveform is detected. Means for correcting the operation of the circuit to achieve the circuit. 제8항에 있어서, 회로의 동작을 바로잡기 위한 수단이 최소의 지연을 갖는 출력신호를 제공하기 위해 지연회로를 리세트하기 위한 수단을 포함하며, 이에 따라 회로가 입력신호 1주기만큼의 지연을 달성시키기 위해 출력신호의 지연이 증가시키도록 동작함을 특징으로 하는 회로.9. The apparatus of claim 8, wherein the means for correcting the operation of the circuit comprises means for resetting the delay circuit to provide an output signal having a minimum delay, whereby the circuit provides a delay of one cycle of the input signal. Circuitry operative to increase the delay of the output signal to achieve. 제2항에 있어서, 지연회로가 다수의 직렬연결된 인버터와 인버터의 스위칭 속도를 변조시키기 위한 수단을 포함함을 특징으로 하는 회로.3. The circuit of claim 2 wherein the delay circuit comprises a plurality of series connected inverters and means for modulating the switching speeds of the inverters. 제10항에 있어서, 각 인버터가 CMOS트랜지스터 쌍으로 구성되며, 인버터의 스위칭 속도를 변조시키기 위한 수단이 인버터와 전원장치 연결 사이에 연결된 추가 트랜지스터를 포함하고, 제어전압이 추가 트랜지스터에 인가되어 인버터에 공급된 전류를 변조시킴으로써 이들의 속도를 변조시키도록 함을 특징으로 하는 회로.11. The inverter of claim 10, wherein each inverter consists of a pair of CMOS transistors, the means for modulating the switching speed of the inverter including an additional transistor coupled between the inverter and a power supply connection, and a control voltage is applied to the additional transistor to And modulating their speed by modulating the supplied current. 주기적 디지탈 입력신호에 대하여 정확한 지연을 갖는 출력신호를 제공하기 위한 위상고정(phase-locked)회로에 있어서 : 기준 주파수를 갖는 주기적 디지탈 입력신로를 제공하기 위한 수단 ; 상기 입력신호를 수신하고 입력신호에 대하여 지연된 출력신호를 발생시키기 위한 가변 지연수단(variable delay means), 그리고 입력신호와 출력신호를 수신하고 출력신호가 입력신호에 대하여 정해진 위상에서 고정되도록 지연수단을 제어하기 위한 위상고정 제어수단을 포함함을 특징으로 하는 위상고정 회로.A phase-locked circuit for providing an output signal having an accurate delay with respect to a periodic digital input signal, comprising: means for providing a periodic digital input path having a reference frequency; Variable delay means for receiving the input signal and generating an output signal delayed with respect to the input signal, and delay means for receiving the input signal and the output signal and for fixing the output signal in a predetermined phase with respect to the input signal. And a phase locked control means for controlling the phase locked circuit. 제12항에 있어서, 제어수단이 입력신호의 사전 결정된 주기 숫자만큼 출력신호가 지연되도록 하기 위한 수단을 포함함을 특징으로 하는 회로.13. The circuit of claim 12, wherein the control means comprises means for causing the output signal to be delayed by a predetermined period number of the input signal. 제13항에 있어서, 제어수단이 입력신호의 위상을 출력신호의 위상과 비교하여 입력신호의 위상이 출력신호의 위상을 앞서는 때 제1오류 신호를 발생시키도록 하고 입력신호의 위상이 출력신호의 위상을 뒤따르는 때 제2오류신호를 발생시키도록 하기 위해 오류신호에 응답하여 제어신호를 발생시키기 위한 교정수단을 포함함을 특징으로 하는 회로.14. The method of claim 13, wherein the control means compares the phase of the input signal with the phase of the output signal to generate a first error signal when the phase of the input signal precedes the phase of the output signal and the phase of the input signal is dependent upon the output signal. And calibration means for generating a control signal in response to the error signal to cause the second error signal to be generated when following a phase. 제14항에 있어서, 교정수단이 제1오류신호에 응답하여 제1방향으로 충전되고 제2오류신호에 응답하여 제2방향으로 충전되는 콘덴서가 있는 충전펌프를 포함하며, 콘덴서에 걸린 전압이 지연수단을 조정하기 위한 제어신호임을 특징으로 하는 회로.15. The method of claim 14, wherein the correcting means comprises a charge pump with a capacitor charged in the first direction in response to the first error signal and charged in the second direction in response to the second error signal, wherein the voltage across the capacitor is delayed. A control signal for adjusting the means. 제15항에 있어서, 지연수단이 다수의 직렬 연결된 인버터와 인버터의 스위칭 속도를 변화시키어 지연 수단의 지연을 변화시키기 위한 수단을 포함함을 특징으로 하는 회로.16. The circuit of claim 15, wherein the delay means comprises means for varying the switching speed of the plurality of series connected inverters and the inverter to change the delay of the delay means. 제16항에 있어서, 각 인버터가 CMOS트랜지스터 쌍으로 구성되며, 지연을 변화시키 위한 수단이 인버터로의 전류적용을 조정하기 위해 제1전원장치 연결과 인버터 사이에 연결된 다수의 제1전원공급 트랜지스터를 포함하고, 전원공급 트랜지스터가 콘덴서로부터의 제어신호에 의해 구동되어짐을 특징으로 하는 회로.17. The device of claim 16, wherein each inverter is comprised of a pair of CMOS transistors, and wherein the means for varying the delay comprises a plurality of first power supply transistors connected between the first power supply connection and the inverter to coordinate the application of current to the inverter. And the power supply transistor is driven by a control signal from the capacitor. 제17항에 있어서, 지연수단의 지연을 변화시키기 위한 수단이 인버터로의 전류적용을 조정하기 위해 제2전원장치 연결과 인버터 사이에 연결된 다수의 제2전원공급 트랜지스터를 포함함을 특징으로 하는 회로.18. The circuit of claim 17, wherein the means for varying the delay of the delay means comprises a plurality of second power supply transistors connected between the second power supply connection and the inverter for adjusting the application of current to the inverter. . 제18항에 있어서, 제1전원공급 트랜지스터가 제1전도도 타입의 MOS트랜지스터이며 제2전원공급 트랜지스터가 제2전도도 타입의 MOS트랜지스터이고, 이때 제2제어신호를 발생시키기 위한 수단이 제1제어신호 크기의 함수로 제2제어신호의 크기를 조정함을 특징으로 하는 회로.19. The device of claim 18, wherein the first power supply transistor is a MOS transistor of a first conductivity type and the second power supply transistor is a MOS transistor of a second conductivity type, wherein the means for generating a second control signal is a first control signal. And adjusts the magnitude of the second control signal as a function of magnitude. 제19항에 있어서, 제2제어신호를 발생시키기 위한 수단이 : 제어신호에 의해 구동되는 제1제어 MOS 트랜지스터 : 제2제어 MOS트랜지스터 : 제2콘덴서에서 전압이 제2제어신호인 제2제어 MOS트랜지스터의 게이트에 연결된 제2콘덴서 : 제2제어 MOS트랜지스터를 통과하는 전류가 제1제어 트랜지스터를 통과하는 전류에 사전 결정된 관계를 갖도록 하기 위해 제2제어 MOS트랜지스터를 구동시키기 위한 전류제어 수단을 포함함을 특징으로 하는 회로.20. The second control MOS of claim 19, wherein the means for generating the second control signal comprises: a first control MOS transistor driven by the control signal: a second control MOS transistor: a second control MOS, wherein the voltage is a second control signal at the second capacitor; A second capacitor connected to the gate of the transistor, comprising current control means for driving the second controlled MOS transistor to cause the current through the second control MOS transistor to have a predetermined relationship to the current through the first control transistor Circuit characterized in that. 제20항에 있어서 : 입력이 출력에 연결되도록 되어있고, 제1 및 제2제어 트랜지스터가 인버터로 전류를 공급하도록 연결된 CMOS인버터, 그리고 인버터의 출력을 기준전압과 비교하여 인버터의 출력이 기준전압과 같아지는 때까지 제2제어 MOS트랜지스터를 구동시키기 위한 비교수단을 포함함을 특징으로 하는 회로.The output of the inverter according to claim 20, wherein the input is connected to the output, the CMOS inverter connected to supply the current to the inverter, and the output of the inverter is compared with the reference voltage. And comparison means for driving the second controlled MOS transistor until equal. 제21항에 있어서, 기준전압이 인버터의 스위칭 전압과 대략 같음을 특징으로 하는 회로.22. The circuit of claim 21 wherein the reference voltage is approximately equal to the switching voltage of the inverter. 제어된 크기의 지연을 디지탈 입력신호를 제공하기 위한 회로에 있어서 : 주기적 출력신호를 제공하기 위한 기준 주파수 수단 ; 기준 주파수 수단의 출력을 수신하고 제어신호에 의해 결정된 지연을 갖는 출력신호를 제공하기 위한 제1가변 지연회로 ; 기준 주파수 수단의 출력신호 위상을 가변 지연회로의 출력신호 위상과 비교하고 가변 지연회로로 제어신호를 발생시키어 가변 지연회로의 출력신호가 기준 주파수 수단의 출력위상으로 고정되어지도록 하기 위한 위상 고정수단, 그리고 디지탈 입력신호를 수신하고 입력신호에 대하여 지연된 출력신호를 제공하며, 제어신호가 지연의 크기를 조정하기 위이해 제2지연회로에 가해지고, 제어신호에서의 변화에 응답하는 제1지연회로의 지연변동이 제어신호에서의 동변화에 응답하는 제2지연호로의 지연크기 변화와 비례하도록 하기 위한 제2가변 지연회로를 포함함을 특징으로 하는 회로.A circuit for providing a digital input signal with a delay of a controlled magnitude, comprising: a reference frequency means for providing a periodic output signal; A first variable delay circuit for receiving an output of the reference frequency means and providing an output signal having a delay determined by the control signal; Phase fixing means for comparing the output signal phase of the reference frequency means with the output signal phase of the variable delay circuit and generating a control signal with the variable delay circuit so that the output signal of the variable delay circuit is fixed to the output phase of the reference frequency means; And receiving the digital input signal and providing a delayed output signal with respect to the input signal, wherein the control signal is applied to the second delay circuit to adjust the magnitude of the delay and responds to a change in the control signal. And a second variable delay circuit for causing the delay variation to be proportional to the change in the delay size to the second delay call in response to the dynamic change in the control signal. 주기적 기준신호에 대하여 정확히 지연된 신호를 제공하기 위한 위상고정 루프회로에 있어서 : 주기적 기준신호를 제공하기 위한 기준주파수 전원 ; 기준신호를 수신하기 위한 제1입력과 제어신호를 수신하기 위한 제어입력을 갖는 가변지연회로, 기준신호와 같은 주파수를 가지며 기준신호에 대하여 제어신호에 의해 결정된 크기만큼 지연된 주기적 출력신호를 제공하는 지연회로 ; 기준신호와 출력신호 사이의 위상을 비교하고, 제어신호를 지연호로로 제공하여 요구되는 위상관계를 달성하도록 지연의 크기를 변화시키기 위한 제어수단, 기준신호와 출력신호 사이의 위상 오류의 방향을 결정하고 위상오류를 줄이는 방향으로 제어신호를 변화시키기 위한 수단을 포함하는 제어수단을 포함함을 특징으로 하는 위상고정 루프회로.CLAIMS 1. A phase locked loop circuit for providing a signal delayed accurately with respect to a periodic reference signal, comprising: a reference frequency power supply for providing a periodic reference signal; A variable delay circuit having a first input for receiving a reference signal and a control input for receiving a control signal, a delay having a frequency equal to the reference signal and providing a periodic output signal delayed by a magnitude determined by the control signal with respect to the reference signal. Circuit ; Comparing the phase between the reference signal and the output signal, and providing a control signal as a delay signal to determine the direction of the phase error between the reference signal and the output signal, and control means for varying the magnitude of the delay to achieve the required phase relationship. And control means including means for changing the control signal in a direction to reduce phase error. 제24항에 있어서, 제어수단이 초기 위상오류가 알려진 방향이도록 하는 지연을 초래케하는 초기값으로 제어신호를 세트시키기 위한 수단을 포함함을 특징으로 하는 회로.25. The circuit of claim 24, wherein the control means comprises means for setting the control signal to an initial value that results in a delay causing the initial phase error to be in a known direction. 제24항에 있어서, 기준신호의 위상과 그 출력신호의 위상을 비교하고, 제1방향의 위상오류가 탐지된때 제1오류신호를 발생시키며 제2방향의 위상오류가 탐지된 때 제2오류신호를 발생시키기 위한 위상탐지기, 그리고 오류신호를 수신하고 수신된 오류신호에 응답하여 제어신호를 발생시키기 위한 충전펌프를 포함함을 특징으로 하는 회로.25. The method of claim 24, wherein the phase of the reference signal is compared with the phase of the output signal, and a first error signal is generated when a phase error in the first direction is detected and a second error when a phase error in the second direction is detected. A phase detector for generating a signal, and a charge pump for receiving an error signal and generating a control signal in response to the received error signal. 제26항에 있어서 : 위상탐지기가, 기준신호의 상승에지에 의해 클록되는 제1의 타입 플립플롭 ; 출력신호의 상승에지에 의해 클록되는 제2의 D-타입 플립플롭 ; 기준신호의 제1상승에지에 응답하여 플립플롭을 가능하게 하므로써 제1플립플롭이 기준신호의 다음 상승에지에 의하여 클록될 수 있고 제2플립플롭이 출력신호의 다음 상승에너지에 의해 클록될 수 있도록 하기 위한 위상비교 제어수단, 그리고 오류신호를 발생시키기 위해 플립플롭의 출력에 연결되는 논리수단을 포함함을 특징으로 하는 회로.27. The apparatus of claim 26, wherein the phase detector comprises: a first type flip-flop clocked by the rising edge of the reference signal; A second D-type flip-flop clocked by the rising edge of the output signal; Enabling flip-flops in response to the first rising edge of the reference signal so that the first flip-flop can be clocked by the next rising edge of the reference signal and the second flip-flop can be clocked by the next rising energy of the output signal. A phase comparison control means, and logic means connected to the output of the flip-flop to generate an error signal. 제27항에 있어서, 위상비교 제어수단이 기준신호의 상승에지에 의하여 클록되는 제3의 D-타입 플립플롭을 포함하며, 제3의 플립플롭의 출력이 제1 및 제2플립플롭의 가능을 제어함을 특징으로 하는 회로.28. The apparatus of claim 27, wherein the phase comparison control means comprises a third D-type flip-flop clocked by the rising edge of the reference signal, wherein the output of the third flip-flop is enabled for the first and second flip-flops. A circuit characterized by a control box. 제28항에 있어서, 제3플립플롭이 (a) 기준신호의 제1상승에지에 응답하여 제1 및 제2플립플롭을 가능하게하므로써 제1플립플롭이 기준신호의 다음 상승에지에 의해 클록되어지도록 하고, (b) 기준신호의 전술한 다음 상승에지 직후에 발생되는 기준신호의 제3상승에지에 응답하여 제1 및 제2플립플롭을 비가능 조건(non-enabled condition)으로 리세트시키는 출력을 제공하도록 배치되어짐을 특징으로 하는 회로.29. The first flip-flop is clocked by the next rising edge of the reference signal by allowing the third flip-flop to (a) enable the first and second flip flops in response to the first rising edge of the reference signal. (B) an output for resetting the first and second flip-flops to a non-enabled condition in response to a third rising edge of the reference signal generated immediately after the aforementioned next rising edge of the reference signal. Circuitry arranged to provide. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
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