KR100245273B1 - Phase detectin output circuit of pll - Google Patents

Abstract

The output circuit of the phase locked loop is composed of an odd number of inverters connected in series, and receives the first phase detection signal and the second phase detection signal outputted from the phase detection circuit, and adds the first level. A delay circuit 500 for delaying and outputting the first phase detection signal so that the first phase detection signal is changed from the first level to the second level after being delayed for a predetermined time after being changed to the second level )Wow; An inversion circuit (600) for receiving the second phase detection signal and outputting an inverted second phase detection signal; First phase output means 700 for receiving the first phase detection signal delayed by the delay circuit 500 and the second phase detection signal inverted by the inversion circuit 600 and outputting a first phase output signal; ; Second phase output means 800 which receives the first phase detection signal delayed by the delay circuit 500 and the second phase detection signal inverted by the inversion circuit 600 and outputs a second phase output signal. Include. By such a device, a phase output signal discharged to a ground voltage level sharply can be obtained.

Description

Phase Detector Output Circuit of Phase Locked Loop

The present invention relates to a phase locked loop, and more particularly, to a phase detection output circuit in a phase locked loop.

1 is a schematic block diagram of a phase locked loop.

Referring to FIG. 1, the phase synchronization loop has only a basic configuration, and includes a voltage controlled oscillator 10, a phase detector 20, a phase detector output unit 30, and a loop filter 40. The voltage controlled oscillator 10 receives a predetermined signal and outputs an oscillation signal fT. The phase detection unit 20 receives a reference signal fi and the oscillation signal fT to detect phase differences of the signals, and delays the signals by the phase difference according to the detected result to output phase detection signals. do. The phase detection output unit 20 receives the phase detection signals and outputs phase output signals. The loop filter 40 receives the phase output signal and outputs a DC level component except for an AC component.

FIG. 2 is a circuit diagram illustrating a conventional phase detection output unit of the phase locked loop of FIG. 1.

Referring to FIG. 2, the phase detection output unit 30 in the phase synchronization loop includes a first inversion unit 50, a second inversion unit 60, a first phase output unit 70, and a second phase output. It has the structure containing the part 80.

The phase detection output unit 30 receives phase detection signals output from the phase detection unit 20 and transmitted to the first node n1 and the second node n2. The first inverting unit 20 receives the phase detection signal transmitted to the first node n1, inverts it, and transmits the inverted signal to the third node n3. The first inverting portion 50 includes a first inverter 52. The second inverting unit 60 receives the phase detection signal transmitted to the second node n2 and inverts it to transfer it to the fourth node n4. In addition, the second inverting unit 60 includes a second inverter 62.

The first phase output unit 70 receives the inverted signals transmitted to the second node n2 and the third node n3 to output the first phase detection signal DOP1. The first phase output unit 70 includes a third inverter 72, a fourth inverter 74, a fifth inverter 76, a first PMOS transistor MP1, and a first NMOS transistor NM1. At the same time, the second phase output unit 80 receives the inverted signals transmitted to the second node n2 and the third node n3 and outputs the second phase output signal DOA1. The second phase output unit 80 includes a sixth inverter 82, a seventh inverter 84, an eighth inverter 86, a second PMOS transistor MP2, and a second NMOS transistor MN2.

Referring to Fig. 1, the operation of the phase detection output circuit having the above configuration is as follows.

The phase detection output unit 39 includes a first inversion unit 50, a second inversion unit 60, a first phase output unit 70, and a second phase output unit 80. The phase detection signal transmitted to the first node n1 is applied to the first inverting unit 50, and the first inverting unit 50 inverts the signal and transfers the signal to the third node n3. The phase detection signal transmitted to the second node n2 is applied to the second inversion unit 60, and the second inversion unit 60 inverts the signal and transmits the signal to the fourth node n4. The signals transmitted to the third node n3 and the fourth node n4 are simultaneously applied to the first phase output unit 70 and the second phase output unit 80.

In the first phase output unit 70, the phase detection signal of the first node n1 passes through the first inverter 52, the fourth inverter 74, and the fifth inverter 76, thereby delaying the signal. It is applied to the gate of the 1NMOS transistor MN1. The phase detection signal of the second node n2 passes through the second inverter 62 and the third inverter 72 and is delayed and applied to the gate of the first PMOS transistor MP1. The first PMOS transistor MP1 and the first NMOS transistor MN1 are turned on and turned off by the delay signals applied to the gate to output the first phase output signal DOP1.

The second phase output unit 80 has the same configuration as the first phase output unit 70, except that the signal of the second node n2 and the signal of the third node n3 are the first phase output unit ( The second phase output signal DOA1 having a phase opposite to that of the first phase output unit 70 is output, although there is a slight difference in signal delay since it is applied to the input terminal opposite to 70).

An output waveform of the first phase output signal DOP1 of the phase detection output unit 30 is shown in FIG. 4.

As shown in FIG. 4, after the signal of the second node n2 transitions from a low level to a high level, the first phase output signal DOP1 output from the conventional phase detection output unit 30 is high. Transitions slowly from level to low level (ie, slowly discharges from the supply voltage level to the ground voltage level). Since the loop filter 40 of the next stage includes a capacitor component, if the first phase output signal DOP1 transitions from a high level to a low speed at a slow speed, the accurate DC level component cannot be extracted. This is a factor that degrades the performance of the phase detection circuit.

Accordingly, an object of the present invention is to provide a phase detection output unit in which phase output signals are discharged in a short time from a power supply voltage level to a ground voltage level.

1 is a block diagram schematically showing the configuration of a phase locked loop.

2 is a circuit diagram showing a conventional phase detection output of the phase locked loop of FIG.

3 is a circuit diagram showing in detail the phase detection output according to an embodiment of the present invention in the phase synchronization loop of FIG.

4 is an output timing diagram of each node of the phase detection output unit of FIG. 3;

* Explanation of symbols for main parts of the drawings

400: delay unit 500: inverting unit

600: first phase output unit 700: second phase output unit

[Configuration]

According to one aspect of the present invention for achieving the object described above, by receiving the oscillation signal (ft) from the input signal (fi) and the voltage controlled oscillator to detect the phase difference between the two signals, the first and second phase An output circuit 300 of a phase locked loop including a phase detection circuit for outputting a detection signal is comprised of an odd number of inverters connected in series, and accepts the first phase detection signal to generate the second phase detection signal. A delay circuit for delaying and outputting the first phase detection signal so that the first phase detection signal is changed from the first level to the second level after being delayed for a predetermined time after the change from the first level to the second level 500; An inversion circuit 600 which receives the second phase detection signal and outputs an inverted second phase detection signal; First phase output means 700 for receiving the first phase detection signal delayed by the delay circuit 500 and the second phase detection signal inverted by the inversion circuit 600 and outputting a first phase output signal; ; Second phase output means 800 which receives the first phase detection signal delayed by the delay circuit 500 and the second phase detection signal inverted by the inversion circuit 600 and outputs a second phase output signal. Include.

In a preferred embodiment, the first phase output means 700 includes: a first input terminal for receiving a second phase detection signal inverted by the inversion circuit 600; A second input terminal for receiving the first phase detection signal delayed by the delay circuit (500); A fifth inverter (702) for inverting the inverted second phase detection signal input from the first input terminal; A sixth inverter (704) for inverting the delayed first phase detection signal input from the second input terminal; A seventh inverter 706 for inverting the output signal of the sixth inverter 704; A first PMOS transistor MP1 having one current path and controlled by an output signal of the fifth inverter 702; A first NMOS transistor (MN1) having one current path and controlled by an output signal of the seventh inverter (706); Current paths of the first PMOS transistor MP1 and the first MNOS transistor MN1 are sequentially formed in series between a power supply voltage and a ground voltage.

In a preferred embodiment, the second phase output means (800) comprises: a first input terminal for receiving a first phase detection signal delayed by the delay circuit (500); A second input terminal for receiving a second phase detection signal inverted by the inversion circuit (600); An eighth inverter (802) for inverting the delayed first phase detection signal input from the first input terminal; A ninth inverter 804 for inverting the inverted second phase detection signal input from the second input terminal; A tenth inverter 806 for inverting an output signal of the ninth inverter 804; A second PMOS transistor (MP2) having one current path and controlled by an output signal of the eighth inverter (802); A second NMOS transistor (MN2) having one current path and controlled by an output signal of the nineteenth inverter (806); Current paths of the second PMOS transistor MP2 and the second NMOS transistor MN2 are sequentially formed in series between a power supply voltage and a ground voltage.

[Action]

Since the phase output signal is discharged to the ground voltage level for a short time by such a device, a sharper phase output signal is output than before, and the sharp phase output signal is applied to a loop filter in the phase synchronization loop to obtain an accurate DC level component. Can be.

EXAMPLE

Reference will now be made in detail with reference to FIGS. 3 to 4 according to a preferred embodiment of the present invention.

FIG. 3 shows a circuit diagram of the phase detection output unit of the phase-locked loop according to the preferred embodiment of the present invention, and FIG. 4 shows each node output timing diagram of the phase detection output unit 300 shown in FIG. have.

Referring to FIG. 3, the phase detection output unit 300 includes a delay unit 500, an inversion unit 600, a first phase output unit 700, and a second phase output unit 800.

The phase detection output unit 300 receives the phase detection signals output from the phase detection unit 200 through the first node n1 and the second node n2. The delay unit 500 receives the phase detection signal transmitted to the first node n1, delays the signal for a predetermined time, and delivers the signal to the third node n3. The delay unit 500 includes a first inverter 502, a second inverter 504, and a third inverter 506 connected in series from the first node n1 to the third node n3. The inverter 600 receives the phase detection signal transmitted to the second node n2, inverts the signal, and transmits the inverted signal to the fourth node n4. The inverter 600 is the fourth inverter 602. It includes.

The first phase detector 700 receives a delay signal transmitted to the third node n3 and receives an inverted signal transmitted to the fourth node n4 to output the first phase output signal DOP. The first phase output unit 700 includes a fifth inverter 702, a sixth inverter 704, a seventh inverter 706, a first PMOS transistor MP1, and a second NMOS transistor NM1. At the same time, the second phase output unit 800 receives the delay signal transmitted to the third node n3 and the inverted signal transmitted to the fourth node n4 to output the second phase output signal DOA. . The second phase output unit 800 includes an eighth inverter 802, a ninth inverter 804, a tenth inverter 806, a second PMOS transistor MP2, and a second NMOS transistor MN2.

3 to 4, the operation of the phase detection output circuit according to the preferred embodiment of the present invention is described.

The first phase output unit 700 and the second phase output unit 800 have the same configuration, and only the signals applied to the input terminal are changed from each other, so that phase output signals having only opposite phases are generated. Will only be described. As an example, an interval while the phase detection signal transmitted to the second node n2 is at the low level, that is, before the phase detection signal is changed from the low level to the high level. In this section, the low level signal of the second node n2 passes through the fourth inverter 602 of the inverting unit 600 and the fifth inverter 702 of the first phase output unit 700. DPP is applied to the gate of the first PMOS transistor MP1. The first PMOS transistor MP1 is turned on due to the low level delay signal DPP and outputs a first phase output signal DOP that rises to a power supply voltage Vdd level.

In this period, the phase detection signal of the first node n1 is maintained at a high level for a predetermined time while the phase detection signal of the second node n2 is at a low level, and then drops to a low level. In the interval, the first phase detection signal of the first node n1 may include the first inverter 502, the second inverter 504, the third inverter 506 of the delay unit 500, and the first phase output unit. The signal is delayed and applied to the gate of the first NMOS transistor MN1 by passing through the sixth inverter 704 and the seventh inverter 706 of 700. When the high level delay signal DPN is applied to the gate of the first NMOS transistor MN1, the first phase output signal DOP is discharged from the power supply voltage level to the ground voltage level.

Due to the delay unit 500, the first PMOS transistor MP1 and the first NMOS transistor MN1 are turned on at different timings. Therefore, when the first PMOS transistor MP1 is turned on, the first NMOS transistor MN1 is turned off, and when the first PMOS MP1 is turned off, the first NMOS MN1 is turned on. Therefore, while the delay signal DPP is logic " 0 ", the first phase output signal DOP, which is turned on and rises to the power supply voltage Vdd level, is outputted, and the delay signal. While DPN is logic " 1 ", the first NMOS transistor MN1 is turned on to output the first phase output signal DOP discharged from the power supply voltage level to the ground voltage level. As the first NMOS transistor NM1 is turned on and discharged to the ground voltage level, the first phase output signal DOP has a sharper output waveform than in the prior art. However, since the first phase output signal DOP is applied to a loop filter composed of a resistor and a capacitor, the first phase output signal DOP does not immediately fall to ground but falls with a gentle slope due to the capacitor component. .

The second phase output unit 800 has the same configuration as the first phase output unit 800 and the signals of the first node n1 and the second node n2 are applied opposite to the first phase output unit 700. And outputs a second phase output signal DOA having a phase opposite to that of the first phase output unit 700. The first phase output signal DOP and the second phase output signal DOA do not have two signals simultaneously applied to the loop filter 40, but only one signal is selectively applied to the loop filter 40.

The reason why the first PMOS transistor MP1 and the first NMOS transistor MN1 are not turned on at the same time by using the delay unit 500 in the phase detection output unit 300 is that the first PMOS transistor MP1 and the first PMOS transistor MP1 are not turned on. When the 1NMOS transistor MN1 is turned on at the same time, a large amount of current flows out to the ground for a short time, so that a clearer output waveform of the phase output signal can be obtained, whereas a leakage current occurs. There is a slight error in the output waveform of the loop filter 40 which outputs a DC level component. Accordingly, when the first PMOS transistor MP1 and the first NMOS transistor MN1 are turned on at different timings by using the delay unit 500, the first PMOS transistor MP1 and the first NMOS transistor MN1 are turned on. Although the waveform of the phase output signal is less clear than when both are turned on, the error due to leakage current (Leakage Cuerrent) can be reduced, and a sharper output waveform can be obtained than before.

As described above, the phase detection output unit can obtain a sharper phase output signal than before because the current falls to ground for a short time, and the sharp phase output signal is applied to the loop filter to obtain an accurate DC level component. have.

Claims (3)

An output circuit of a phase locked loop including a phase detection circuit which receives an oscillation signal ft from an input signal fi and a voltage controlled oscillator, detects a phase difference between the two signals, and outputs first and second phase detection signals. At 300, comprising: an odd number of inverters connected in series, receiving the first phase detection signal and changing the second phase detection signal from a first level to a second level, and then delaying for a predetermined time period. A delay circuit (500) for delaying and outputting the first phase detection signal so that the first phase detection signal is changed from the first level to the second level; An inversion circuit (600) for receiving the second phase detection signal and outputting an inverted second phase detection signal; First phase output means 700 for receiving the first phase detection signal delayed by the delay circuit 500 and the second phase detection signal inverted by the inversion circuit 600 and outputting a first phase output signal; ; Second phase output means 800 which receives the first phase detection signal delayed by the delay circuit 500 and the second phase detection signal inverted by the inversion circuit 600 and outputs a second phase output signal. And an output circuit of a phase locked loop. 2. The apparatus of claim 1, wherein the first phase output means (700) comprises: a first input terminal for receiving a second phase detection signal inverted by the inversion circuit (600); A second input terminal for receiving the first phase detection signal delayed by the delay circuit (500); A fifth inverter (702) for inverting the inverted second phase detection signal input from the first input terminal; A sixth inverter (704) for generating the delayed first phase detection signal input from the second input terminal; A seventh inverter 706 for inverting the output signal of the sixth inverter 704; A first PMOS transistor MP1 having one current path and controlled by an output signal of the fifth inverter 702; A first NMOS transistor (MN1) having one current path and controlled by an output signal of the seventh inverter (706); And the current passages of the first PMOS transistor MP1 and the first NMOS transistor MN1 are sequentially formed in series between a power supply voltage and a ground voltage. According to claim 1, The second phase output means (800) comprises: a first input terminal for receiving a first phase detection signal delayed by the delay circuit (500); A second input terminal for receiving a second phase detection signal inverted by the inversion circuit (600); An eighth inverter (802) for inverting the delayed first phase detection signal input from the first input terminal; A ninth inverter 804 for generating the inverted second phase detection signal input from the second input terminal; A tenth inverter 806 for inverting an output signal of the ninth inverter 804; A second PMOS transistor (MP2) having one current path and controlled by an output signal of the eighth inverter (802); A second NMOS transistor (MN2) having one current path and controlled by an output signal of the nineteenth inverter (806); And the current paths of the second PMOS transistor (MP2) and the second NMOS transistor (MN2) are sequentially formed in series between a power supply voltage and a ground voltage.

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