KR19980067982A - Phase Detection Output Circuit of Phase Synchronous Loop - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop, and more particularly, to a phase detection output unit in a phase locked loop. The present invention relates to a phase locked loop, which receives a phase detection signal transmitted to a first node, delays the signal, A delay unit for outputting; An inversion unit receiving a phase detection signal transmitted to a second node and inverting the signal to output an inversion signal; A first phase output unit receiving the delay signal and the inverted signal and outputting a first phase output signal; And a second phase output unit configured to receive the delay signal and the inverted signal and output a second phase output signal. By such a device, a phase output signal discharged to a ground voltage level sharply can be obtained.

Description

Phase detection output circuit of phase synchronization loop.

The present invention relates to a phase locked loop, and more particularly, to a phase detection output circuit in a phase locked loop.

1 is a schematic block diagram of a phase locked loop.

Referring to FIG. 1, the phase synchronization loop has only a basic configuration, and includes a voltage controlled oscillator 10, a phase detector 20, a phase detector output unit 30, and a loop filter 40. The voltage controlled oscillator 10 receives a predetermined signal and outputs an oscillation signal f _T. The phase detection unit 20 receives a reference signal fi and the oscillation signal f _T to detect phase differences of the signals, and delays the signals by the phase difference according to the detected result to detect phase detection signals. Is output. The phase detection output unit 20 receives the phase detection signals and outputs phase output signals. The loop filter 40 receives the phase output signal and outputs a DC level component except for an AC component.

Referring to FIG. 1, the phase detection output unit 30 in the phase synchronization loop may include a first inversion unit 50, a second inversion unit 60, a first phase output unit 70, and a second phase output. It has the structure containing the part 80.

The phase detection output unit 30 receives the phase detection signals output from the phase detection unit 20 and transmitted to the first node n1 and the second node n2. The first inverting unit 20 receives the phase detection signal transmitted to the first node n1, inverts it, and transmits the inverted signal to the third node n3. The first inverting unit 50 includes a first inverter 52. The second inverting unit 60 receives the phase detection signal transmitted to the second node n2 and inverts it to be transmitted to the fourth node n4. In addition, the second inverting unit 60 includes a second inverter 62.

The first phase output unit 70 receives the inverted signals transmitted to the second node n2 and the third node n3 and outputs the first phase output signal DOP1. The first phase output unit 70 includes a third inverter 72, a fourth inverter 74, a fifth inverter 76, a first PMOS transistor MP1, and a first NMOS transistor MN1. do. At the same time, the second phase output unit 80 receives the inverted signals transmitted to the second node n2 and the third node n3 and outputs the second phase output signal DOA1. The second phase output unit 80 includes a sixth inverter 82, a seventh inverter 84, an eighth inverter 86, a second PMOS transistor MP2, and a second NMOS transistor MN2. .

Referring to Fig. 1, the operation of the phase detection output circuit having the above configuration is as follows.

The phase detection output unit 30 includes a first inversion unit 50, a second inversion unit 60, a first phase output unit 70, and a second phase output unit 80. The phase detection signal transmitted to the first node n1 is applied to the first inverting unit 50, and the first inverting unit 50 inverts the signal and transfers the signal to the third node n3. The phase detection signal transmitted to the second node n2 is applied to the second inverting unit 60, and the second inverting unit 60 inverts the signal and transfers the signal to the fourth node n4. The signals transmitted to the third node n3 and the fourth node n4 are simultaneously applied to the first phase output unit 70 and the second phase output unit 80.

In the first phase output unit 70, the phase detection signal of the first node n1 passes through the first inverter 52, the fourth inverter 74, and the fifth inverter 76, thereby delaying the signal. 1 is applied to the gate of the NMOS transistor MN1. The phase detection signal of the second node n2 passes through the second inverter 62 and the third inverter 72 so that the signal is delayed and applied to the gate of the first PMOS transistor MP1. The first PMOS transistor MP1 and the first NMOS transistor MN1 are turned on and turned off by delay signals applied to the gate to output the first phase output signal DOP1.

The second phase output unit 80 has the same configuration as the first phase output unit 70, except that the signal of the second node n2 and the signal of the third node n3 are the first phase output unit ( The second phase output signal DOA1 having a phase opposite to that of the first phase output unit 70 is output, although there is a slight difference in signal delay since it is applied to the input terminal opposite to 70).

An output waveform of the first phase output signal DOP1 of the phase detection output unit 30 is shown in FIG. 4.

However, according to the conventional phase detection output unit 30 as described above, the phase output signal is not discharged quickly from the power supply voltage Vdd level to the ground voltage level by the capacitor component in the filter of the phase synchronization loop. This causes a problem that the correct DC level component is not output from the loop filter.

Accordingly, an object of the present invention is to provide a phase detection output unit in which phase output signals are discharged in a short time from a power supply voltage level to a ground voltage level.

1 is a block diagram schematically showing the configuration of a phase locked loop;

2 is a circuit diagram showing a conventional phase detection output of the phase locked loop of FIG.

3 is a circuit diagram showing in detail the phase detection output unit according to the embodiment of the present invention in the phase synchronization loop of FIG.

4 is an output timing diagram of each node of the phase detection output unit of FIG. 3;

* Explanation of symbols on main parts of the drawings

400: delay unit 500: inverting unit

600: first phase output unit 700: second phase output unit

(Configuration)

According to one aspect of the present invention for achieving the above object, a delay means for receiving a phase detection signal transmitted to the first node, delaying the signal to deliver a delay signal to a third node; Inversion means for receiving a phase detection signal transmitted to a second node, inverting the signal, and transferring an inversion signal to a fourth node; First phase output means for receiving the delay signal and the inverted signal and outputting a first phase output signal; And a second phase output means for receiving the delay signal and the inverted signal and outputting a second phase output signal.

In a preferred embodiment of the circuit, the delay means comprises a first inverter having an input terminal connected to the first node, a second inverter having an input terminal connected to the output terminal of the first inverter, and an input terminal connected to the output terminal of the second inverter. And an output terminal connected to the third node.

In a preferred embodiment of this circuit, the inverting means comprises a fourth inverter having an input terminal connected to the second node and an output terminal connected to the fourth node.

In a preferred embodiment of the circuit, the first phase output means includes a fifth inverter having an input terminal connected to a fourth node, a power supply voltage being applied to a source, a gate connected to an output terminal of the fifth inverter, and a drain having a first phase. A first PMOS transistor connected to an output terminal to which an output signal is output, a sixth inverter connected to an input terminal of the third node, a seventh inverter connected to an output terminal of the sixth inverter, and a drain of the first PMOS transistor And a first NMOS transistor connected at a gate thereof to a output terminal of the seventh inverter 406 and having a source grounded.

In a preferred embodiment of the circuit, the second phase output means includes an eighth inverter having an input terminal connected to a third node, a power supply voltage being applied to a source, a gate connected to an output terminal of the eighth inverter, and a drain having a second phase. A second PMOS transistor connected to an output terminal to which an output signal is output, a ninth inverter connected to an input terminal of the fourth node, a tenth inverter connected to an output terminal of the ninth inverter 504, and a drain of the second PMOS transistor; And a second NMOS transistor connected to a drain, a gate connected to an output terminal of the tenth inverter, and a source grounded.

(Action)

Since the phase output signal is discharged to the ground voltage level for a short time by such a device, a sharper phase output signal is output than before, and the sharp phase output signal is applied to a loop filter in the phase synchronization loop to obtain an accurate DC level component. have.

(Example)

Hereinafter, reference will be made in detail with reference to FIGS. 3 to 4 according to a preferred embodiment of the present invention.

3 shows a circuit of a phase detection output 300 according to a preferred embodiment of the present invention in a phase locked loop.

4, each node output timing diagram of the phase detection output unit 300 is shown.

Referring to the phase detection output unit 300 according to the preferred embodiment of the present invention in the phase synchronization loop shown in FIG.

Referring to FIG. 3, the phase detection output unit 300 includes a delay unit 500, an inversion unit 600, a first phase output unit 700, and a second phase output unit 800.

The phase detection output unit 300 receives the phase detection signals output from the phase detection unit 200 through the first node n1 and the second node n2. The delay unit 500 receives the phase detection signal transmitted to the first node n1, delays the signal for a predetermined time, and delivers the signal to the third node n3. The delay unit 500 includes a first inverter 502, a second inverter 504, and a third inverter 506 connected in series from the first node n1 to the third node n3. The inverter 600 receives the phase detection signal transmitted to the second node n2, inverts the signal, and transmits the inverted signal to the fourth node n4. The inverter 600 is the fourth inverter 602. It includes.

The first phase output unit 700 receives the delay signal transmitted to the third node n3 and receives the inverted signal transmitted to the fourth node n4 and outputs the first phase output signal DOP. . The first phase output unit 700 includes a fifth inverter 702, a sixth inverter 704, a seventh inverter 706, a first PMOS transistor MP1, and a second NMOS transistor MN1. do. At the same time, the second phase output unit 800 receives the delay signal transmitted to the third node n3 and the inverted signal transmitted to the fourth node n4 to output the second phase output signal DOA. . The second phase output unit 800 includes an eighth inverter 802, a ninth inverter 804, a tenth inverter 806, a second PMOS transistor MP2, and a second NMOS transistor MN2. do.

3 to 4, the operation of the phase detection output circuit having the configuration as described above is as follows.

Since the first phase output unit 700 and the second phase output unit 800 have the same configuration and only signals applied to the input terminal are changed from each other, phase output signals having only opposite phases are generated. Will only be described. As an example, a section is provided while the phase detection signal transmitted to the second node n2 is at a low level, that is, before the phase detection signal is changed from a low level to a high level. In this section, the low level signal of the second node n2 passes through the fourth inverter 602 of the inverter 600 and the fifth inverter 702 of the first phase output unit 700. DPP is applied to the gate of the first PMOS transistor MP1. The first PMOS transistor MP1 outputs a first phase output signal DOP that is turned on due to the low level delay signal DPP and rises to a power supply voltage Vdd level.

In this period, the phase detection signal of the first node n1 is maintained at a high level for a predetermined time while the phase detection signal of the second node n2 is at a low level, and then drops to a low level. The first phase detection signal of the first node n1 in the section includes the first inverter 502, the second inverter 504, the third inverter 506 of the delay unit 500, and the first phase output unit. The signal is delayed and applied to the gate of the first NMOS transistor MN1 by passing through the sixth inverter 704 and the seventh inverter 706 of 700. When the high level delay signal DPN is applied to the gate of the first NMOS transistor MN1, the first phase output signal DOP is discharged from the power supply voltage level to the ground voltage level.

Due to the delay unit 500, the first PMOS transistor MP1 and the first NMOS transistor MN1 are turned on at different timings. Therefore, when the first PMOS transistor MP1 is turned on, the first NMOS transistor MN1 is turned off, and when the first PMOS MP1 is turned off, the first NMOS MN1 is turned on. . Therefore, while the delay signal DPP is logic ″ 0 ″, the first phase output signal DOP is outputted in which the first PMOS transistor MP1 is turned on and rises to the power supply voltage Vdd level. While the DPN is logic ″ 1 ″, the first NMOS transistor MN1 is turned on to output the first phase output signal DOP discharged from the power supply voltage level to the ground voltage level. As the first NMOS transistor NM1 is turned on and discharged to the ground voltage level, the first phase output signal DOP has a sharper output waveform than before. However, since the first phase output signal DOP is applied to a loop filter composed of a resistor and a capacitor, the first phase output signal DOP does not directly fall to ground but falls with a gentle slope due to the capacitor component. .

The second phase output unit 800 has the same configuration as that of the first phase output unit 800, and the signals of the first node n1 and the second node n2 are applied opposite to the first phase output unit 700. And outputs a second phase output signal DOA having a phase opposite to that of the first phase output unit 700. The first phase output signal DOP and the second phase output signal DOA do not have two signals simultaneously applied to the loop filter 40, but only one signal is selectively applied to the loop filter 40.

The phase detection output unit 300 uses the delay unit 500 to prevent the first PMOS transistor MP1 and the first NMOS transistor MN1 from being turned on at the same time. ) And the first NMOS transistor MN1 are turned on at the same time, a large amount of current is drawn to the ground for a short time to obtain a more distinct output waveform of the phase output signal, while the leakage current (leakeage current) A problem occurs and a slight error occurs in the output waveform of the loop filter 40 outputting the DC level component. Accordingly, when the first PMOS transistor MP1 and the first NMOS transistor MN1 are turned on at different timings using the delay unit 500, the first PMOS transistor MP1 and the first PMOS transistor MP1 are turned on. The waveform of the phase output signal is less pronounced than when both the NMOS transistors MN1 are turned on, but the error caused by leakage current can be reduced, and a slightly sharper output waveform can be obtained.

As described above, the phase detection output unit can obtain a sharper phase output signal than before because the current falls to ground for a short time, and the sharp phase output signal is applied to the loop filter to obtain an accurate DC level component. .

Claims (5)

Delay means (500) receiving a phase detection signal transmitted to a first node, delaying the signal, and transmitting a delay signal to a third node (n3); Inverting means (600) for receiving the phase detection signal transmitted to the second node (n2), inverting the signal, and transferring the inverted signal to the fourth node (n4); First phase output means (700) for receiving the delay signal and the inverted signal and outputting a first phase output signal (DOP); A phase detection output unit including a second phase output means 800 for receiving the delay signal and the inverted signal and outputting a second phase output signal DOA The method of claim 1, The delay means 500, A first inverter (502) having an input terminal connected to the first node (n1); A second inverter 504 whose input terminal is connected to the output terminal of the first inverter 502; And a third inverter (506) having an input terminal connected to an output terminal of the second inverter (504) and an output terminal connected to a third node (n3). The method of claim 1, The inverting means 600, And a fourth inverter (602) having an input terminal coupled to the second node (n2) and an output terminal coupled to a fourth node (n4). The method of claim 1, The first phase output means 700, A fifth inverter 702 whose input is connected to the fourth node n4; A first PMOS transistor MP1 connected to an output terminal of a source voltage Vdd, a gate connected to an output terminal of the fifth inverter 702, and a drain connected to an output terminal of a first phase output signal DOP; ; A sixth inverter 704 whose input is connected to the third node n3; A seventh inverter 706 having an input terminal connected to the output terminal of the sixth inverter 704; And a drain connected to the drain of the first PMOS transistor (MP1), a gate connected to an output terminal of the seventh inverter (706), and a source-grounded first NMOS transistor (MN1). The method of claim 1, The second phase output means 800, An eighth inverter 802 whose input terminal is connected to the third node n3; A second PMOS transistor MP2 connected to an output terminal of a source voltage Vdd, a gate connected to an output terminal of the eighth inverter 802, and a drain connected to an output terminal of a second phase output signal DOA; ; A ninth inverter 804 whose input is connected to the fourth node n4; A tenth inverter 806 having an input terminal connected to an output terminal of the ninth inverter 804; And a drain connected to the drain of the second PMOS transistor (MP2), a gate connected to an output terminal of the tenth inverter (806), and a second NMOS transistor (MN2) having a source grounded.