JPS58107727A - Phase synchronous circuit - Google Patents

Abstract

PURPOSE:To decrease a steady-state phase error, by comparing the phase of inputs to a phase comparator, outputting the result of comparison in rectangular wave and summing the integration of the wave to a VCO control voltage of a phase locked loop. CONSTITUTION:The 1st phase comparator PC1, a low pass filter LPF, a VCO, and a frequency divider DV constitute a conventional phase comparator. Further, the 2nd phase comparator PC2, an integrator INT, and an adder ADD are added, and when an output of the frequency divider DV is fluctuated in a slight phase due to an input signal, ''0'', ''1'' are outputted alternately, a prescribed output is given at the integrator INT, and the output is summed to a normal VCO control voltage, allowing to compensate the steady-state phase delay of the output of VCO.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase-locked path for obtaining an output signal that is phase-locked to an input signal.

For example, as shown in FIG. 1, the phase synchronized circuit inputs a signal applied to an input terminal IN and a signal frequency-divided into IA by an output signal upper frequency divider DV of a voltage controlled oscillator vCO to a phase comparator Pct. In addition, the phase is compared and the comparison output is connected to the resistor R11.
R2: The voltage controlled oscillator vcoo control voltage is passed through a low-pass filter LPF configured with a 2ndenna C1 etc., and the input signal frequency 11 N is output from the output terminal OUT.
It outputs a signal with twice the frequency F2.

The phase output characteristic of the phase comparator PC1 has a sawtooth wave characteristic as shown in FIG. 2, and the voltage controlled oscillator vCO is controlled so that the phase difference becomes zero.

Therefore, when the frequency F10 is input to the input terminal IN, the phase is synchronized with the output terminal 0UTWcR reference signal.
When a signal of frequency F2 with Fl=y= is outputted, the following results.

However, due to aging, temperature changes, etc. of the elements in each part, a certain amount of phase error may occur, which was conventionally dealt with by selecting highly stable elements and configuring the circuit. It was difficult to reduce the error. Therefore, a configuration in which two phase-locked circuits are connected in series has been proposed. However, it has the disadvantage that the circuit configuration is complicated and that it is expensive because twice as many circuit elements are required.

The present invention aims to reduce the steady-state phase error (with a relatively simple configuration). Examples will be described in detail below.

FIG. 3 is a block diagram of an embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same parts, PCB is a phase comparator, I
NT' is an integrator, and ADD is an adder. The output characteristics of the first phase comparator PCI are shown in FIG. 2, while the second phase comparator PC8 has rectangular wave characteristics as shown in FIG. #I4. The integrator INT is for correcting the steady phase error, and integrates the output of the phase comparator PC2, and adds the integrated output to the adder DD, which adds it to the output of the low-pass filter LPF to control the voltage. oscillator vc
The control voltage is set to 0.

FIG. 5 is a more detailed block diagram of the embodiment of the present invention, where FF1 and FFI are phase comparators PC1 and PC! The flip 70, OP1 to 6P3, which constitute the circuit, are operational amplifiers, R3 to R11 are resistors, C2 to C4 are capacitors, and the same reference numerals as in FIG. 13 indicate the same parts.

The inverter INV, the resistor 13, the continuum tc2, and the NAND circuit NAND are for forming a pulse at the first rising edge of the input signal applied to the input terminal IN).
The pulse is applied to the set terminal B of the 70-tube FFI, setting the clip-flop FFI. Qllif of this 7 rig 70 tube FFI! The second terminal is connected to the data terminal DK, the output signal of the frequency divider DV is applied to the clock terminal CK, and the Q terminal is applied to the low-pass filter LPF.

Low pass filter LPF Fi resistance R4~16,
It is composed of a converter tCS and an operational amplifier OP1, and a low-pass filter LP11' C) Output line adder AD
D Ic is added. Also, the output signal of the frequency divider DV is applied to the data terminal of the 7-lip flop FF2, the clock terminal CKK input signal is applied, and the output signal of the Q terminal is applied to the 1-divider h1MT.
1 integrator! The paddle is composed of resistors R7, R8, :2nden f-C4° and operational amplifier 0PAa, 7
When the QJ terminal of the rib crop FFa is "1", the output of the integrator INT decreases. Further, by setting RIO to a sufficiently large value, the influence of the integral output on the loop consisting of PCI is reduced, and the pull-in characteristic of the phase comparator Pct by the loop is not adversely affected.

The adder ADD is composed of resistors R9 to all and an operational amplifier OP3, and includes a low-pass filter LPF and an integrator I.
The outputs from the NT are added to form the control voltage of the voltage controlled oscillator vCO.

Figure tiX6 is an explanatory diagram of the operation. If the input signal (-) in the figure and the output signal of the divider DV are the output signals of the divider DV, then the output signal of the NAND circuit NAND is the leading phase of φ1, and the output signal of the NAND circuit NAND is As shown in (c), it occurs at the rising edge of the input signal and sets the flip-flop FFI. Therefore, when the output signal of the divider DV is 11", the data terminal D
Since the i terminal output of KU"O# is applied, the flip 70 knob FFI is reset. Figure 6 (d) a7
This shows the Q terminal output of the lip flop FFI, which is an output with a pulse width of leading phase difference φ1.

In addition, in the clip 70 tube FF2, since the output signal of the frequency divider DV is "0" at the 9th point in time when the input signal rises, the Q terminal output becomes "O" as shown in FIG. 6(e). Therefore, the voltage controlled oscillator VCO is controlled so that the output of the integrator INT gradually increases and the phase of the output signal of the frequency divider DV is delayed.

In addition, if the output signal of the frequency divider DV is delayed in phase by φ2 with respect to the input signal as shown in #I6 figure (f), the flip 7
0-tube FFI (DQ terminal output changes as shown in Figure 6-), and 7-lip-flop FF2 changes as the output signal of frequency divider DV is "1" at the first rising edge of the input signal. , the Q terminal output becomes "l#" as shown in Figure (b). Therefore, the voltage controlled oscillator is activated so that the output 1 of the integrator INT gradually decreases and the phase of the output signal of the frequency divider DV advances. v
CO is controlled.

The phase comparator PC2 determines whether the phase of the output signal of the divider DV is delayed or advanced with respect to the input signal.
When the phases match, "L" and "O" are output alternately according to the slight phase fluctuation of the output signal of the divider DV, and the output line of the integrator INT becomes constant, The voltage controlled oscillator VCO performs an oscillation operation in synchronization with the input signal phase.

As explained above, the present invention line, the first one-phase comparator P
CI, low pass filter LPF, voltage controlled oscillator v
A loop consisting of a second phase comparator PC2 and an integrator INT is added to a loop consisting of CO and a frequency divider DV, and the second phase comparator PC2 has a phase comparison output characteristic of a rectangular wave characteristic. If the steady phase error shows an advanced phase, the output of the second phase comparator PC2 is integrated by the integrator INT and added to the output of the low-pass filter LPF, and the output of the voltage controlled oscillator vCO is If the output phase is controlled to be delayed and the steady phase error shows a delayed phase, the output phase of the voltage controlled oscillator vCO is controlled to be advanced, so the steady phase error can be significantly reduced. Become. Note that, of course, if the input signal frequency and the output signal frequency are made equal, the frequency divider DV can be omitted; in that case, the first and second phase comparators PCI and PO2 and voltage controlled oscillator vC
Compare the phase with the output signal of O.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional phase synchronization circuit, Fig. 2 is a phase comparison output characteristic curve of the phase comparator PC1, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 is a tlE2o Phase comparator pcgo phase comparison output characteristic curve diagram, Figure 5 line Block diagram of a more detailed embodiment of the present invention, fI
The Xe diagram is an explanatory diagram of the operation of the Rattan diagram. pci and pcg are first and second phase comparators, LPF is a low-pass filter, INT is an integrator, ADD is an adder,
vCO is a voltage controlled oscillator, and Dv is a divider. Patent Applicant: Fujitsu Limited (1 person) Representative Patent Attorney: Hisa Gobe Tamamushi (3 persons) Figure i Figure 2 Phase difference Figure 3 Figure 4 Phase difference

Claims (1)

[Claims] The first phase comparator compares the input signal with the output signal of the voltage controlled oscillator or the output signal frequency-divided by the frequency divider, and the comparison output is passed through a low-pass filter to control the voltage controlled oscillator. In a phase-locked circuit that outputs a voltage, a phase comparison is performed between the input signal and the output signal, and a second phase comparator whose phase comparison output characteristic is a rectangular wave characteristic; A phase synchronized circuit comprising: an integrator that integrates an output; and an adder that adds the output of the integrator and the output of the low-pass filter to obtain a control voltage for the voltage controlled oscillator.