JP2002344311A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a PLL circuit capable of stably operating with sappressing the steady-state phase error and the jitter to the minimum. SOLUTION: An integration item of a phase comparison output is obtained by a complete integrator 2 and limited by a limiter 4. A proportional item of the phase comparison output is obtained by an incomplete integrator 3, and added to the output of the limiter 4 by an adder 5 to provide an added output as a suppression voltage for a VCO 6. This lessens the steady-state phase error and minimizes the output jitter quantity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit,
In particular, the present invention relates to a PLL circuit which detects a phase difference between an output of a voltage controlled oscillator (VCO) and an external signal and controls the VCO according to the phase difference.

[0002]

2. Description of the Related Art A PLL (Phase Locked Loop) circuit is
A phase difference between an input clock as an input signal and a loop clock as an oscillation output of the VCO is generated by a phase comparator, and the phase comparison result signal is passed through a low-pass filter to remove a phase comparison frequency component. In general, the gain is increased by using an operational amplifier to control the VCO as a control voltage.

[0003]

SUMMARY OF THE INVENTION Such a general PL
In the case of the L-circuit method, it is necessary to operate the operational amplifier as a complete integrator in order to minimize the steady-state phase error. In order to reduce the amount of jitter, it is necessary to make the time constant of this perfect integrator a relatively large value.
If this time constant is increased, the lock range and capture range of the PLL circuit become very narrow, causing problems such as unstable circuit operation, loss of lock, and the inability to pull in the loop at all. .

An object of the present invention is to provide a PLL circuit capable of performing a stable operation by minimizing a steady phase error and minimizing a jitter amount.

[0005]

According to the present invention, there is provided a PLL circuit which detects a phase difference between an output of a voltage controlled oscillator and an external signal and controls the voltage controlled oscillator according to the phase difference. Thus, a PLL circuit is obtained in which an addition signal of an output of the integral term of the phase difference through a limiter and a proportional term of the phase difference is used as a control voltage of the voltage controlled oscillator.

According to the present invention, a voltage controlled oscillator, a phase comparator for detecting a phase difference between the oscillation output and an external signal, a complete integrator for generating an integral term of the phase comparison output, A limiter that limits an integral term, an incomplete integrator that generates a proportional term of the phase comparison output, and an adder that adds the limiter output and the proportional term to generate a control voltage of the voltage-controlled oscillator. P characterized by the following:
An LL circuit is obtained.

The operation of the present invention will be described. In the PLL circuit of the present invention, a perfect integrator having a large time constant is used to prevent the VCO clock (output clock) from immediately following the disturbance of the input clock, and the jitter suppressing effect is expected. In this case, the time constant of the complete integrator becomes large and the pull-in becomes poor. Therefore, the output voltage of the complete integrator is limited by a limiter circuit to limit the output voltage to a certain voltage range. And a signal proportional to the phase difference is added, and the added output is used as a VCO control voltage. As a result, a stable PLL circuit with a reduced steady-state phase error and a minimum output jitter amount can be obtained.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. An external input clock is one input of a phase comparator 1, and the other input receives an oscillation clock of the VCO 6 by a frequency divider 7 by 1 / N. A divided clock is supplied. The phase comparison output of the phase comparator 1 is input to a perfect integrator 2 that generates an integral term, and is also input to an incomplete integrator 3 that generates a proportional term. The integral term which is the output of the complete integrator 2 is input to the limiter 4 and subjected to limit processing, and becomes one input of the adder 5. Incomplete integrator 3
Is the other input of the adder 5. The added output of the adder 5 is used as a control voltage of the VCO 6.

FIG. 2 is a diagram showing a phase difference (θ) versus frequency (f) characteristic of each part in the PLL circuit of FIG. The characteristic shown at the left end of FIG. 2 is an output characteristic of the integral term output from the perfect integrator 2 through the limiter 4, and the gain of the perfect integrator 2 is logically infinite. Is controlled so that the phase difference at “1” becomes “0”. Therefore, the vertical axis (phase difference θ) of the characteristics in the figure is fixed to “0”. Thereafter, by passing through the limiter 4, the predetermined voltage range VL within the range of Vcc (of the control voltage of the VCO 6) is limited, and as a result, the integral term of the characteristic shown at the left end of FIG. 2 is obtained. Become.

The center characteristic in FIG. 2 shows the output characteristic of the comparison term of the incomplete integrator 3, and shows a linear characteristic in the range of Vcc.

Since the signal components having these two characteristics are added in the adder 5, the characteristics of the added output are as shown in the right end of FIG. That is, the range in which the limiter 4 operates (V
In L), even if the proportional term is controlled to output the phase difference θ, since the integral term side is strong (priority is given), the phase difference θ is fixed to “0” output as this integral term. become. In the range where the limiter is not effective, the characteristic of the proportional term appears, so that the phase difference θ appears, and the characteristic at the right end in FIG. 2 is obtained. VA indicates the range of the integral term, and VB indicates the range of the proportional term.

When only the proportional term of the phase comparison output of the phase comparator 1 in FIG. 1 is used for the CVO control voltage, the amount of jitter can be minimized, but as shown in the central characteristic of FIG. Will occur. On the other hand, when only the integral term is used, the amount of jitter increases, but as shown in the characteristic at the left end of FIG.
The phase difference can be eliminated.

Therefore, as in the configuration of the present invention, by using a so-called double loop configuration in which the integral term (limiter is set) and the proportional term are added, the phase difference θ is reduced within the range of the limiter. It can be fixed to 0 "to minimize the steady-state phase error, and within the range where the proportional term is effective,
Since the amount of jitter is small and pull-in by the phase difference is possible, the capture range and the lock range are widened.

FIG. 3 is a circuit diagram showing an example of the complete integrator 2 in FIG.
And a well-known circuit configuration including resistors 23 to 28 can be used. In FIG. 3, Vc is the power supply voltage (+5
V). FIG. 4 is a circuit diagram showing an example of the incomplete integrator 3 in FIG.
And a passive element circuit comprising: FIG. 5 is a circuit diagram showing an example of the limiter 4 of FIG. 1 and includes diodes 41 to 44 and resistors 45 and 46. It is to be noted that these circuit configurations are merely examples, and it is needless to say that various changes can be made.

[0015]

As described above, according to the present invention, it is possible to obtain a stable PLL circuit which eliminates a steady phase error and has a small output jitter amount by an extremely simple circuit configuration.

In particular, SDH (Synchronous Digital Hier
In a transport apparatus such as an archy), a configuration is used in which a reference clock in the apparatus is supplied from a panel on which a PLL circuit is mounted in each of a transmission unit and a reception unit.
It is required to eliminate the phase difference between the input and output generated in the circuit and minimize the amount of phase fluctuation between the transmitter and the receiver in the device. Accordingly, it is necessary to increase the capacity of the bit buffer used for the purpose of absorbing the phase difference and suppressing the jitter. However, the use of the PLL circuit according to the present invention minimizes the steady-state phase error and the jitter. There is also an effect that the capacity of the bit buffer can be reduced.

As a result, with respect to the disturbance of the input clock, V
The CO clock (output clock) does not immediately follow, and the jitter of the main signal output of the SDH can be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating characteristics of an example of the present invention.

FIG. 3 is a circuit diagram illustrating an example of the complete integrator of FIG. 1;

FIG. 4 is a circuit diagram illustrating an example of the incomplete integrator of FIG. 1;

FIG. 5 is a circuit diagram showing an example of the limiter of FIG. 1;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 phase comparator 2 complete integrator 3 incomplete integrator 4 limiter 5 adder 6 VCO (voltage controlled oscillator) 7 frequency divider

Claims (5)

[Claims] 1. A PLL circuit for detecting a phase difference between an output of a voltage controlled oscillator and an external signal and controlling the voltage controlled oscillator in accordance with the phase difference. A PLL circuit, wherein an addition signal of an output having passed through a limiter and a proportional term of the phase difference is used as a control voltage of the voltage controlled oscillator. 2. The PLL circuit according to claim 1, further comprising a complete integrator for generating said integral term. 3. The PLL circuit according to claim 1, further comprising an incomplete integrator for generating the proportional term. 4. A voltage controlled oscillator, a phase comparator for detecting a phase difference between the oscillation output and an external signal, a complete integrator for generating an integral term of the phase comparison output, and a limiter for limiting the integral term And an incomplete integrator for generating a proportional term of the phase comparison output; and an adder for adding the limiter output and the proportional term to obtain a control voltage of the voltage controlled oscillator. circuit. 5. The PL according to claim 1, wherein the limiter limits the integral term in a predetermined range within a range from a maximum value to a minimum value of the control voltage.
L circuit.