JPH07288468A - Feedforward control type phase locked loop circuit - Google Patents

Abstract

PURPOSE:To obtain an output signal that has the frequency synchronous with that of an input signal by providing a voltage control multivibrator oscillator, a frequency comparator and a loop filter. CONSTITUTION:An input pulse is inputted to a phase synchronizing pulse generator 35, and a phase synchronizing pulse of a prescribed width is generated at the rise/fall time point of the input pulse. The phase synchrionizing pulse is inputted to a voltage control oscillator VCM 31 and oscillated there. Thus the output signal of the VCM 31 has the phase synchronization with the input pulse in a remaining time base error 0. Then a stabilizing circuit 37 limits the control voltage change range that is outputted from a frequency comparator 27 and inputted to the VCM 31 via a loop filter 29 to a proper level of range. Thus the circuit 37 limits the oscillation frequency range of the VCM 31 and stabilizes the VCM 31. As a result, the proper phase synchronization is attained even with use of a multivibrator as a voltage control oscillator. Thus it is not required to heighten the oscillator frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a feedforward control type phase locked loop circuit, and more particularly, it uses a multivibrator oscillator as a voltage controlled oscillator, and substantially eliminates the residual time time axis error without using a high frequency oscillator. It relates to a technology that enables highly accurate phase synchronization with zero.

[0002]

2. Description of the Related Art FIG. 12 shows a basic structure of a general feedback control type phase locked loop which has been conventionally used. The circuit shown in the figure includes a phase comparator 1, a loop filter 3, a voltage controlled oscillator (VCO) 5, and a frequency divider 7. In order to synchronize the output signal of the VCO 5 with the phase of the input pulse, the oscillation output of the VCO 5 is first divided by the frequency divider 7 so that the frequency corresponds to the frequency of the input pulse. Next, the phase comparator 1 compares the phases of the input pulse and the frequency-divided signal from the frequency divider 7, generates a voltage corresponding to the phase difference between the two, and inputs the voltage to the loop filter 3. The loop filter 3 usually has a low-pass filter action and an amplifying action, removes unnecessary high-frequency components of the error signal input from the phase comparator 1, and the phase-locked loop circuit has desired synchronization characteristics and response characteristics. The error signal is processed and given to the VCO 5. As a result, the VCO 5 oscillates a signal phase-locked with the input pulse.

However, in such a feedback control type phase locked loop circuit, the loop filter, which is a low pass filter, determines the synchronization characteristics and the response characteristics.
The response speed of the phase locked loop becomes slow.

In contrast to such a feedback control type phase synchronization circuit, a feedforward control type digital phase synchronization circuit is used to increase the response speed. FIG. 13 shows an example of such a feedforward control type phase locked loop circuit. The circuit shown in the figure includes an oscillator 9 that oscillates a signal that is asynchronous with an input pulse, and two cascaded D-type flip-flops (D-FF1 and D-FF).
2) 11, 13, NAND gate 15, and frequency divider 1
Equipped with 7. The input pulse is applied to the data input of the first D-type flip-flop 11, and the output of the flip-flop 11 is supplied to the data input of the second D-type flip-flop 13. The outputs of the first and second D-type flip-flops 11 and 13 are supplied to the first and second inputs of the NAND gate 15, respectively. NA
The output of the ND gate 15 is supplied to the reset input of the frequency divider 17. Further, the output of the oscillator 9 is the first and second
It is supplied to the clock inputs of the D-type flip-flops 11 and 13 and the input of the frequency divider 17.

FIG. 14 shows the signal waveform of each part of the phase locked loop circuit of FIG. The operation of the phase locked loop circuit of FIG. 13 will be described with reference to FIG. Note that, in FIG. 14, each of the signal waveforms (a) to (f) shows a signal waveform at the point described by the same reference numeral in the circuit of FIG. 13.

Assume that the oscillator 9 oscillates the asynchronous oscillator output signal shown in FIG. 14A, and the signal shown in FIG. 14B is input as an input pulse. This input pulse becomes a signal which rises by the first D-type flip-flop 11 at the next rise time of the output waveform of the oscillator 9 as shown in FIG. Also, the second D
As shown in (d), the output of the type flip-flop 13 becomes a signal that falls at the next rising edge of the output signal of the oscillator 9. The NAND gate 15 outputs the output (c) of the first D-type flip-flop 11 and the second D-type flip-flop 11 as described above.
The output (d) of the flip-flop 13 is ANDed and the inverted waveform is obtained.
Shown in. The output signal of the NAND gate 15 becomes the reset signal of the frequency divider 17, and the frequency divider 17 is reset at the falling edge of the reset signal. From this reset time, the frequency divider 17 outputs the output signal of the oscillator 9. Start dividing. Therefore, the output signal (f) of the frequency divider 17 is a signal that is phase-locked with the input pulse. 13 and 14, the frequency division ratio N of the frequency divider 17 is 4. Further, in FIG. 14, the shaded area is an area where the polarity is uncertain.

Further, in FIG. 14, the oscillator output waveform (a) is shown with a duty cycle of 50%, and t0 shows the half cycle time of this oscillator output signal. Further, Δt is the time from the rise of the input pulse to the rise of the oscillator output signal, and corresponds to the time delay of the phase locked loop. Since the input pulse and the output of the oscillator 9 are asynchronous with respect to this time Δt, the maximum value thereof is one cycle of the oscillator output signal, that is, 2t0.
0 is an uncontrollable residual phase error.

[0008]

In the phase locked loop circuit as shown in FIG. 14, the residual phase error is one cycle of the oscillation signal of the maximum oscillator 9 as described above. Therefore, it is necessary to increase the oscillation frequency of the oscillator in order to reduce the residual phase error and perform highly accurate phase synchronization. For example, in order to reduce the residual phase error by half, it is necessary to double the oscillation frequency of the oscillator 9.

However, if the frequency of the oscillator is too high, the hardware constituting the oscillator becomes expensive, the power consumption increases, and the amount of heat generated by the oscillator and the power supply for supplying power to the oscillator increases. Occurs. Further, if the oscillation frequency becomes high, the generation of interfering radio waves to the outside of the device increases, or the integrated circuit (IC) that constitutes the oscillator may not be economically available.

Further, in the phase locked loop circuit of FIG. 13, since the input pulse is latched at the output of the oscillator which is asynchronous with the input pulse or at the rising or falling edge of the pulse instead of the output pulse, the phase locking circuit is used. Even if the oscillation frequency of is increased, some phase error will always remain.

Incidentally, in the circuit shown in FIG. 13, in order to further reduce the residual phase error of the output signal, that is, the residual time axis error and perform the phase synchronization with high accuracy, the circuit shown in FIG. 15 is further added. Can be used. The circuit of FIG. 15 includes a delay circuit 21 that delays the output of the reference oscillator by 1/4 cycle and a delay circuit 2 that delays the output by 2/4 cycle.
A delay circuit 25 for delaying by 3, 3/4 cycles and an output of each of these delay circuits 21, 23, 25 and an output of a reference oscillator are accepted, and one of these signals is switched according to a switching control signal. The output switching circuit 19 is included. The switching control signal detects a phase difference between the reference oscillator output and the input signal to be synchronized with a detector (not shown), and selects and outputs any one of the four inputs of the switching circuit 19 according to the phase difference. It is what makes me.

However, using the circuit of FIG. 15 further complicates the hardware configuration of the apparatus, and even if such a circuit is used, the residual time axis error cannot be made zero.

Therefore, it is an object of the present invention to provide a phase locked loop circuit in which the residual time base error is substantially zero without using an oscillator that generates a high frequency signal.

Another object of the present invention is to realize the above-described phase locked loop circuit having substantially zero residual time axis error with an extremely simple circuit structure and low cost.

[0015]

To achieve the above object, according to a first aspect of the present invention, a voltage controlled multivibrator oscillator whose oscillation frequency changes according to a control voltage is used, and the output of the oscillator is used. The frequency comparator generates a signal corresponding to the frequency difference between the signal or the frequency-divided signal of the output signal and the input signal, and outputs the signal output from the frequency comparator as a control voltage via a loop filter. Supply to voltage controlled multivibrator oscillator. A phase control circuit that directly regulates the phase of the oscillation signal of the voltage controlled multivibrator oscillator by the input signal is used.

The voltage controlled multivibrator oscillator has a collector and a base substantially cross-coupled to each other,
The astable multivibrator oscillator can be provided with a pair of transistors in which a capacitor is connected between the emitters, and the phase control circuit uses, for example, a switching transistor, and is externally supplied by a phase synchronization pulse generated from the input signal. Directly regulate the charge or discharge cycle of the capacity.

Further, it is advantageous to provide a frequency stabilizing circuit for limiting the change range of the control voltage output from the frequency comparator and applied to the voltage controlled multivibrator oscillator.

According to the second aspect of the present invention, a voltage controlled multivibrator oscillator whose oscillation frequency changes according to a control voltage is used, and the output signal of the voltage controlled multivibrator oscillator or the output signal is divided. A frequency comparator produces a signal responsive to the frequency difference between the circulated signal and the reference frequency signal. The signal output from the frequency comparator is supplied to the voltage controlled multivibrator oscillator via a loop filter. The phase control circuit directly regulates the phase of the oscillation signal of the voltage controlled multivibrator oscillator by the phase control input signal.

In this case, like the circuit of the first aspect, the voltage-controlled multivibrator oscillator has a collector and a base that are substantially cross-coupled to each other and a pair of transistors having a capacitor connected between the emitters. The phase control circuit may be a stable multivibrator oscillator, and the phase control circuit may be configured to directly regulate the charge or discharge cycle of the capacitance from the outside by a phase synchronization pulse generated from the phase control input signal.

Further, it is advantageous to provide a frequency stabilizing circuit for limiting the change range of the control voltage output from the frequency comparator and applied to the voltage controlled multivibrator oscillator.

Further, according to the third aspect of the present invention, an astable multivibrator oscillator having a capacitor for determining an oscillation frequency is used, and the astable multi-vibrator is directly supplied from the outside by a phase synchronization pulse generated from an input signal by a phase control circuit. The phase of the oscillation signal of the astable multivibrator oscillator can be synchronized with the phase of the input signal by regulating the charge or discharge cycle of the capacitance of the multivibrator oscillator.

[0022]

In the phase locked loop circuit according to the first aspect of the present invention, the feedback type frequency locked loop circuit is constituted by the circuit including the voltage controlled multivibrator oscillator, the frequency comparator and the loop filter, and the output signal in which at least the frequency is synchronized with the input signal. Is obtained. In this case, the phase control circuit further directly regulates the phase of the oscillation signal of the voltage controlled multivibrator oscillator by the input signal.
Specifically, the voltage controlled multivibrator oscillator is an astable multivibrator having a pair of transistors and a capacitance that determines the oscillation frequency, and the phase control circuit directly externally uses a phase synchronization pulse generated from the input signal. Regulate the charge or discharge cycle of the capacity.

Therefore, the oscillating frequency of the oscillator is controlled by feedback control to be the same as the frequency of the input signal, while the oscillating phase controls the on or off operation of each transistor of the voltage controlled multivibrator oscillator by directly raising or rising the input signal. It is controlled to be synchronized with the input signal by controlling to start from the falling edge. Therefore, the phase of the output signal of the voltage controlled multivibrator oscillator is directly regulated by the input pulse, the phase control is performed extremely quickly, and the residual time axis error does not theoretically occur. Further, unlike the conventional case, it is not necessary to raise the oscillation frequency of the oscillator more than necessary in order to reduce the residual time axis error. Therefore, the signal compared with the input signal in the frequency comparator may be the output of the oscillator as it is, and it is not always necessary to divide the output signal of the oscillator and supply it to the frequency comparator.

Further, the variation range of the oscillation frequency of the voltage controlled multivibrator oscillator is reduced by limiting the variation range of the control voltage output from the frequency comparator and applied to the voltage controlled multivibrator oscillator by the frequency stabilizing circuit. Therefore, the phase regulation operation by the phase synchronization circuit can be made more accurate.

In the second aspect of the present invention, the voltage controlled multivibrator oscillator is frequency-controlled based on the reference frequency signal. The phase of the oscillation signal of the voltage controlled multivibrator oscillator whose frequency is controlled by the reference frequency signal is regulated by the phase control input signal different from the reference frequency signal. This makes it possible to obtain a signal whose frequency is synchronized with the reference frequency signal and whose phase is synchronized with the phase control input signal.

In this case as well, the voltage controlled multivibrator oscillator can be an astable multivibrator having a pair of transistors and a capacitance that determines the oscillation frequency, and the phase control circuit is generated from the phase control input signal. The phase synchronization can be achieved by directly controlling the charge or discharge cycle of the capacitance from the outside by the phase synchronization pulse.

Further, by using a frequency stabilizing circuit for limiting the variation range of the control voltage output from the frequency comparator and applied to the voltage controlled multivibrator oscillator, the variation range of the oscillation frequency of the voltage controlled multivibrator oscillator is controlled. It is possible to reduce the size and perform accurate phase synchronization.

Furthermore, in the phase locked loop circuit according to the third aspect of the present invention, a signal of a certain oscillation frequency is output by an astable multivibrator oscillator having a capacitance that determines the oscillation frequency, and such an astable multivibrator is provided. By regulating the phase of the oscillation signal of the oscillator by the phase control circuit, it becomes possible to obtain at least the oscillation signal whose phase is regulated by the input signal, that is, whose phase is synchronized with the phase of the input signal, with a simple circuit.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a phase locked loop circuit according to an embodiment of the present invention. The circuit shown in FIG.
A feedback type frequency synchronizing circuit including a loop filter 29, a voltage controlled oscillator 31, and a frequency divider 33 is included. The loop filter 29 and the frequency divider 33 are respectively
It may be the same as the loop filter 3 and the frequency divider 7 of the phase locked loop circuit of FIG. The voltage controlled oscillator 31 shown in FIG.
Although it is similar to the voltage-controlled oscillator 5 of FIG. 11, the circuit of FIG. 1 uses a voltage-controlled multivibrator in particular.

The phase synchronization circuit of FIG. 1 further receives an input pulse, generates a pulse for phase synchronization, and inputs it to a voltage controlled oscillator (VCM) 31.
And a stabilizing circuit 37 connected to the circuit between the frequency comparator 27 and the VCM 31.

In the phase locked loop circuit of FIG. 1, the frequency comparator 27, the loop filter 29, the VCM 31, the frequency divider 3 are included.
The feedback type frequency synchronization circuit constituted by 3 generates an output signal frequency-synchronized with the input pulse. Further, in the present invention, the input pulse is the phase-locked pulse generator 3
5, the phase synchronization pulse generator 35 generates a phase synchronization pulse having a predetermined pulse width from the rising or falling time of the input pulse. This phase synchronization pulse is applied to the VCM 31 and causes the VCM 31 to oscillate in synchronization with the phase synchronization pulse. By this, VCM
The output signal of 31 is phase-synchronized with the input pulse with zero residual time axis error. Further, the stabilizing circuit 37 limits the change range of the control voltage output from the frequency comparator 27 and input to the VCM 31 via the loop filter 29 to an appropriate value to limit the oscillation frequency range of the VCM 31 as described later in detail. Limit and stabilize. This makes it possible to perform proper phase synchronization even when a multivibrator is used as the voltage controlled oscillator.

When a direct phase comparison between the output of the oscillator (VCM31) and the input signal is performed without passing through a frequency divider such as the frequency divider 33, the phases of both are synchronized. Furthermore, phase synchronization cannot be applied externally. Therefore, a frequency comparator is needed instead of a phase comparator.

Even though the frequency divider is used, a frequency comparator is basically required, but it is not a direct comparison of the phases of both signals. Therefore, even if a phase comparator is used as a frequency comparator, it is practical. The phase comparator is often used as the frequency comparator without any problem.

Next, the detailed configuration of the VCM 31 and the like used in the circuit of FIG. 1 will be described with reference to FIG.
2A shows a basic circuit of a general emitter-coupled multivibrator in FIG. 2A, and FIG. 2B shows an example of the multivibrator circuit used in the phase locked loop according to the present invention.

The multivibrator circuit shown in FIG. 2A has a pair of switching transistors Q1 and Q2 whose bases and collectors are cross-coupled to each other, collectors of these transistors Q1 and Q2, and a power source V.
load resistors R1 and R2 connected between cc and
It includes a capacitor C coupled between the emitters of the transistors Q1 and Q2, and variable current sources I1 and I2 connected between the emitters of the transistors Q1 and Q2 and the ground, respectively. Variable current sources I1 and I
In the figure, the current flowing through these current sources is I1.
And I2.

As is well known, such an emitter-coupled multivibrator circuit has transistors Q1 and Q.
Oscillation occurs due to cross-coupling between the two collectors and bases, and the oscillation frequency is determined by the capacitance of the capacitor C and the charging / discharging currents I1 and I2 to the capacitor C. Since the currents I1 and I2 are determined by the control voltage, the oscillation frequency of this multivibrator circuit can be adjusted by the control voltage.

FIG. 2B shows the basic configuration of the VCM 31 used in the phase locked loop circuit of the present invention. In this circuit, a switching transistor Q3 and a current limiting resistor R3 are further connected to the multivibrator circuit shown in FIG. 2 (a). Transistor Q3
Is connected to the power supply Vcc, and the emitter is connected to the emitter of the transistor Q2, that is, one terminal of the capacitor C. The base of the transistor Q3 is connected to the phase-locked pulse generator 35 via the resistor R3.
The phase-locked pulse generated by is applied. The other parts are the same as those in FIG.

In the circuit of FIG. 2B, the circuit excluding the transistor Q3 and the resistor R3 is the same as that of FIG.
The oscillation operation similar to that of the multivibrator circuit of (a) is performed, and the oscillation output, that is, the VCM output is taken out from the collector of the transistor Q1 or Q2. When performing such an oscillating operation, the phase-locked pulse generator 3
When, for example, a positive phase synchronization pulse is applied from 5 to the base of the transistor Q3 via the resistor R3, the phase synchronization pulse is forcibly applied to one end of the capacitor C that determines the oscillation cycle of the multivibrator. . As a result, each transistor Q1, Q2 of the multivibrator
The ON / OFF operation of can be regulated by the phase synchronization pulse. As will be described later in detail, since the phase synchronization pulse is phase-synchronized with the input pulse in a predetermined phase relationship, the output of this multivibrator, that is, VC
The M output will be phase locked to the input pulse.

As a result, the phase locked loop circuit according to the present invention can be phase-locked with the input pulse without residual time axis error. Moreover, in order to reduce the residual time axis error as in the conventional circuit, the frequency of the oscillator is reduced. Does not have to be high.

FIG. 3 shows an example in which a circuit similar to that shown in FIG. 2B is constructed using an integrated circuit (IC).
The circuit of FIG. 3 is an MC1658 manufactured by Motorola Inc. as an IC.
Type integrated circuit for voltage controlled multivibrator. Pin 1 (V _CC1 ) and pin 5 (V _CC2 ) of this integrated circuit are both connected to a predetermined power supply voltage Vcc, and pin 8 is connected to the ground. A capacitance C for determining the oscillation frequency is connected between the 11th pin and the 14th pin, and the 14th pin is further connected to the emitter of the switching transistor Q3. The collector of the transistor Q3 is connected to the power supply Vcc, and the base is connected to the phase synchronization pulse input via the resistor R3. Pin 2 ( _VCX ) is the loop filter 2 in the circuit of FIG.
It is connected to the output of 9 and a control voltage for changing the oscillation frequency is applied. Pins 12 and 13 are a bias filter terminal and an input filter terminal, respectively, and a predetermined filter capacitance is connected to the ground. Pins 6 and 4 serve as output terminals for taking out the non-inverted output and the inverted output of the voltage controlled multivibrator, respectively. Thus, the basic circuit portion including the voltage controlled multivibrator of the phase locked loop according to the present invention can be easily configured by using a general-purpose IC.

Next, the phase synchronization pulse generator 35 in the phase synchronization circuit of FIG. 1 will be described in detail with reference to FIGS. 4 and 5. When a multivibrator circuit (VCM) as shown in FIG. 2B is used, the VC
When the duty cycle of the VCM oscillation output signal is 50%, the phase-locked pulse applied to M may be 50% or more and less than 100% of the oscillation cycle of the VCM oscillation signal, with the exceptions described later. is necessary. Therefore, it is necessary to generate a phase synchronization pulse having an optimum pulse width according to the frequency of the VCM.

FIG. 4 shows a general monostable multivibrator (see FIG.
Then, the configuration in the case where it is necessary to generate a phase synchronization pulse narrower than the minimum pulse width that can be generated by MM1 and MM2) is shown. The phase-locked pulse generator circuit of FIG. 4 has two monostable multivibrators (M
M1, MM2) 38, 39, and an exclusive OR gate (EX-OR) 41 for receiving the output of each monostable multivibrator 38, 39. The output of the exclusive OR gate 41 is applied as a phase-locked pulse to the phase-locked pulse input of the VCM 31.

FIG. 5 shows the signal waveform of each part of the circuit of FIG. 4, and shows the signal waveforms of the parts (a) to (e) of FIG. FIG. 5 (a)
An input pulse as shown in FIG. 3 is input to each monostable multivibrator 38, 39, and signals having pulse widths as shown in (b) and (c) at their respective time constants are output as monostable multivibrators 38, 3 respectively.
It is output from 9. The outputs of the monostable multivibrators 38 and 39 are exclusive-ORed by an exclusive-OR gate 41 to generate a signal as shown in (d), and this signal is applied to the phase-locked pulse input of the VCM 31. As a result, the VCM 31 makes the exclusive OR gate 4
An oscillation signal synchronized with the output pulse of 1 is output. That is, each monostable multivibrator 3
It is possible to generate a phase-locked pulse narrower than the minimum pulse width that can be generated by each monostable multivibrator 38, 39 by utilizing the time difference between the pulses that are wider than the minimum pulse width that can be generated by 8 and 39.

When the output pulse of the exclusive OR gate 41 is supplied as a phase synchronizing pulse to the base of the transistor Q3 via the resistor R3 shown in FIG. 2B, the phase synchronizing pulse becomes high. The current flowing through the emitter of the transistor Q2 during the level changes to the transistor Q3.
Is absorbed by the emitter of the transistor Q2 and the transistor Q2 is turned off, that is, turned off. At this time, the transistor Q1
Is conductive, that is, turned on. After that, when the phase synchronization pulse, that is, the output pulse of the exclusive OR gate 41 falls, the transistor Q3 turns off and the current of the transistor Q2 starts to flow. This time point becomes the oscillation start point, and the trailing edge of the pulse (d) of the exclusive OR gate 41, that is, the trailing edge of the phase-locked pulse coincides with the oscillation start point. Does not occur, that is, it becomes zero. However, a delay corresponding to the output pulse width of the monostable multivibrator 37 (MM1) occurs from the rise of the input pulse.

Next, FIG. 6 shows the configuration of the phase-locked pulse generator 35 when the VCM oscillation frequency is relatively low and a phase-locked pulse wider than the minimum pulse width that can be generated by the monostable multivibrator is sufficient. The circuit of FIG.
A monostable multivibrator 43 that receives an input pulse is provided. The monostable multivibrator 43 generates a phase synchronization pulse of 50% or more and less than 100% of the oscillation cycle of the VCM and applies it to the phase synchronization pulse input of the VCM.

FIG. 7 shows the signal waveform of each part of the phase locked loop circuit of FIG. In this case, the output (b) of the monostable multivibrator 43 generates a phase synchronization pulse having a predetermined pulse width determined by the internal time constant from the rising time of the input pulse (a). The width of this phase synchronization pulse is 50% or more of the cycle of VCM output as described above.
It is less than 00%.

In the above description, the residual time axis error does not become zero when the width of the phase synchronization pulse is narrower than half of the oscillation cycle of VCM (when the duty cycle is 50%). Therefore, the width of the phase-locked pulse is important, and more than half the oscillation period is required. If the width of the phase synchronization pulse exceeds one oscillation cycle, the number of pulses in the waveform of the oscillator output will be insufficient. If this does not cause a problem, the width of the phase synchronization pulse may be 100% or more of the oscillation cycle of the VCM. If there is a problem, the width of the phase-locked pulse is 50% of the oscillation cycle of the VCM as described above.
As described above, it is necessary to satisfy less than 100%.

Further, when the duty cycle of the output waveform of the VCM is not 50%, the time width of the off period of the switching transistor which injects the phase synchronization pulse, that is, the transistor Q2 in FIG. 2B, is the minimum pulse width. Becomes Therefore, if this is utilized, the width of the phase synchronization pulse can be changed to some extent and set.

As described above, in the phase locked loop circuit shown in FIG. 1, the voltage controlled multivibrator (VCM) can be directly phase locked by the phase locked pulse instead of the voltage control terminal. That is, the VCM output signal can be synchronized with the input pulse with zero residual time axis error.

Even if the residual time axis error is zero with respect to the input pulse, the time axis information of the input pulse itself may not be accurate in reality, resulting in a large residual time axis error. There is. Taking the time axis correction of the video signal as an example, the input pulse is a synchronization signal separated from the video signal, and this is information of the time axis depending on the goodness of the S / N (signal to noise ratio) of the video signal. Accuracy depends on. Therefore, in addition to the sync signal, the time axis information is extracted from the reference information of the color signal in the video signal (called a color burst signal, the time axis information is more accurate than the sync signal), and the time axis correction is performed. I am doing it.

When there are two types of time axis information as in the case of such a video signal, more precise phase synchronization can be performed by sequentially inputting one type of input pulse twice. Symbols A and B in the input pulse waveforms (a) of FIGS. 5 and 7 indicate the respective input pulse signals when inputting twice as described above. In this case, A can be a pulse corresponding to a sync signal separated from the video signal, and B can be an input pulse corresponding to the color burst signal. In addition,
The second B pulse may or may not be present, but when there is a B pulse, it is necessary that the information on the time axis of the B pulse is more accurate than that of the A pulse. This is because the phase locked state that is later in time continues thereafter. Therefore, it is possible to use two or more types of input pulses as the information on the time axis, and it is convenient to use the last pulse having the most precise phase information.

Next, the stabilizing circuit 37 used in the phase locked loop circuit of FIG. 1 will be described. In the phase locked loop circuit shown in FIG. 1, a voltage controlled multivibrator oscillator is used as the VCM 31. Since this multivibrator oscillator has an extremely large amount of change in the oscillation frequency with respect to the amount of change in the control voltage, it is desirable to use a stabilizing circuit that limits the range of change in the oscillation frequency.

FIG. 8 shows a control voltage-oscillation frequency characteristic (dotted line) of a VCO using a variable capacitance diode, which is used for general time axis correction, and a VCM used in the phase locked loop of the present invention. The control voltage-oscillation frequency characteristic (solid line) is shown. As is clear from this figure, the control voltage is V
When changing in the range of 1 to Vh (for example, about 1.0 V), the change amount is about ± 3 with respect to the center value of the oscillation frequency at the control voltage Vs in the case of the VCO using the variable capacitance diode.
%, Whereas the VCM used in the present invention is about ±
It reaches 50%. Therefore, it is necessary to stabilize the oscillation frequency by limiting the change range of the oscillation frequency with respect to the change of the control voltage.

FIG. 9 shows an example of a stabilizing circuit for stabilizing such an oscillation frequency. The circuit shown in the figure shows a circuit from receiving the output of the frequency comparator to applying the control voltage to the VCM 31, and includes a loop filter 29 and a stabilizing circuit 37. The loop filter 29 is the first
Of operational amplifier OP1, resistors R4, R5 and R6, and capacitors C1 and C2. When the stabilizing circuit 37 is not used, the positive terminal (+) of the operational amplifier OP1
A fixed voltage is applied to. The stabilizing circuit 37 includes an operational amplifier OP2, resistors R7 and R8, a capacitor C3, and a reference voltage source Vs. The output terminal of the operational amplifier OP2 is connected to the positive input terminal of the operational amplifier OP1,
Further, it is connected to the negative input terminal (-) of the operational amplifier OP2 through the parallel circuit of the resistor R7 and the capacitor C3. The negative terminal of the operational amplifier OP2 is connected to the control voltage input of the VCM 31 together with the output terminal of the operational amplifier OP1 via the resistor R8. The positive input terminal of the operational amplifier OP2 is connected to the reference voltage source of the control voltage Vs corresponding to the center value of the oscillation frequency of the VCM 31.

In the circuit of FIG. 9, if the stabilizing circuit 37 is not provided, the control voltage of the output of the operational amplifier OP1 can be changed from a voltage lower than Vl to a voltage higher than Vh, and when there is no input pulse. A control voltage is generated in any one of such a wide range. Even if an input pulse is applied from this state, the oscillation frequency of the VCM 31 is too far from the center frequency, so that the VCM 31 may not be synchronized with the regular oscillation frequency. In order to prevent this, the output of the operational amplifier OP1, namely VC
Operational amplifier O so that the control voltage of M31 becomes almost Vs
In the circuit P2, feedback is applied to the positive input terminal of the operational amplifier OP1. That is, the voltage Vs is applied to the positive input terminal of the operational amplifier OP2, compared with the control voltage of the VCM31, and a signal corresponding to the comparison result is fed back to the positive input terminal of the operational amplifier OP1. The strength of feedback, that is, the gain, is determined by R7 / R8, and the response speed is mainly determined by the capacitance C3. As a result, the control voltage of the VCM 31 does not greatly deviate from the vicinity of Vs regardless of the presence or absence of the input pulse, and the synchronization with the normal oscillation frequency can be obtained extremely accurately.

FIG. 10 shows the configuration of a phase locked loop circuit according to another embodiment of the present invention. In the circuit shown in FIG.
The frequency comparator 45 and the loop filter 29 constitute a feedback type frequency synchronizing circuit. The oscillation signal from the reference oscillator 47 and the output signal of the VCM 31 are applied to the input of the frequency comparator 45. The reference oscillator 47 may be used, for example, when synchronizing with other devices in a large-scale system such as a broadcasting station. The circuit from the output of the frequency comparator 45 to the VCM 31 via the loop filter 29 is provided with a stabilizing circuit 37 together with the loop filter. The loop filter 29 and the stabilizing circuit 37 may be the same as those in FIG. Further, the VCM 31 may be the same as that shown in FIG. The frequency comparator 45 detects not a phase difference between two signals but a frequency difference and outputs a voltage corresponding to the difference. By constructing such a feedback circuit, the frequency of the output signal of the VCM 31 matches that of the reference oscillator 47. Further, a phase synchronization pulse generator 35 similar to that shown in FIG. 1 is connected to the VCM 31 to perform phase synchronization between the input pulse and the oscillation signal of the VCM 31. Therefore, even in such a configuration, the phase synchronization can be performed with the residual time axis error of zero without using a complicated circuit, and a highly accurate phase synchronization signal can be obtained.

FIG. 11 shows a circuit configuration when it is desired to apply phase synchronization to the input pulse although frequency synchronization is not required.
In this case, the control voltage of the VCM 31 is the reference voltage source 49
A fixed voltage supplied by VCM3
1 oscillates at a fixed frequency. Therefore, in this case, the frequency stabilizing circuit is not necessary. Then, in the VCM 31 shown in FIG.
A phase-locked pulse oscillator 35 similar to that is connected, and the VCM 31 can be phase-locked with high precision by the input pulse. In this circuit, the oscillation output frequency of the VCM 31 can be easily set to a desired value, and the phase is synchronized by the input pulse at the set frequency.
Therefore, it can be used as a clock generator for various digital circuits.

[0058]

As described above, according to the present invention, the following excellent effects can be obtained with a simple circuit configuration.

(1) Basically, highly accurate phase synchronization can be performed with the residual time axis error of zero with respect to the input signal.

(2) Due to the feed-forward control, the phase is synchronized in about one to several cycles of the VCM after the input signal is applied, the synchronization pull-in is performed very quickly, and high-speed response is possible.

(3) Since it is not necessary to increase the frequency of the oscillator in order to reduce the residual time axis error, the circuit can be manufactured at a low price, the power consumption and the heat generation amount are small, and strong interference radio waves are generated. Also disappears.

(4) As shown in each of the above embodiments, the circuit configuration can be made to meet the required accuracy by adding and deleting the peripheral circuits, so that the circuit is highly versatile and can be used for a plurality of purposes. Can promote the standardization of.

(5) Appropriate in a circuit requiring a highly accurate residual time axis error, which has been performed by an analog circuit in the past, such as a time base collector or a time axis fluctuation correction circuit for a video signal such as high speed reproduction in a VTR. It can be used as a general-purpose clock generator that can be externally synchronized with devices that use digital circuits, and a highly accurate clock generator can be realized with a simple circuit configuration.
In particular, when the residual time axis error is important, such as in the above time base collector, by using this circuit, it is possible to perform high-speed response and highly accurate time axis correction with a simple configuration. Further, when it is used in a device that corrects the time-axis distortion of an image in high-speed forward reproduction, high-speed reverse reproduction, or the like of a VTR, it is possible to perform high-speed response and high-accuracy time-axis correction with the same simple configuration. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a phase locked loop circuit according to an embodiment of the present invention.

FIG. 2 is an electric circuit diagram (a) showing a basic configuration of a general emitter-coupled multivibrator, and an electric circuit diagram (b) showing a configuration of a voltage-controlled multivibrator oscillator usable in the phase locked loop circuit of FIG. Is.

FIG. 3 is an electric circuit diagram showing a configuration when a voltage controlled multivibrator oscillator usable in the phase locked loop circuit of FIG. 1 is realized by an integrated circuit.

FIG. 4 is a block diagram showing a configuration of the phase-locked pulse generator shown in FIG.

5 is a signal waveform diagram for explaining the operation of the circuit of FIG.

FIG. 6 is a block diagram showing another configuration example of the phase-locked pulse generator of FIG.

FIG. 7 is a signal waveform diagram for explaining the operation of the circuit of FIG.

FIG. 8 is an explanatory diagram showing the relationship between the oscillation frequency change amount and the control voltage of the voltage controlled oscillator.

9 is an electric circuit diagram showing a configuration example of a stabilizing circuit used in the circuit of FIG.

FIG. 10 is a block diagram showing a schematic configuration of a phase locked loop circuit according to another embodiment of the present invention.

FIG. 11 is a block diagram showing a schematic configuration of a phase locked loop circuit according to still another embodiment of the present invention.

FIG. 12 is a block diagram showing a basic configuration of a conventional general phase locked loop circuit.

FIG. 13 is a block diagram showing a configuration of a conventional general digital phase synchronization circuit.

FIG. 14 is a signal waveform diagram for explaining the operation of the circuit of FIG.

FIG. 15 is a block diagram showing a configuration of a circuit that has been used conventionally to digitally reduce a residual time axis error.

[Explanation of symbols]

 27 Frequency Comparator 29 Loop Filter 31 Voltage Controlled Oscillator (VCM) 33 Frequency Divider 35 Phase Lock Pulse Generator 37 Stabilization Circuit 38, 39, 43 Monostable Multivibrator 41 Exclusive OR Gate Q1, Q2, Q3 Transistor R1, R2, ..., R8 resistors I1, I2 variable current sources C, C1, C2 capacitances OP1, OP2 operational amplifiers

Claims (7)

[Claims] 1. A voltage-controlled multivibrator oscillator whose oscillation frequency changes in accordance with a control voltage, and an output signal of the voltage-controlled multivibrator oscillator or a frequency difference between a signal obtained by dividing the output signal and an input signal. A frequency comparator that generates a signal, a loop filter that generates a control voltage for supplying to the voltage controlled multivibrator oscillator based on a signal output from the frequency comparator, and an oscillation signal of the voltage controlled multivibrator oscillator And a phase control circuit for regulating the phase of the oscillation signal by the input signal to synchronize the phase of the oscillation signal with the phase of the input signal. 2. The voltage controlled multivibrator oscillator is an astable multivibrator oscillator comprising a pair of transistors having a collector and a base substantially cross-coupled to each other and a capacitor connected between the emitters, and The feedforward control type phase-locked circuit according to claim 1, wherein the control circuit directly regulates a charge or discharge cycle of the capacitor from the outside by a phase-locking pulse generated from the input signal. 3. The frequency stabilizing circuit for limiting a variation range of a control voltage output from the frequency comparator and applied to the voltage controlled multivibrator oscillator, according to claim 1 or 2. The feedforward control type phase locked loop circuit described. 4. A voltage controlled multivibrator oscillator whose oscillation frequency changes according to a control voltage, and a frequency difference between an output signal of the voltage controlled multivibrator oscillator or a signal obtained by dividing the output signal and a reference frequency signal. A frequency comparator that generates a signal according to, a loop filter that generates a control voltage for supplying to the voltage controlled multivibrator oscillator based on the signal output from the frequency comparator, and the voltage controlled multivibrator oscillator. A feedforward control type phase synchronization, comprising: a phase control circuit that regulates the phase of the oscillation signal by a phase control input signal to synchronize the phase of the oscillation signal with the phase of the phase control input signal. circuit. 5. The voltage controlled multivibrator oscillator is an astable multivibrator oscillator comprising a pair of transistors having a collector and a base substantially cross-coupled to each other and a capacitor connected between the emitters, and the phase 5. The feedforward control type phase synchronization circuit according to claim 4, wherein the control circuit directly regulates a charge or discharge cycle of the capacitance from the outside by a phase synchronization pulse generated from the phase control input signal. 6. The frequency stabilizing circuit according to claim 4, further comprising a frequency stabilizing circuit for limiting a variation range of a control voltage output from the frequency comparator and applied to the voltage controlled multivibrator oscillator. The feedforward control type phase locked loop circuit described. 7. An astable multivibrator oscillator having a capacity for determining an oscillation frequency, and a charge or discharge cycle of the capacity of the astable multivibrator oscillator directly externally controlled by a phase synchronization pulse generated from an input signal. And a phase control circuit that regulates the phase of the oscillation signal of the unstable multivibrator oscillator by the input signal to synchronize the phase of the oscillation signal with the phase of the input signal. Type phase synchronization circuit.