JPH03216565A - Input threshold value voltage measuring system - Google Patents

Abstract

PURPOSE:To accurately calculate the dynamic input threshold voltage of a semiconductor integrated circuit by calculating input threshold voltage from the difference between delay times of outputs changing with respect to a plurality of inputs different in inclination. CONSTITUTION:The pin electronics circuit 22 of a tester supplies the first and second input signals different in inclination and same in the voltage difference between an L-level and an H-level to a semiconductor integrated circuit 20 according to the control program of a memory 23. The circuit 22 detects the delay time from the start of the rising of the output to the first input of the circuit 20 to the falling of the output to the second input thereof to calculate input threshold voltage by operation. By this method, a dynamic input threshold value having inclination is calculated.

Description

[Detailed Description of the Invention] (Summary) This method uses an input threshold voltage measurement method to measure the input threshold voltage of a semiconductor integrated circuit in actual operation, and accurately measures the input threshold voltage under actual operating conditions of the semiconductor integrated circuit. With the purpose of A plurality of input signals having different slopes of decline are supplied to the semiconductor integrated circuit, and the difference in delay time until the output signal of the semiconductor integrated circuit changes with respect to each of the plurality of input signals is determined. The input threshold voltage is determined using the difference in slope and the difference in delay time.

[Industrial application field]

The present invention relates to an input threshold voltage measurement method, and more particularly, to an input threshold voltage measurement method for measuring the input threshold voltage of a semiconductor integrated circuit in actual operation.

[Conventional technology]

Conventionally, as shown in FIG. 5, a semiconductor integrated circuit 10 as a circuit under test is connected to a tester 11.
The input threshold voltage is being measured.

For example, in the case of a high-level input threshold, the low-level voltage ViL of the input signal supplied from the tester 11 to the semiconductor integrated circuit 10 is fixed and set as the H-level voltage Vifl1, and then the H-level voltages are sequentially applied to ViH2...viHn. The tester 11 compares the output signal of the semiconductor integrated circuit 10 with the expected value and ends the test when they match,
The voltage of the input signal at that time is set as the high-level input threshold of the semiconductor integrated circuit 10.

[Problem to be solved by the invention]

The conventional measurement method has a problem in that the input threshold value of the semiconductor integrated circuit 10 is a static value, which differs from a dynamic value under actual usage conditions. Furthermore, if noise or the like is superimposed on the input signal, there is a problem in that measurement errors become large and accurate input steel values cannot be determined.

The present invention has been made in view of the above points, and an object of the present invention is to provide an input threshold measurement method that accurately measures an input threshold under actual usage conditions of the semiconductor integrated circuit 10.

(Means for solving the problem:!R) The input threshold voltage measurement method of the present invention supplies an input signal to a semiconductor integrated circuit, measures the output signal of the semiconductor integrated circuit, and calculates the input threshold voltage of the semiconductor integrated circuit. In the input threshold voltage measurement method, multiple input signals with different rising or falling slopes are supplied to a semiconductor integrated circuit, and the delay time until the output signal of the semiconductor integrated circuit changes in response to each of the multiple input signals is calculated. The difference is determined, and the input threshold voltage is determined using the difference in slope of the plurality of input signals and the difference in delay time.

(Operation) In the present invention, the input threshold voltage is determined from the difference between the slope of the rising or falling slope of the input signal and the delay time.

In other words, since the input vAlaN pressure is determined using a dynamic input signal with a slope, it is possible to determine the dynamic input threshold voltage under actual usage conditions. is smaller than the standard input threshold measurement.

〔Example〕

FIG. 3 shows a block diagram of a test configuration to which the method of the present invention is applied.

In the figure, input and output terminals of a semiconductor integrated circuit 20 serving as the test circuit are connected to a bin electronics circuit 22 of a tester 21.

A control unit 23 in the tester 21 executes a control program stored in a memory 24 to control the operation of the bin electronics circuit 22 , and also reads out test data and comparison pattern data from the test memory 25 and sends them to the bin electronics circuit 22 . supply

The bin electronics circuit 22 has the configuration shown in FIG. Test data from the test memory 25 supplied to the terminal 30a is stored in the drive pattern register 32 and supplied to the waveform synthesis circuit 33. Clock selection circuit 3
5 selects a clock according to the signal supplied from the control section 23 via the terminal 31a and supplies it to the waveform synthesis circuit 33.
selects a waveform mode such as NRZ waveform or R2 waveform according to the signal supplied via the waveform synthesis circuit 33;
The waveform synthesis circuit 33 performs waveform synthesis based on these signals and supplies the result to an output buffer 734. Output buffer 34
is connected to the terminal 31c from the IIIJw section 23. 31d, 31e
TI/0 control signal, high level instruction voltage ■i
High and low level instruction voltages ViO are supplied, and the output buffer 34 generates an input signal of a voltage according to these, and supplies it to the semiconductor integrated circuit 20 from the terminal 37.

Further, the output signal of the semiconductor integrated circuit 20 that enters the terminal 40 is supplied to the comparators 42 and 43 via the buffer 41, and the high-level threshold voltage VOH supplied from the control unit 23 via the terminals 31f and 310 is supplied here to the comparators 42 and 43. , low level threshold voltage vO[, the pattern comparison circuit 44
is supplied to The pattern comparison circuit 44 is supplied with comparison pattern data from a comparison pattern register 45 that stores comparison pattern data supplied from the test memory 25 via the terminal 30b, and the pattern comparison circuit 44 converts the output signal pattern into this comparison pattern. It compares it with the data and supplies the comparison result to the ill control section 23 from the terminal 46.

In the present invention, the tester 21 is shown in FIGS.
As shown in each figure, two types of input signals with different slopes at
, a2 are generated and separately supplied to the semiconductor integrated circuit 20. The voltages VH between the L level and H level of these two types of input signals are the same.

This figure 1 (A). (C) From the semiconductor integrated circuit 20 in response to each input signal afta2 as shown in FIG. 1(B). (D) The output signals shown in each case are obtained.

The tester 21 detects the rising edge of the input signal a1 shown in FIG. 1(A). The delay time 11 -10 from 11-10 to the falling edge detection time t1 of the output signal in FIG. 1(B) and from the rising start time t2 of the input signal a2 in FIG. 1(C) to the time t2 of the output signal in FIG. 1(D) Delay time t3- until falling detection time t3
Find the difference Δt from t2. Also, Fig. 1(A). (C)
Each rise time T+. Since each T2 is known, the input threshold voltage viHTH is determined by the following equation.

ViHTH=Δt×VH/(Tt−T2)
(1) In this equation, T+-T2 is the input signal a+,8
This is caused by the difference in slope between the two.

In order to explain equation (1), if the input signals at, a2 and time t3 of FIG. 1 (A>.(C) are aligned, the input signal a+ of FIG. 1(A). The rise of a2 is as shown in Fig. 2. Here, d+ and 62 are the times from when the input signals a+ and aZ each reach the threshold voltage Vi old 11 from the start of rising, and the following relationship holds true. .

VH / T + = V iHTH / d + VH /
T2=Vi old H/dz d+ -d2 =Δt Therefore, △t = (T+ -T2) ・VillT
ll/Vll This leads to equation (1).

In this way, using equation (1), input signals aH, az
The input threshold voltage is determined from the difference between the rising slope of and the delay time. In other words, since a dynamic input threshold voltage with a slope is determined, a dynamic input threshold voltage under actual usage conditions can be determined. Furthermore, since the input signal has a predetermined rising edge, the measurement error is smaller even if noise is superimposed on the input signal, compared to a conventional input signal in which the H level voltage is fixed.

In the above embodiments, the measurement of high level input equivalent voltages has been described as an example, but the same applies to the measurement of low level input thresholds, and the present invention is not limited to the above embodiments.

〔Effect of the invention〕

As described above, according to the input equivalent voltage measurement method of the present invention,
The dynamic input threshold voltage of a semiconductor integrated circuit under actual usage conditions can be accurately measured, and the influence of noise is small, making it extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is an input/output signal waveform diagram for explaining the method of the present invention, FIG. 2 is a diagram for explaining the principle of the method of the present invention, and FIG. 3 is a block diagram of a test mechanism to which the method of the present invention is applied. FIG. 4 is a block diagram of the bin electronics circuit, and FIG. 5 is a block diagram of a conventional test mechanism. In the figure, 20 is a semiconductor integrated circuit, 21 is a tester, 22 is a bin electronics circuit, 23 is an IIJw section, 24 is a memory, and 25 is a test memory.

Claims (1)

[Claims] An input threshold voltage for supplying an input signal to a semiconductor integrated circuit (20), measuring an output signal of the semiconductor integrated circuit (20), and measuring an input threshold voltage of the semiconductor integrated circuit (20). In the measurement method, a plurality of input signals having different rising or falling slopes are supplied to the semiconductor integrated circuit (20), and the output signal of the semiconductor integrated circuit (20) for each of the plurality of input signals changes. An input threshold voltage measuring method characterized in that: a difference in delay time is determined; and an input threshold voltage is determined using the difference in slope of the plurality of input signals and the difference in delay time.