JPH07111454B2 - Input threshold voltage measurement method - Google Patents
Input threshold voltage measurement methodInfo
- Publication number
- JPH07111454B2 JPH07111454B2 JP2012380A JP1238090A JPH07111454B2 JP H07111454 B2 JPH07111454 B2 JP H07111454B2 JP 2012380 A JP2012380 A JP 2012380A JP 1238090 A JP1238090 A JP 1238090A JP H07111454 B2 JPH07111454 B2 JP H07111454B2
- Authority
- JP
- Japan
- Prior art keywords
- threshold voltage
- input
- semiconductor integrated
- integrated circuit
- input threshold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Testing Of Individual Semiconductor Devices (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】 〔概要〕 半導体集積回路の実動作の入力閾値電圧を測定する入力
閾値電圧測定方法に関し、 半導体集積回路の実使用条件での正確な入力閾値電圧を
測定することを目的とし、 半導体集積回路に入力信号を供給して該半導体集積回路
の出力信号を測定し、該半導体集積回路の入力閾値電圧
を測定する入力閾値電圧測定方法において、立上がり又
は立下がりの傾きが異なる複数の入力信号を該半導体集
積回路に供給し、該複数の入力信号夫々に対する該半導
体集積回路の出力信号が変化するまでの遅延時間の差を
求め、該複数の入力信号の傾きと該遅延時間の差とを用
いて入力閾値電圧を求めるよう構成する。The present invention relates to an input threshold voltage measuring method for measuring an input threshold voltage of actual operation of a semiconductor integrated circuit, and an object of the present invention is to measure an accurate input threshold voltage under actual use conditions of the semiconductor integrated circuit. In the input threshold voltage measuring method of supplying an input signal to the semiconductor integrated circuit, measuring the output signal of the semiconductor integrated circuit, and measuring the input threshold voltage of the semiconductor integrated circuit, a plurality of different rising or falling slopes are provided. Is input to the semiconductor integrated circuit, the difference in the delay time until the output signal of the semiconductor integrated circuit changes with respect to each of the plurality of input signals is obtained, and the slope of the plurality of input signals and the delay time The difference is used to obtain the input threshold voltage.
本発明は入力閾値電圧測定方法に関し、半導体集積回路
の実動作の入力閾値電圧を測定する入力閾値電圧測定方
法に関する。The present invention relates to an input threshold voltage measuring method, and more particularly to an input threshold voltage measuring method for measuring an input threshold voltage of actual operation of a semiconductor integrated circuit.
従来、第５図に示す如く、被測定回路としての半導体集
積回路10をテスタ11に接続して半導体集積回路10の入力
閾値電圧を測定している。例えばハイレベルの入力閾値
の場合、テスタ11より半導体集積回路10に供給する入力
信号のＬレベルの電圧V iLを固定してＨレベルの電圧V
iH1とし、以下順次Ｈレベルの電圧がV iH2,…V iHnと異
なる信号を供給し、半導体集積回路10の出力信号をテス
タ11で期待値と比較して一致したときに試験を終了し、
そのときの入力信号の電圧を半導体集積回路10のハイレ
ベルの入力閾値としている。Conventionally, as shown in FIG. 5, a semiconductor integrated circuit 10 as a circuit to be measured is connected to a tester 11 to measure an input threshold voltage of the semiconductor integrated circuit 10. For example, in the case of a high level input threshold, the L level voltage V iL of the input signal supplied from the tester 11 to the semiconductor integrated circuit 10 is fixed and the H level voltage V iL is fixed.
iH1 is supplied, and a signal whose H level voltage is sequentially different from V iH2, ... V iHn is supplied, and when the output signal of the semiconductor integrated circuit 10 is compared with the expected value by the tester 11, the test ends, and the test ends.
The voltage of the input signal at that time is used as the high-level input threshold of the semiconductor integrated circuit 10.
従来の測定方法では半導体集積回路10の入力閾値は静的
な値であり、実使用条件での動的な値とは異なってしま
うという問題があった。また入力信号にノイズ等が重畳
すると測定誤差が大きくなり正確な入力閾値を求めるこ
とができないという問題があった。The conventional measurement method has a problem that the input threshold value of the semiconductor integrated circuit 10 is a static value, which is different from the dynamic value under actual use conditions. Further, when noise or the like is superposed on the input signal, a measurement error becomes large and an accurate input threshold value cannot be obtained.
本発明は上記の点に鑑みなされたもので、半導体集積回
路10の実使用条件での正確な入力閾値を測定する入力閾
値測定方法を提供することを目的とする。The present invention has been made in view of the above points, and an object thereof is to provide an input threshold value measuring method for measuring an accurate input threshold value under actual use conditions of the semiconductor integrated circuit 10.
本発明の入力閾値電圧測定方法は、 半導体集積回路に入力信号を供給して半導体集積回路の
出力信号を測定し、半導体集積回路の入力閾値電圧を測
定する入力閾値電圧測定方法において、 立上がり又は立下がりの傾きが異なる複数の入力信号を
半導体集積回路に供給し、 複数の入力信号夫々に対する半導体集積回路の出力信号
が変化するまでの遅延時間の差を求め、 複数の入力信号の傾きと該遅延時間の差とを用いて入力
閾値電圧を求める。The input threshold voltage measuring method of the present invention is an input threshold voltage measuring method of supplying an input signal to a semiconductor integrated circuit, measuring an output signal of the semiconductor integrated circuit, and measuring an input threshold voltage of the semiconductor integrated circuit. A plurality of input signals having different falling slopes are supplied to the semiconductor integrated circuit, and a difference in delay time until the output signal of the semiconductor integrated circuit changes with respect to each of the plurality of input signals is obtained. The input threshold voltage is obtained using the time difference.
本発明においては、入力信号の立上がり又は立下がりの
傾きと遅延時間との差から入力閾値電圧を求める。つま
り傾きを持った動的な入力信号で入力閾値電圧を求める
ため、実使用条件での動的な入力閾値電圧を求めること
ができ、また入力信号にノイズが重畳した場合の誤差が
従来の静的な入力閾値の測定よりも小さくなる。In the present invention, the input threshold voltage is obtained from the difference between the rising or falling slope of the input signal and the delay time. In other words, since the input threshold voltage is calculated using a dynamic input signal having a slope, it is possible to calculate the dynamic input threshold voltage under actual use conditions. Smaller than a typical input threshold measurement.
第３図は本発明方法を適用した試験構成のブロック図を
示す。FIG. 3 shows a block diagram of a test configuration to which the method of the present invention is applied.
同図中、該試験回路としての半導体集積回路20の入力、
出力夫々の端子はテスタ21のピンエレクトロニクス回路
22に接続されている。In the figure, the input of the semiconductor integrated circuit 20 as the test circuit,
Each output terminal is a pin electronics circuit of tester 21
Connected to 22.
テスタ21内の制御部23はメモリ24に格納されている制御
プログラムを実行し、ピンエレクトロニクス回路22の動
作制御を行なうと共に、テストメモリ25からテストデー
タ及び比較パターンデータを読出してピンエレクトロニ
クス回路22に供給する。The control unit 23 in the tester 21 executes the control program stored in the memory 24, controls the operation of the pin electronics circuit 22, and reads the test data and the comparison pattern data from the test memory 25 to the pin electronics circuit 22. Supply.
ピンエレクトロニクス回路22は第４図に示す構成であ
る。端子30aに供給されるテストメモリ25よりのテスト
データはドライブパターンレジスタ32に格納されて波形
合成回路33に供給される。クロック選択回路35は制御部
23より端子31aを介して供給される信号に応じてクロッ
クを選択して波形合成回路33に供給し、波形モード選択
回路36は制御部23より端子31bを介して供給される信号
に応じてNRZ波形,RZ波形等の波形モードを選択して波形
合成回路33に供給し、波形合成回路33はこれらの信号に
基づいて波形合成を行ない出力バッファ34に供給する。
出力バッファ34には制御部23より端子31c,31d,31e夫々
を介してI/O制御信号、ハイレベル指示電圧V iH,ローレ
ベル支持電圧V iOが供給され、出力バッファ34にこれら
に従った電圧の入力信号を生成して端子37より半導体集
積回路20に供給する。The pin electronics circuit 22 has the structure shown in FIG. The test data from the test memory 25 supplied to the terminal 30a is stored in the drive pattern register 32 and supplied to the waveform synthesis circuit 33. The clock selection circuit 35 is a control unit
A clock is selected according to the signal supplied from the terminal 23 via the terminal 31a and supplied to the waveform synthesis circuit 33, and the waveform mode selection circuit 36 controls the NRZ according to the signal supplied from the control section 23 via the terminal 31b. A waveform mode such as waveform or RZ waveform is selected and supplied to the waveform synthesizing circuit 33, and the waveform synthesizing circuit 33 performs waveform synthesizing based on these signals and supplies it to the output buffer 34.
The output buffer 34 is supplied with the I / O control signal, the high-level instruction voltage V iH, and the low-level support voltage V iO from the control unit 23 via the terminals 31c, 31d, 31e, respectively, and the output buffer 34 follows them. A voltage input signal is generated and supplied from the terminal 37 to the semiconductor integrated circuit 20.
また、端子40に入来する半導体集積回路20の出力信号は
バッファ41を介してコンパレータ42,43に供給され、こ
こで制御部23より端子31f,31gを介して供給されるハイ
レベル閾値電圧ＶOH，ローレベル閾値電圧ＶOLと比較さ
れた後、パターン比較回路44に供給される。パターン比
較回路44にはテストメモリ25より端子30bを介して供給
される比較パターンデータを格納した比較パターンレジ
スタ45より比較パターンデータが供給されており、パタ
ーン比較回路44は出力信号パターンをこの比較パターン
データと比較してその比較結果を端子46から制御部23に
供給する。Further, the output signal of the semiconductor integrated circuit 20 coming into the terminal 40 is supplied to the comparators 42 and 43 via the buffer 41, and here the high level threshold voltage VOH supplied from the control unit 23 via the terminals 31f and 31g. , And is supplied to the pattern comparison circuit 44 after being compared with the low level threshold voltage VOL. The comparison pattern data is supplied to the pattern comparison circuit 44 from the comparison pattern register 45 which stores the comparison pattern data supplied from the test memory 25 through the terminal 30b. The pattern comparison circuit 44 outputs the output signal pattern to this comparison pattern. The result of comparison with the data is supplied from the terminal 46 to the control unit 23.
本発明においては、テスタ21は第１図（Ａ），（Ｃ）夫
々に示す如く、傾きの異なる２種類の入力信号a1,a2を
生成して別々に半導体集積回路20に供給する。この２種
類の入力信号のＬレベル、Ｈレベル間の電圧VHは互いに
同一である。この第１図（Ａ），（Ｃ）夫々の入力信号
a1,a2に対して半導体集積回路20より第１図（Ｂ），
（Ｄ）夫々に示す出力信号が得られる。In the present invention, the tester 21, as shown in FIGS. 1A and 1C, respectively, generates two types of input signals a 1 and a 2 having different slopes and supplies them to the semiconductor integrated circuit 20 separately. The voltage VH between the L level and the H level of these two types of input signals is the same. Input signals of FIG. 1 (A) and (C) respectively
a 1, a first view from the semiconductor integrated circuit 20 with respect to a 2 (B),
(D) The output signals shown in each are obtained.
テスタ21は第１図（Ａ）の入力信号a1の立がり開始時点
t0から第１図（Ｂ）の出力信号の立下がり検出時点t1ま
での遅延時間t1−t0と第１図（Ｃ）の入力信号a2の立上
がり開始時点t2から第１図（Ｄ）の出力信号の立下がり
検出時点t3までの遅延時間t3−t2との差Δｔを求める。
また、第１図（Ａ），（Ｃ）夫々の立上がり時間T1,T2
夫々は既知であるから次式により入力閾値電圧V iHTHを
求める。Standing rising start point of the input signal a 1 of the tester 21 is first diagram (A)
Figure 1 from the start time t 2 rising edge of the input signal a 2 with delay time t 1 -t 0 of the standing up edge detection time point t 1 FIG. 1 (C) of the output signal from t 0 Fig. 1 (B) The difference Δt from the delay time t 3 −t 2 until the fall detection time t 3 of the output signal of (D) is obtained.
In addition, the rise times T 1 and T 2 of FIGS. 1A and 1C, respectively.
Since each is known, the input threshold voltage V iHTH is calculated by the following equation.
V iHTH＝△ｔ×VH/（T1−T2） （１） この式でT1−T2は入力信号a1,a2夫々の傾きの差から生
じる。V iHTH = Δt × VH / (T 1 −T 2 ) (1) In this equation, T 1 −T 2 is generated from the difference in slope between the input signals a 1 and a 2 .
（１）式を説明するために、第１図（Ａ），（Ｃ）夫々
の入力信号a1,a2の時点t1,t3をそろえると第１図
（Ａ），（Ｃ）の入力信号a1,a2の立上がりは第２図に
示す如くなる。ここでd1,d2夫々は入力信号a1,a2夫々が
立上がり開始から閾値電圧V iHTHとなるまでの時間であ
り、次式の関係が成立する。In order to explain the equation (1), when the time points t 1 and t 3 of the input signals a 1 and a 2 of FIGS. 1 (A) and 1 (C) are aligned, FIG. 1 (A) and 1 (C) are obtained. The rising edges of the input signals a 1 and a 2 are as shown in FIG. Here, d 1 and d 2 are the times from the start of rising of the input signals a 1 and a 2 to the threshold voltage V iHTH, respectively, and the relationship of the following equation is established.
VH/T1＝V iHTH/d1 VH/T2＝V iHTH/d2 d1−d2＝△ｔ このため△ｔ＝（T1−T2）・V iHTH/VH これによって（１）式が導びかれる。VH / T 1 = V iHTH / d 1 VH / T 2 = V iHTH / d 2 d 1 −d 2 = Δt Therefore, Δt = (T 1 −T 2 ) · V iHTH / VH Due to this, (1) The formula is derived.
このように、（１）式を用いて入力信号a1,a2の立上が
りの傾きと遅延時間との差から入力閾値電圧を求める。
つまり傾きを持った動的な入力閾値電圧を求めるため、
実使用条件での動的な入力閾値電圧を求めることができ
る。また、入力信号の立上がりは所定の傾きがあるた
め、従来の如くＨレベルの電圧が固定の入力信号に比し
て、入力信号にノイズが重畳しても測定誤差が小さくな
る。In this way, the input threshold voltage is obtained from the difference between the rising slopes of the input signals a 1 and a 2 and the delay time using the equation (1).
In other words, to obtain a dynamic input threshold voltage with a slope,
It is possible to obtain a dynamic input threshold voltage under actual use conditions. In addition, since the rising edge of the input signal has a predetermined slope, the measurement error is smaller even if noise is superimposed on the input signal, as compared with the conventional input signal in which the H level voltage is fixed.
なお、上記実施例ではハイレベルの入力閾値電圧の測定
を例として説明したが、これはローレベルの入力閾値の
測定でも同様であり、上記実施例に限定されない。In addition, although the measurement of the high level input threshold voltage has been described as an example in the above-described embodiment, this is the same in the measurement of the low level input threshold voltage and is not limited to the above-described embodiment.
上述の如く、本発明の入力閾値電圧測定方法によれば、
半導体集積回路の実使用条件での動的な入力閾値電圧を
正確に測定でき、ノイズによる影響が小さくて済み、実
用上きわめて有用である。As described above, according to the input threshold voltage measuring method of the present invention,
The dynamic input threshold voltage can be accurately measured under the actual use conditions of the semiconductor integrated circuit, and the influence of noise is small, which is extremely useful in practice.
第１図は本発明方法を説明するための入出力信号波形
図、 第２図は本発明方法の原理を説明するための図、 第３図は本発明方法を適用した試験機構のブロック図、 第４図はピンエレクトロニクス回路のブロック図、 第５図は従来の試験機構のブロック図である。 図において、 20は半導体集積回路、 21はテスタ、 22はピンエレクトロニクス回路、 23は制御部、 24はメモリ、 25はテストメモリ を示す。FIG. 1 is an input / output signal waveform diagram for explaining the method of the present invention, FIG. 2 is a diagram for explaining the principle of the method of the present invention, and FIG. 3 is a block diagram of a test mechanism to which the method of the present invention is applied. FIG. 4 is a block diagram of a pin electronics circuit, and FIG. 5 is a block diagram of a conventional test mechanism. In the figure, 20 is a semiconductor integrated circuit, 21 is a tester, 22 is a pin electronics circuit, 23 is a control unit, 24 is a memory, and 25 is a test memory.
Claims (1)
て該半導体集積回路（20）の出力信号を測定し、該半導
体集積回路（20）の入力閾値電圧を測定する入力閾値電
圧測定方法において、 立上がり又は立下がりの傾きが異なる複数の入力信号を
該半導体集積回路（20）に供給し、 該複数の入力信号夫々に対する該半導体集積回路（20）
の出力信号が変化するまでの遅延時間の差を求め、 該複数の入力信号の傾きと該遅延時間の差とを用いて入
力閾値電圧を求めることを特徴とする入力閾値電圧測定
方法。1. An input threshold voltage measurement for supplying an input signal to a semiconductor integrated circuit (20), measuring an output signal of the semiconductor integrated circuit (20), and measuring an input threshold voltage of the semiconductor integrated circuit (20). In the method, a plurality of input signals having different rising or falling slopes are supplied to the semiconductor integrated circuit (20), and the semiconductor integrated circuit (20) for each of the plurality of input signals.
The input threshold voltage measuring method is characterized in that a difference in delay time until the output signal changes is obtained, and an input threshold voltage is obtained by using the slopes of the plurality of input signals and the difference in the delay times.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012380A JPH07111454B2 (en) | 1990-01-22 | 1990-01-22 | Input threshold voltage measurement method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012380A JPH07111454B2 (en) | 1990-01-22 | 1990-01-22 | Input threshold voltage measurement method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03216565A JPH03216565A (en) | 1991-09-24 |
| JPH07111454B2 true JPH07111454B2 (en) | 1995-11-29 |
Family
ID=11803669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012380A Expired - Fee Related JPH07111454B2 (en) | 1990-01-22 | 1990-01-22 | Input threshold voltage measurement method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07111454B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007085932A (en) * | 2005-09-22 | 2007-04-05 | Verigy (Singapore) Pte Ltd | Input threshold level measuring technique and input threshold level measuring device |
| JP2008102060A (en) * | 2006-10-20 | 2008-05-01 | Yokogawa Electric Corp | Timing calibration circuit and timing calibration method of semiconductor testing device |
-
1990
- 1990-01-22 JP JP2012380A patent/JPH07111454B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03216565A (en) | 1991-09-24 |
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