JPS62137575A - Logic circuit tester - Google Patents

Abstract

PURPOSE:To enable the delay time between an input terminal and an output terminal, between the input terminal and an F/F and between the F/F and the output terminal to be accurately measured by inserting a pattern to which a pattern applied to an external input terminal is inverted into the midway of a function test pattern. CONSTITUTION:When inputted with an external input terminal applied pattern, the input device 3 of a logic circuit tester 1 feeds a bit pattern to a pattern inverting device 4. The inverting device 4 generates an inverted pattern 5 to which an inputted bit pattern is inverted. A pattern editing device 6 inserts the pattern 5 into the suitable location of the pattern 2 inputted from the input device 3 and edits a test pattern 7 to be inputted to a test unit 8. The test unit 8, inputted with the pattern 7, applies it to a circuit 9 to be tested and the circuit 9 is tested by applying an input pattern and comparing output patterns. Thus, a delay time from the change in an input to the change in an output can be accurately measured. Further, the set up time of an F/F for the change in an external input and the delay time from the change in the F/F to the change in an output can be accurately measured.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a logic circuit tester.

[Prior Art] Conventionally, there is a test method using a scan canvas as a test method for logic circuits (for example, Information Processing Society of Japan, "CAD of Logic Devices", Chapter 4.5, pages 79-82, Ohmsha Shoten, S.
56). In this test method, the register is set to scan mode to operate as a shift register and an input pattern is applied serially to the register, then the normal mode is set to apply a clock, and the register is set to scan mode again to operate as a shift register. Logic circuits were tested by serially reading out values stored in registers.

[Problem that the invention seeks to solve]

In the conventional logic circuit testing method using the scan path described above, the scanning operation on the test machine takes time, and since failure detection is primarily considered, the timing from input change to clock application is testing, delay time testing from input change to output change, and F/F/
This method has the disadvantage that it is not possible to adequately test the delay time from a change in F to a change in output.

Means for Solving Problem C] The logic circuit tester of the present invention includes an input section for inputting a functional test pattern, a pattern inverting section for inverting the external input terminal application pattern in the functional test pattern, and a pattern inverting section for inverting the external input terminal application pattern in the functional test pattern. It has a pattern editing section that inserts the pattern into the original functional test pattern, and a testing section that applies the edited pattern to the logic circuit under test and performs the test.

In this way, by inserting an inverted pattern of the input terminal application pattern in the middle of the functional test pattern, the delay time between the input terminal and the output terminal, between the input terminal and the FZF, and between the F/F and the output terminal can be reduced. Can be measured accurately.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the essential parts of the logic circuit tester of the present invention.

This logic circuit tester 1 has an input section 3 into which a functional test pattern 2 is input, an external input terminal application pattern 10 in the functional test pattern 2 is received from the input section 3, the bit pattern is inverted, and an inverted pattern 5 is obtained. Insert the inverted pattern 5 generated by the pattern inverting unit 4 into an appropriate position of the functional test pattern 2 inputted by the input unit 3.
A pattern editing section 6 edits and outputs the test pattern 7, inputs the edited test pattern 7, applies it to the circuit under test 9, applies the input pattern and compares the output pattern, and outputs the circuit under test 9. It is equipped with a test section 8 for testing.

Next, the operation of this logic circuit tester will be explained in detail.

FIG. 2 is a diagram showing an example of functional test pattern 2. This functional test pattern 2 includes a Tato part input terminal application pattern 10, a scan in pattern 11 for manually setting a value in the scan register, and an external output terminal correct value pattern +2.14.
, the clock application pattern 13, and the scan out pattern 15 which is the correct value when reading out the data in the scan register serially are arranged in the order of processing. Here, each bit of the bit pattern 16 is applied to each external input terminal for the external input terminal application pattern 10, and to each F/F of the scan register for the scan-in pattern 11a and the scan-out pattern 15. Value pattern 12, 1
4 corresponds to each external output terminal.

FIG. 3 is a diagram showing an example of the inversion pattern 5. When the input section 3 receives the external input terminal application pattern 10, it sends the bit pattern 16 to the pattern inversion section 4. The pattern reversing unit 4 converts “O” of the input bit pattern 16 into “1”.
External input terminal inverted application pattern 2 with ° reversed to “o”
0 and a continuous inverted pattern 5 of the original input bit pattern 10. FIG. 4 is a diagram showing an example of the test pattern 7 edited by the pattern editing section 6. The pattern editing section 6 is arranged between the scan-in pattern 11 and the external output terminal correct value pattern 12 and between the external output terminal correct value pattern 12 and the clock application pattern 13 of the functional test pattern 2 input from the input section 3. A reverse pattern 57j is inserted.

FIG. 5 is a diagram showing an example of a test waveform applied to the circuit under test 9 by the test section 8.

A strobe waveform 55 represents the timing at which Jlm of the external output terminal is sampled and compared with the correct answer.Here, the strobe pulse rise time 56 is determined from when a change appears at the external output terminal after the value of the external input terminal changes. If it is too early, it will no longer match the correct value and an error will occur. Therefore,
By varying the strobe pulse rise time 56 and measuring the minimum time that does not cause an error, it is possible to accurately measure the delay time from an input change to an output change. In addition, if the clock pulse rise time 57 is earlier than the F/F setup time in response to an external input change, the F/F will take in the value before the change due to clock application, and when scan-out is performed, the correct value will be returned. will not match and an error will occur. Therefore, by changing the clock pulse rise time 57 and measuring the minimum time that does not cause an error, it is possible to accurately measure the setup time of the F/F in response to external input changes. Furthermore, if the clock-strobe pulse interval 58 is shorter than the time from when the F/F changes due to clock application until that change appears at the external output terminal, it will not match the correct value at the output terminal and an error will occur. . Therefore, by varying the clock-strobe pulse interval 58 and measuring the minimum time that does not cause an error, it is possible to accurately measure the delay time from a change in F/F to a change in output.

(Effects of the Invention) As explained above, the present invention inserts a pattern that is an inversion of the external input terminal application pattern in the middle of the functional test pattern, thereby providing a This has the effect that the delay time between the F and output terminals can be measured with high accuracy.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of an embodiment of the logic circuit tester of the present invention, FIG. 2 is a diagram showing an example of the functional test pattern 2 that is input to the tester, and FIG. A fourth diagram illustrating an example of the inverted pattern 5 that is the output of the pattern inverting section 4 in the figure.
The figure shows the test pattern 7 which is the output of the pattern editing section 6 in Figure 1.
FIG. 5 is a diagram showing an example of a test waveform applied to the circuit under test 9 by the test section 8 of FIG. DESCRIPTION OF SYMBOLS 1...Logic port 8 tester, 2...Function test pattern, 3...Input section, 4...Pattern inversion section, 5...Inversion pattern, 6...Pattern editing section, 7. ...Test pattern, 8...Test section, 9...Circuit under test, 10...External input terminal application pattern, 11...Scan in pattern, 12, 14...External output terminal correct value pattern , 13...
・Clock application pattern, 15... Scan out pattern, 16... Hit pattern, 20... External input terminal inverted application pattern, 30, 31.
...Inserted inversion pattern, 51, 52.53... Waveform applied to external input terminal, 54... Clock pulse, 55... Strobe pulse, 56... Strobe pulse rise time, 57... Clock Pulse rise time, 58...Clock-strobe pulse interval. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] An input section for inputting a functional test pattern, a pattern inversion section for inverting an external input terminal application pattern in the functional test pattern, and a pattern editing section for inserting the inverted pattern into the original functional test pattern. A logic circuit testing machine comprising: a test section that applies the edited pattern to a logic circuit under test and performs a test.