JPS63279180A - Logic circuit tester - Google Patents

Abstract

PURPOSE:To measure a delay time between input and output terminals and a setup time between the input terminal and a register at a high accuracy, by inverting a specified input terminal pattern immediately before the application of a clock and the comparison of an output expected value. CONSTITUTION:A pattern generating section 4 inputs a pattern (a) from a pattern memory 2 and outputs an input pattern (a) to a test pin 7 referring a pin attribute memory 3. When a test command in the pattern memory 2 directs an output value to be compared or a clock to be applied, this pattern generating section inverts and outputs the input pattern (a) for a fixed time immediately before the comparison or the application of a clock. A comparison section 5 inputs an expected value pattern (b) from the pattern memory 2 to take in an output value of a circuit 8 to be tested through a tester pin 7 and compares the output value of the circuit 8 being tested with the expected value pattern (b) by synchronizing a timing signal of timing control section 6, thereby judging the acceptance or rejection of the circuit 8 being tested.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a logic circuit tester.

[Conventional technology]

Conventionally, there is a test method using a scan canvas as a test method for logic circuits. Such a technique is described, for example, in Information Processing Society of Japan, "CAD for Logic Devices", Chapters 4 and 5, pages 79-82, Ohm Shoten, 556).

In this test method, first, the register is set to scan mode and operates as a shift register, and an input pattern is serially applied to the register.Then, the register is set to normal mode and a clock is applied, and then the register is set to scan mode again and the register is operated as a shift register. Logic circuits were tested using the procedure of operating the circuit as a register, serially reading out the values stored in the register, and testing.

[Problem that the invention seeks to solve]

In the conventional logic circuit testing method using the scan path described above, the scanning operation on the test machine takes time, so
Furthermore, since failure detection is primarily considered, there is a problem in that it is not possible to sufficiently test the timing from an input change to clock application or the delay time from an input change to an output change.

[Means for solving problems]

The logic circuit tester of the present invention includes a pattern memory that stores test patterns and test commands, a pin attribute memory that specifies an inverted input pin, and a test command in the pattern memory that compares output values or applies a clock. At the time of a command, immediately before comparing the output value or applying a clock, generate a pattern that is an inversion of the test pattern in the pattern memory for a certain period of time for the input pin that is an inverted input pin in the pin attribute memory. Department and
The test circuit is equipped with a comparison section that compares the output value of the circuit under test with the expected value pattern in the pattern memory, and a timing control section that controls the timing of pattern inversion, comparison, and clock application.

[For production]

In the present invention, the pattern of a specific input terminal is inverted immediately before applying the tarock and immediately before comparing the expected output values.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing the main parts of an embodiment of the logic circuit tester of the present invention.

In the figure, 1 is a logic circuit tester, which includes a pattern memory 2 that stores test patterns and test commands, and a pin attribute memory 3 that specifies inverted input bins.
Then, a pattern generation unit inputs a test pattern and a test command from the pattern memory 2, refers to the bin attribute memory 3, and generates a pattern to be output to each tester pin 7 connected to the circuit under test 8, that is, a pattern generator in the pattern memory 2. When the test command is a command that compares output values or applies a clock, immediately before comparing the output values or applying a clock, the pattern memory 2 stores a certain period of time for the input pin that is an inverted input pin in the bin attribute memory 3. a pattern generator 4 that generates a pattern that is an inversion of the test pattern in the test pattern; a comparison unit 5 that compares the output value of the circuit under test 8 with the expected value pattern in the pattern memory 2; and timing of pattern inversion, comparison, and clock application. and a timing control section 6 that controls the timing control section 6.

The pattern memory 2 stores an input pattern, an expected value pattern b, and a test command C. Also,
The bin attribute memory 3 stores input pin, output pin,
Information such as clock pins is stored. Here, regarding the input pin, information specifying whether the input pattern is to be inverted or not is further stored.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, the pattern generating section 4 inputs the input pattern a from the pattern memory 2, refers to the pin attribute memory 3, and outputs the input pattern a to the tester pin T defined as an input pin. Further, this pattern generating section 4 inverts and outputs the input pattern a for a certain period of time according to a timing signal from a timing control section 6 to an input pin designated as an inversion input pin.

The comparator 5 inputs the expected value pattern b from the pattern memory 2, takes in the output value of the circuit under test 8 through the tester pin 7, and compares the output value and expected value of the circuit under test 8 in synchronization with the timing signal of the timing controller 6. The patterns b are compared to determine whether the circuit under test 8 is good or bad.

The timing control section 6 inputs the test command C from the pattern memory 2, analyzes it, and generates a timing signal for controlling the pattern generation section 4 and comparison section 5. In addition, when test command C is a command that compares output values or applies a clock, immediately before comparing output values or applying a clock, a certain period of time is applied to the input pin specified as an inverted input pin in the pin attribute memory 3. Generates an inversion timing signal for inverting input pattern a.

Further, when the test command C is a command for comparing output values, a comparison timing signal for comparing the output value of the circuit under test 8 and the expected value pattern b is generated.

Next, a mechanism for inverting the input pattern in the pattern generating section 4 will be explained in detail with reference to FIG.

FIG. 2 is a diagram showing a partial circuit for one tester pin in a sister example of the pattern generating section 4 of FIG. 1. This pattern generating section 4 includes an AND gate 4□ which receives an inversion designation signal d and an inversion timing signal e, and an exclusive OR circuit 4 which receives an output of this AND gate 41 and an input pattern. and this exclusive OR circuit 4. It is composed of an output driver 48 which receives the output of . here,
The inversion designation signal d is a signal coming from the pin attribute memory 3, and is “1” for the input pin designated as the inversion input pin.
", and becomes "0" for other pins. Also, the inverted timing signal e is a signal coming from the timing control section 6,
The period when the input pattern is inverted is "1", otherwise it is "0'°".

And gate 4□ outputs "1" when inversion designation signal d is "1" and inversion timing signal 6 is "1", and at this time, the output of exclusive OR circuit 4 A signal that is the inversion of pattern a is output.Otherwise, the output of AND gate 4□ is "O", and the input pattern a is output as is to the output of exclusive OR circuit 4. .

Therefore, for the input pin designated as an inverted input pin in the pin attribute memory 3, the inverted timing signal e is “
Input pattern a is inverted and output only during the period when it is 1", and at other times, and for input pins other than the input pins designated as inversion pins, input pattern a is output as '1'. Then, the output driver 4 converts the output "0" and "1" of the exclusive OR circuit 4 into the input voltage level of the circuit under test 8.

Next, the effect of inverting and outputting an input pattern will be explained using the drawings.

FIG. 3 is a diagram showing waveforms when the input pattern is not inverted, where (a) shows the waveform of data input a applied to the circuit under test 8, and (b) shows the waveform of the clock input, (C )
shows each waveform of the comparison timing signal. If the input pattern shown in Figure 3 of Jin is not inverted, data is set (scanned) in a scan register (not shown), the output values are compared, and a clock is applied to register the scan register. (readout/scanout). This is sufficient if the purpose is to detect faults, but since the time from input data change to output value comparison and clock application is long, circuit delay time and register setup time It is not possible to measure the AC characteristics of

On the other hand, FIG. 4 is a diagram showing the waveform when the input pattern is inverted using the logic circuit tester according to the present invention.
(a) shows the waveform of the inversion timing test.
, (b) shows the inverting input, (C) shows the non-inverting input, (d) shows the clock input, and (e) shows the waveforms of the comparison timing signal.

As is clear from FIG. 4, the inversion timing signal (,) becomes "work" immediately before the comparison of the output values is performed, that is, immediately before the pulse of the comparison timing signal (e) is output, and during that time the inversion input 6) waveform is inverted.

As a result, the output values are compared immediately after the input of the circuit under test 8 changes, so the time t1 from when the inverted input (b) returns to its original state until the pulse of the comparison timing signal (,) is output is adjusted. By doing so, the circuit under test 80 input terminal -
It is possible to accurately measure the delay time between output terminals.

Furthermore, the inversion timing signal (a) is set to "1" immediately before the clock is applied, and the waveform of the inversion input (b) is inverted during that time. As a result, the clock is applied immediately after the input of the circuit under test 8 changes, so it is necessary to adjust the time T from when the inverted input (b) returns to its original state until the pulse of the clock input (d) is output. Accordingly, the setup time between the input terminal and the register of the circuit under test 8 can be measured with high accuracy.

Further, by setting only the input whose timing is to be tested as an inverting input and setting the other input pins as non-inverting inputs, it is possible to easily perform a timing test on a specific pin. Furthermore, by changing the pin designated as an inverted input in the pin attribute memory 30 without changing the pattern memory 2 shown in FIG. 1, timing tests can be performed on all input pins using the same test pattern.

〔Effect of the invention〕

As described above, according to the present invention, by inverting a specific input terminal pattern immediately before applying a clock and immediately before comparing expected output values, a test pattern for the purpose of failure detection is used to This has the advantage that the delay time between output terminals and the setup time between input terminals and registers can be measured with high precision. In addition, by setting only the input for which the timing test is to be performed as an inverting input and setting the other input bins as non-inverting inputs, it is possible to easily perform a timing test on a specific bin.
This is extremely effective in that it can be shown that timing tests for all input bins can be performed using the same test pattern by changing the bin designated as the inverted input in the bin attribute memory without changing the pattern memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a main part of an example of a logic circuit tester of the present invention, FIG. 2 is a circuit diagram showing a partial circuit for one tester bin in the embodiment of the pattern generation section of FIG. 1, FIG. 3 is a diagram showing waveforms when the input pattern is not inverted, and FIG. 4 is a diagram showing waveforms when the input pattern is inverted. 1...Logic circuit tester, 2...Pattern memory,
3...Bin attribute memory, 4...Pattern generation section,
5... Comparison section, 6... Timing control section, T.
...Test turbine, 8...Circuit under test.

Claims (1)

[Claims] A pattern memory that stores test patterns and test commands, a pin attribute memory that specifies an inverted input pin, and a test command in the pattern memory that compares output values or applies a clock when the test command is a command that compares output values or applies a clock. A pattern generation section that generates a pattern that is an inversion of the test pattern in the pattern memory for a certain period of time for an input pin that is an inverted input pin in the pin attribute memory immediately before applying a clock, and an output value of the circuit under test. A logic circuit tester comprising: a comparison section for comparing the expected value pattern in the pattern memory; and a timing control section for controlling the timing of pattern inversion and comparison and clock application.