JP3340459B2 - Signal determination device and signal determination method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal judging device and a signal judging device.
More particularly, the present invention relates to a signal determination device and a signal determination method for determining whether an output signal of a device under test is correct.

When an LSI (eg, a logic IC) is taken as a device under test, the LSI is tested by an LSI tester, that is, in the LSI tester,
It is determined whether the output signal from the LSI is correct. However, in the conventional LSI tester, only one of the "H" level and the "L" level of the output signal from the LSI can be determined within one cycle of the determination. Output signal is “L”
If the level changes from the “H” level to the “H” level or from the “H” level to the “L” level, an accurate determination cannot be made.

Therefore, there is a demand for a determination apparatus which can solve the above-mentioned problem and can determine the “L” level and the “H” level of the output signal from the LSI within one cycle of the determination.

[0004]

2. Description of the Related Art FIG. 4 shows a use state of a determination device. Reference numeral 10 denotes a determination device to which an output signal OUT from the LSI under test 12 is supplied. Then, the determination device 10 determines whether the output signal OUT is correct based on the expected value signal 14 and the strobe signal 16, and outputs a FAIL signal 18.

Next, the configuration of the determination device will be described using the block circuit of the LSI tester shown in FIG. In FIG. 5, the pattern generator 20 supplies an expected value 22 of “L” level or “H” level to a comparison circuit 24.
When the pattern generator 20 supplies the input pattern 26 to the waveform generator 28, the waveform generator 28
0 is supplied to the driver 32. The comparison circuit 24
The waveform generator 28 can be timed by timing signals 36 and 38 from a timing generator 34, respectively.

The driver 32 has an input level source 40
Supplies the input levels V _1L and V _1H , and the signal from the driver 32 is applied to the input of the DUT 46. The output signal of the DUT 46 is
And 44 are supplied to one input terminal. The other input terminals of the comparators 42 and 44 are supplied with reference levels V _0L and V _0H from a reference level source 48, respectively. In addition, the circuit 50 enclosed by the dashed line
Are referred to as pin electronics.

The signals 52 and 54 from the comparators 42 and 44 are supplied to a comparison circuit 24,
4 compares the signals 52 and 54 with the expected value 22 to determine whether or not the comparison result is correct.

Next, FIG. 6 shows a conventional judging device. First, a configuration of a conventional determination device will be described with reference to FIG. Output signal OUT from DUT 60
Is supplied to the + input terminals of the comparators 62 and 64. The reference level V _0H is supplied to the _negative input terminal of the comparator 62, and the reference level V _0L is supplied to the _negative input terminal of the comparator 64. Comparator 6
After being inverted, the output from 2 is supplied to the AND gate 66, and the output from the comparator 64 is supplied to the AND gate 68 as it is. The AND gates 66 and 68 are further supplied with a strobe 70, and the AND gate 66 is supplied with the expected value signal 72 as it is, and the AND gate 68 is supplied with the expected value signal 72 by an inverter (inverting circuit). ) Supplied after being inverted at 74. The output from the AND gates 66 and 68 is
, And a FAIL signal 78 is output from the OR gate 76.

Hereinafter, the operation of the above-described conventional determination device will be described with reference to timing charts of FIGS. 6 (B) and 6 (C). First, FIG. 6B shows that the output signal OUT is “H”.
The case where the level is determined is shown. Incidentally, one cycle of determination, corresponds to a time period t ₁ ~t _6. Also, from time t _{1 to} t ₆ , the expected value signal 72 is always at “H” level.
Is at "L" level. As a result, the output of AND gate 68, that is, point B 'is always at "L" level. Therefore, the comparator 62 and the AND gate 66 will be described below.

At times t _{1 to} t ₃ and t _{5 to} t ₆ ,
The output signal OUT is at “L” level, and the reference level V
_0H , the output from the comparator 62, that is, the point A is at the “H” level.
Is at "H" level. Further, since the expected value signal 72 is at "H" level, the second input to the AND gate 66 is at "H" level. However, since strobe 70 is at "L" level, the third input to AND gate 66 is always at "L" level. Therefore, the output from AND gate 66, that is, point A 'is at "L" level, and FAIL signal 78 is always at "L" level.

Therefore, the determination of the output signal OUT is not made at the times t _{1 to} t ₃ and t _{5 to} t ₆ . Next, time t
In ₃ ~t _5, the output signal OUT is "H" level is higher than the reference level V _0H, output or point A from the comparator 62 is "L" level, the first input of the AND gate 66 Is at the “L” level. Also,
Since the expected value signal 72 is at "H" level, the second input to the AND gate 66 is at "H" level. here,
Considering the time t ₄ , the strobe 70 is at the “H” level, and the third input to the AND gate 66 is “H”.
Level. Therefore, the output from AND gate 66, that is, point A 'is at "L" level, and FAIL signal 7
8 is the “L” level.

However, at time t ₄ , the output signal O
When the UT takes an abnormal state, that is, is at the "L" level, all three inputs to the AND gate 66 are at the "H" level, and the output from the AND gate 66, that is, the point A 'is at the "H" level. Becomes As a result, the FAIL signal 7
8 becomes "H" level, and the abnormality of the output signal OUT is determined.

Therefore, at time t ₄ , the FAIL signal 7
By looking at 8, it is possible to determine whether or not the output signal OUT is correctly at the “H” level. Next, FIG. 6C illustrates a case where it is determined that the output signal OUT is at the “L” level. In this case, since the expected value signal 72 is always at the “L” level, the AND gate 66
, The point A 'is always at the "L" level. Also, 'Considering point, at time t ₁ ~t ₃ and t ₅ ~t _6, since the strobe 70 is at "L" level, B' output or B of the AND gate 68 points always "L"
Is a level, at time t ₄ of time t ₃ ~t _5,
Since the strobe 70 is at "H" level, the output signal O
UT determination is possible. That is, at time t ₄ , if output signal OUT is correctly at “L” level,
Although the point B 'is at the "L" level, when the output signal OUT is in an abnormal state, that is, at the "H" level, all three inputs of the AND gate 68 are at the "H" level.
The point B 'becomes "H" level. As a result, the FAIL signal 78 becomes "H" level, so that the abnormality of the output signal OUT is determined.

Therefore, at time t ₄ , the FAIL signal 7
By looking at 8, it is possible to determine whether or not the output signal OUT is correctly at the “L” level. As described above, according to the conventional determination device of FIG. 6, it is possible to determine whether the output signal is correctly at the “H” level or the “L” level.

[0015]

In the above-described conventional determination device, only one of the "H" level and the "L" level of the output signal can be determined, and the output signal changes from the "L" level to the "H" level. When the level changes to “L” level or from “H” level to “L” level, accurate determination cannot be performed. Hereinafter, this point will be described.

Referring to the timing chart of FIG. 6B, at time t ₄ , it can be determined whether or not the output signal OUT is at the correct “H” level. For example, of the times t _{1 to} t ₃ , At time t ₂ , output signal O
It is not possible to determine whether the UT is correctly at the "L" level. For this reason, the output signal OUT becomes the time t.
_{Even in the} abnormal case where the signal always takes the “H” level from _{1 to} t ₆ , the FAIL signal 78 is at the “L” level, and as a result, an erroneous determination that the output signal OUT is correct is made.

Similarly, referring to the timing chart of FIG. 6C, at time t ₄ , the output signal OUT
It can be determined whether or not taking proper "L" level, for example in a time t ₂ of time t ₁ ~t _3, to determine whether the output signal OUT is taken correctly "H" level Can not. Therefore, the output signal OUT
There even when abnormal take always "L" level at t ₁ ~t ₆ times, FAIL signal 78 is "L" level, as a result, it a determination is made to incorrectly that the output signal OUT is correct I will.

[0018] In order to solve the above problems, in one cycle in other words the time t ₁ ~t ₆ of the judgment, the expected value signal 72 is shifted to "H" level and "L" level both level time It is possible to take. However, in this case, the number of bits required for expressing the level of the expected value signal 72 increases, resulting in an increase in the data amount. As a result,
There is a disadvantage that the determination device becomes large and expensive.

Therefore, an object of the present invention is to provide an expected value signal for judgment.
Issue is at either the first or second level
Simple configuration signal Trial of which can determine the first level and second level of the output signal within a period which is at the level of waiting value
It is an object of the present invention to provide an apparatus and a signal determination method .

[0020]

According to a first aspect of the present invention, an output signal of a DUT which is a device under test is determined.
Strobe generation circuit that generates the strobe signal of
A selection circuit and the strobe signal and the output signal.
Indicates the level of the expected value of the first level or the second level
A determination circuit for determining the output signal based on an expected value signal
And the AND gate, which is
The strobe generating circuit is configured to output a first signal of the output signal.
A first strobe signal, which is a first strobe signal for determining a bell,
To determine the trobe and the second level of the output signal
A second strobe signal, which is a second strobe signal of
The expected value signal is either the first level or the second level
Stagger the time within the expected period, which is the level of one of the expected values.
To be formed . The invention according to claim 2 is
The first or second level of the output signal of the device under test
The expected value signal indicating the level of the expected value of the
The level of the expected value of one of the second levels
A first strobe signal generated within a period and the expected value signal;
Judge the first level of the output signal of the device under test based on the signal
And the expected value signal corresponds to the first level or the second level.
Within the period that is the level of one of the expected values
The second strobe signal generated at a different time from the first strobe signal
A test element based on a lobe signal and the expected value signal;
The second level of the output signal is determined based on the result of the determination.
And outputting a determination result signal .

[0021]

According to the present invention, the first strobe (86) for judging the first level and the second strobe (88) for judging the second level are shifted in time within one cycle of the judgment. (80, 82), and the determination circuit (80, 82) outputs the first signal of the output signal (OUT) based on the first strobe (86) and the second strobe (88). Determine the level and the second level.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a determination device according to an embodiment of the present invention.

First, the configuration of a determination device according to an embodiment of the present invention will be described with reference to FIG. The output signal OUT from the DUT 60 is supplied to the + input terminals of the comparators 62 and 64. The reference level V _0H is supplied to the _negative input terminal of the comparator 62, and the reference level V _0L is supplied to the _negative input terminal of the comparator 64.
The output from the comparator 62 is supplied to one input terminal of the AND gate 80 after being inverted, and the output from the comparator 64 is supplied to one input terminal of the AND gate 82 as it is.

Reference numeral 84 denotes a selection circuit. The selection circuit 84 includes an expected value signal 72, a first strobe 86, and
The second strobe 88 is received, and the H strobe 90 is supplied to the other input terminal of the AND gate 80, and the L strobe 92 is supplied to the other input terminal of the AND gate 82. The output of the AND gate 80 and the output of the AND gate 82 are supplied to the OR gate 76, and the FAIL signal 78 is output from the OR gate 76. The first strobe 86 and the second strobe 88 are generated by a strobe generating circuit (not shown) with a time lag within one cycle of the determination.

FIG. 2 shows the structure of the selection circuit 84. In FIG. 2, the expected value signal 72 is
After being inverted by the inverter 94, it is supplied to one input terminal of the AND gate 96, and, as it is, one input terminal of the AND gate 98 and the AND gate 10.
0 is supplied to one input terminal of the
After being inverted by 2, it is supplied to one input terminal of the AND gate 104. The first strobe 86 is supplied to the other input terminal of the AND gate 96 and the other input terminal of the AND gate 100, and the second strobe 88 is connected to the other input terminal of the AND gate 98 and the AND gate 10.
4 is supplied to the other input terminal. Then, the outputs of the AND gates 96 and 98 are supplied to the OR gate 106,
The L strobe 92 is output from the OR gate 106, and the output from the AND gates 100 and 104 is supplied to the OR gate 108, and the OR gate 1
08, the H strobe 90 is output.

Hereinafter, the operation of the determination device will be described with reference to timing charts of FIGS. 1 (B) and 1 (C). First, FIG. 1B illustrates a case where it is determined that the output signal OUT changes from “L” level to “H” level. Incidentally, one cycle of the determination corresponds to the time period t ₁ ~t _6. Further, from time t _{1 to} t ₆ , the expected value signal 72 is
It is always at "H" level.

Consider the times t _{1 to} t ₃ . In FIG. 2, since the expected value signal 72 is at "H" level, the AND gates 98 and 100 are in the ON state and the AND gates 96 and 104 are in the ON impossible state. Here, from time t _{1 to} t ₃ , the first strobe 86 is at the “L” level, so that the output of the AND gate 100 is at the “L” level. Therefore, the outputs of AND gates 100 and 104 are at "L" level, and H strobe 90 from OR gate 108 is at "L" level. As a result, the selection circuit 8
Since the H strobe 90 from 4 is always at the "L" level, the AND gate 80 is in the non-ON state, that is, the output of the AND gate 80, that is, the point A 'is always at the "L" level. Therefore, hereinafter, the comparator 64
And the AND gate 82 will be described.

At time t _{1 to} t ₃ , the output signal OU
Since T is at the “L” level and lower than the reference level V _0L , the output from the comparator 64, that is, the point B is “L”.
Level, and one input terminal of the AND gate 82 is at the “L” level. Here, considering time t ₂ , the second strobe 88 is at “H” level, and
Since the expected value signal 72 is at “H” level, the selection circuit 8
4, the output of the AND gate 98 is at "H" level,
As a result, L strobe 92 is at "H" level, and the other input terminal of AND gate 82 is at "H" level. Therefore, the output from AND gate 82, that is, point B 'is at "L" level, and FAIL signal 78 is at "L" level.

However, at time t ₂ , the output signal O
When the UT takes an abnormal state, that is, is at the "H" level, all the two inputs of the AND gate 82 are at the "H" level, and the output from the AND gate 82, that is, the point B 'is at the "H" level. Become. As a result, the FAIL signal 78 becomes "H" level, and the abnormal state of the output signal OUT is determined.

Therefore, at time t ₂ , the FAIL signal 7
By looking at 8, it is possible to determine whether or not the output signal OUT is correctly at the “L” level. Next, consider the time t ₃ ~t _5. In FIG. 2, since the expected value signal 72 is at the “H” level, the AND gates 98 and 100 are in the ON state and the AND gate 9
Reference numerals 6 and 104 are in an on-disable state. Here, the time t ₃ ~
In t _5, since the second strobe 88 is the "L" level, the output of the AND gate 98 is "L" level. Therefore, the outputs of AND gates 96 and 98 are at "L" level, and L strobe 92 from OR gate 106 is at "L" level. As a result, L from the selection circuit 84
Since strobe 92 is always at the "L" level, AND gate 82 is in the non-ON state, that is, the output of AND gate 82, that is, point B 'is always at the "L" level. Therefore, the comparator 62 and the AND gate 80 will be described below.

At time t _{3 to} t ₅ , the output signal OUT
Is the “H” level, which is higher than the reference level V _0H ,
The output from the comparator 62, that is, the point A is at the "L" level, and one input terminal of the AND gate 80 is at the "L" level.
Level. Here, considering the time t ₄ , the first strobe 86 is at the “H” level and the expected value signal 72 is at the “H” level, so that the output of the AND gate 100 in the selection circuit 84 is “H”. As a result, the H strobe 90 is at the "H" level, and the other input terminal of the AND gate 80 is at the "H" level. Therefore, the output from AND gate 80, that is, point A 'is at "L" level, and FAIL signal 78 is at "L" level.

However, at time t ₄ , the output signal O
When the UT takes an abnormal state, that is, is at the "L" level, all the two inputs of the AND gate 80 are at the "H" level, so that the output from the AND gate 80, that is, the point A 'is at the "H" level. Become. As a result, the FAIL signal 78 becomes "H" level, and the abnormal state of the output signal OUT is determined.

Therefore, at time t ₄ , the FAIL signal 7
By looking at 8, it is possible to determine whether or not the output signal OUT is correctly at the “H” level. As described above with reference to FIG. 1B, according to the determination apparatus according to the embodiment of the present invention, the output signal OUT is “L”.
When the level changes from “H” level to “H” level, at time t ₂ ,
By viewing the FAIL signal 78 at t _4, the output signal O
It can be determined that the UT correctly takes the “L” level and then takes the “H” level correctly.

Next, FIG. 1C shows a case where it is determined that the output signal OUT changes from "H" level to "L" level. Incidentally, one period of determining the time t ₁ ~t ₆
Corresponding to the time. In the period from t _{1 to} t ₆ , the expected value signal 72 is always at the “L” level.

Considering times t _{1 to} t ₃ , time t
₂ , since the second strobe 88 is at the “H” level,
The AND gate 104 in the selection circuit 84 is turned on, the H strobe 90 is set to the “H” level, and as a result, the AND gate 80 is turned on. Then, based on whether the output signal OUT is correctly at the "H" level, the output from the AND gate 80, that is, the level at the point A 'changes, so that the level of the FAIL signal 78 changes. This makes it possible to determine whether or not the output signal OUT is correctly at the “H” level.

Considering the times t _{3 to} t ₅ ,
At time t ₄ , since the first strobe 86 is at “H” level, the AND gate 96 in the selection circuit 84 is turned on, and the L strobe 92 is at “H” level. It will be in the ON state. And
Since the output from the AND gate 82, that is, B ', changes based on whether the output signal OUT is correctly at the "L" level, the level of the FAIL signal 78 changes, and
By looking at the L signal 78, it can be determined whether or not the output signal OUT is correctly at the "L" level.

As described above with reference to FIG. 1C, according to the determination apparatus of the embodiment of the present invention, when the output signal OUT changes from "H" level to "L" level, by viewing the FAIL signal 78 by _2, t _4, it can be determined that the output signal OUT is taken then properly "L" level taken correctly "H" level.

As described above in detail, according to the embodiment of the present invention, one cycle of determination, that is, time t _{1 to} t _6.
, The "L" level and the "H" level of the output signal OUT can be determined.

In the above embodiment, the output signal OU
When the output signal OUT is determined when T always takes the "H" level or always takes the "L" level, the second strobe 88 is disabled using the real-time control function of the LSI tester or the like. I just need.

In the above embodiment, two strobes, the first strobe 86 and the second strobe 88, are used. However, the number of strobes is not limited to two.
Three or more are possible. As described above, when three or more strobes are set, the “H” level is obtained at three or more locations,
It is possible to determine the “L” level. Then, in FIG. 3, a timing chart of the determination apparatus according to another embodiment of the present invention have been shown, at time t _3, t _5, the first
The output signal OUT is obtained by the strobe and the second strobe.
Is determined at time t ₂ and time t ₄ .
The output signal OUT is obtained by the strobe and the fourth strobe.
Is determined at the “L” level. As described above, in the embodiment of FIG. 3, by setting four strobes, it is possible to determine the level at two “H” levels and two “L” levels, that is, a total of four levels.

[0041]

As described above, according to the present invention,
Since a plurality of strobes are determined in one cycle of the determination, the first configuration of the output signal is performed in one cycle of the determination with a simple configuration.
A level and a second level can be determined.

[Brief description of the drawings]

FIG. 1 shows a determination device according to an embodiment of the present invention, and (A)
FIG. 3B is a diagram illustrating the configuration, FIG. 4B is a timing chart showing a case where a change from “L” level to “H” level is determined, and FIG. FIG. 6 is a timing chart showing a case where the determination is made.

FIG. 2 is an explanatory diagram of a configuration of a selection circuit in the determination device of FIG.

FIG. 3 is a timing chart of a determination device according to another embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a use state of the determination device.

FIG. 5 is a block circuit diagram of an LSI tester.

FIGS. 6A and 6B show a conventional judging device, FIG. 6A is an explanatory diagram of the configuration, FIG. 6B is a timing chart showing a case of judging an “H” level, and FIG. FIG. 6 is a timing chart illustrating a case of determination.

[Explanation of symbols]

 60 DUT 62, 64 Comparator 72 Expected value signal 76 OR gate 78 FAIL signal 80, 82 AND gate 84 Selection circuit 86 First strobe 88 Second strobe 90 H strobe 92 L strobe OUT Output signal

Claims (2)

(57) [Claims] A strobe generating circuit for generating a strobe signal for determining an output signal of a device under test; and a first level in the strobe signal and the output signal.
A determination circuit for determining the output signal based on an expected value signal indicating a level of the expected value of the second or second level , wherein the strobe generation circuit determines a first level of the output signal. The expected value signal includes a first strobe signal for determining and a second strobe signal for determining a second level of the output signal.
Level of the expected value of either the first level or the second level
A signal judging device characterized in that the signals are generated at different times within a certain period . 2. A first level in an output signal of a device under test.
Or the expected value signal indicating the level of the expected value of the second level
Expected value of either the first level or the second level
First strobe signal 及 occurring within a level period
And determining a first level of the output signal of the device under test based on the expected value signal , and determining whether the expected value signal is the first level or the second level.
A second level of an output signal of the test element is determined based on a second strobe signal generated at a time different from the first strobe signal within a period that is one of the expected value levels and the expected value signal. Outputting a determination result signal based on the result of the determination.