JP3061650B2 - Generated pulse monitor circuit of IC tester - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester, and more particularly, to a test strobe (hereinafter referred to as "strobe") for determining a timing for judging an output result of a device under test (DUT) such as an IC memory or a logic IC. The present invention relates to an improvement of a monitor circuit capable of monitoring with a simple circuit.

[0002]

2. Description of the Related Art An IC tester obtains data on the electrical characteristics and performance of a DUT by comparing the output result of the DUT with an expected value. The expected value is provided by the pattern generator, and the maximum number of input / output (I / O) measurable DUTs is determined by the number of outputs. The output of the DUT is
Normally, the data is input to an analog comparator, the output of the analog comparator is received by a digital converter, the data input to the digital comparator is collected at the timing of strobe occurrence, and the data is stored as a determination result in a failure analysis memory or the like. Therefore, the judgment result, the timing of the generation of the strobe, and the presence or absence thereof have an important influence on the judgment result. Therefore, it is necessary to monitor the state of whether or not the strobe is correctly output to ensure the reliability of the determination result.

[0003]

The area for determining the output of the conventional DUT can be up to about two cycles for a test cycle, and the output determination interval is 20 ns.
It is about. Therefore, the monitor area of the strobe is adopted in accordance with this condition. However, in recent years, as the operation speed of the IC has been improved, there has been a demand for a device capable of setting the interval in two cycles to the limit of 0 ns.
For example, in a high-speed test for read timing of an SRAM or the like, as shown in FIG. 4, the test cycle spans two cycles, and the strobe generation timing in the second cycle is narrower than 20 ns and has high accuracy. Are required.

By the way, the strobe generation timing of the tester can be made shorter and more accurate by adjusting the rate pulse serving as the reference clock at a high speed and adjusting it by a minute delay circuit. Therefore, it is possible to provide the same adjustment circuit on the monitor side in order to monitor it. However, this not only complicates a monitor circuit for simply monitoring whether or not a strobe is occurring, but also makes the circuit expensive and requires adjustment with the strobe generating side.

SUMMARY OF THE INVENTION The present invention addresses the above-mentioned problems of the prior art and the above-mentioned demands. An IC which can monitor a high-speed strobe with a short time interval using a simple circuit even if it generates a high-speed strobe. It is an object to provide a tester generated pulse monitor circuit.

[0006]

According to the present invention, there is provided a timing generating circuit for monitoring generation of a timing pulse generated at a predetermined phase with respect to a periodically generated reference pulse. A first distribution circuit that receives a reference pulse and distributes each reference pulse in a cycle of n cycles (n is an integer of 2 or more), and a reference pulse distributed by the first distribution circuit. And n registers for receiving and storing the logic level state of the pulse, and receiving the timing pulse, distributing each timing pulse in n cycles, and distributing the timing pulse corresponding to the distribution of the first distribution circuit. A second distribution circuit for clearing the information stored in the register with the distributed timing pulse, and a register at a timing after the generation of the distributed timing pulse State of the stored logic level is one that comprises a detection circuit for detecting whether or not cleared.

[0007]

In this manner, the generation of the timing pulse is distributed in units of a plurality of cycles of the reference pulse, the data is set in the register according to the distribution reference pulse, and the set data is reset on the timing pulse side. Therefore, whether or not a timing pulse has been generated can be monitored regardless of the timing pulse generation phase. Also, the timing pulse is a strobe,
If it is over two cycles, it is sufficient to monitor the value of the register for the occurrence of the strobe corresponding to that cycle. In addition, since the n-cycle distribution is used, even if the timing pulse is high-speed, low-speed monitoring according to the number of distributions is sufficient, and a monitor circuit can be realized with a simple circuit.

[0008]

FIG. 1 is a block diagram of a strobe monitor circuit of an IC tester according to the present invention, FIG. 2 is a block diagram mainly showing a determination circuit system of the IC tester, and FIG. It is a timing chart of operation.

In FIG. 2, 1 is a timing generator, 2
Is a strobe selection circuit, 3 is a digital comparator, 4
Is an analog comparator, and 5 is a DUT. This figure shows only one output system of the DUT 5, and in actuality, an analog comparator 4 and a digital comparator 3 corresponding to the number of outputs of the DUT 5 are provided. Is omitted.

Here, the value of the output of the digital comparator 3 is output to the fail analysis memory 6 at the timing of generation of the strobe ST from the strobe circuit 2, and the result of the determination is stored in a predetermined address assigned in advance. Is done. The strobe selection circuit 2 outputs a large number of strobes ST ₁ , ST ₂ ,.
STn, one of which is the pattern generator 1
(Or the test processor 10). The selected strobe is input to the digital comparator 3 and a strobe monitor circuit 8 described later.

The strobe monitor circuit 8 receives a rate pulse (RAT) from the timing generator 1 through the variable delay circuit 7.
E) In response to the RT, monitor whether or not the strobe ST is generated according to the rate pulse RT whose timing is adjusted by the variable delay circuit 7. The circuit configuration of the strobe monitor circuit 8 is, as shown in FIG.
2, and flip-flops (F / F) 83, 84, 85,
86, an NG detection circuit 87, and a flip-flop (F / F) 88 for storing NG data.
Then, the data of the flip-flop (F / F) 88 is taken into the test processor 10 via the tester bus 11, and the test processor 10 determines whether or not the determination is based on the output of the strobe ST. It is checked whether the measurement result is correct.

In this case, the strobe monitor circuit 8 receives the rate pulse RTi (i represents an i-th strobe by an arbitrary integer) of the timing generator 1 in the distribution circuit 81. Each time, the rate pulse RTi is sequentially distributed to the set side (S) of each of the flip-flops 83, 84, 85, 86. Similarly, a distribution circuit 82 receives a strobe STi (i represents an i-th strobe by an arbitrary integer), and thereby each flip-flop 83, 4
Strobe sequentially on the reset side (R) of 84, 85, 86
ST is distributed and output.

Each flip-flop 83, 84, 85, 8
6 are input to the NG detection circuit 87, respectively.
If at least one of the Q outputs of the flip-flops 83, 84, 85, 86 has a Q output of "1" until the next strobe pulse ST, the NG detection circuit 87 detects this. As a result, a logical value "1" is generated at the output, and the state is set to the flip-flop 88 using the rate pulse RT as a gate signal.

FIG. 3 shows the operation. The rate pulse RT from the timing generator 1 is supplied to the strobe monitor circuit 8 as a pulse train as shown in FIG. This is input to the distribution circuit 81, and as shown in (b), the rate pulse RT ₁ , the rate pulse RT ₂ , and the rate pulse RT ₃ are distributed in units of four cycles with respect to the rate pulse RT of (a). is output as rate pulse RT _4, they are inputted to the set terminal of the flip-flop 83, 84, 85, 86 corresponding to the distribution, respectively (S).

Similarly, the strobe ST selected by the strobe selection circuit 2 is given to the strobe monitor circuit 8 as a pulse train as shown in FIG. This is input to the distribution circuit 82 and, as shown in (d), the strobe ST ₁ , the strobe ST ₂ , and the strobe ST ₂ are distributed to the strobe ST of (c) in units of four cycles.
₃ is output as a strobe ST _4, the flip-flop 83,84,85,8 correspond to the distribution, respectively
6 is input to the reset terminal (R). As a result, when the strobe ST is normally generated, each flip-flop generates a Q output which is set by the rate pulse RT and reset by the strobe ST, as shown in FIG. The NG detection circuit 87 receives these outputs and detects whether or not each Q output has been reset. That is, the NG detection circuit 87 receives a Q output as shown in (e) from each of the flip-flops 83, 84, 85, 86, and determines the state of the rising edge of the rate pulse RT before being input to the distribution circuit 81. Detect at edge. In the normal state where the strobe pulse ST is normally generated at this timing,
The detection value when the Q output is a logical value “0” is
It is "0".

Normally, the Q output of the flip-flop has an operation delay with respect to the first rise of the rate pulse RT (or may have a special operation delay). The Q output is delayed, and the rising edge of each rate pulse RT is necessarily before the rising of the Q output generated as a result of its distribution. As a result, the rising edge of the rate pulse RT corresponds to the immediately preceding Q output detection state. In other words, what detects each Q output is the rate pulse RT at the next timing to the rate pulse RT related to distribution. Therefore, Q output =
The strobe pulse ST depends on whether or not “1” is generated.
It is possible to determine whether or not the error has occurred. In addition, a timing circuit such as a delay circuit, a flip-flop, or another logic circuit is provided to ensure that the detection of the Q output is performed at the rate pulse RT at the next timing or at a timing subsequent thereto. You may detect whether it is output.

In the mode extending over two cycles shown in FIG. 4, the strobe ST ₂ corresponding to the second cycle is used.
Monitors whether or not an error has occurred. Therefore, the distribution circuit 8
1 generates a 1/2 frequency divided output (see (f)) which is frequency-divided in accordance with the falling edge of the rate pulse RT,
The detection circuit 87 receives the signal, locks the detection result of the first cycle at its HIGH level (= “1”), and
Only the strobe ST in the cycle is monitored as valid.

As described above, if the n-th (n is an arbitrary integer) strobe ST does not occur, for example, the Q output of the flip-flop 83 is not reset, and is indicated by a dotted line in FIG. Thus, the Q output of the flip-flop 83 continues to be generated. As a result, the next n
The NG detection circuit 87 detects this at the (+1) th rate pulse RT, and "1" is stored in the flip-flop 88.

The detection information stored in the flip-flop 88 is information generated in connection with the generation of the strobe ST itself which must be generated in response to the rate pulse RT. Therefore, it becomes irrelevant to the generation phase of the strobe ST. Therefore, in principle, the present invention can be applied even when the phase relationship between the rate pulse RT and the strobe ST is “0”. Also, since each flip-flop is provided corresponding to the distributed strobe ST, it can be determined whether or not it has occurred corresponding to the strobe ST. It is only necessary to invalidate the judgment result.

The data of the flip-flop 88 is then transmitted to the test processor 1 via the tester bus 11.
It will be read to zero. Since many other registers corresponding to the flip-flops 88 are provided corresponding to the pins, the reading in this case, including other similar data, is transferred to the test processor 10 collectively.

As described above, in the embodiment, an example is shown in which the rate pulse RT and the strobe ST are distributed and detected in four cycles. However, the four cycles are an example, and the present invention relates to these. What is necessary is to distribute and detect a plurality of cycles as one cycle. In the embodiment, the flip-flops are provided corresponding to each of the distributed cycles. However, the flip-flops need only have a register for storing information according to each distribution.

In the embodiment, the monitoring of the strobe is described. However, the present invention is not limited to the monitoring of the strobe, and the timing pulse having a predetermined phase with respect to a reference pulse generated at a predetermined cycle is not limited to the monitoring. The present invention can also be applied to an edge monitor of a so-called timing pulse for monitoring the occurrence, for example.

[0023]

As described above, according to the present invention, the generation of the timing pulse is distributed in units of a plurality of cycles of the reference pulse, the data is set in the register according to the distribution reference pulse, and the set data is stored in the register. Since the configuration is such that reset is performed on the timing pulse side, it is possible to monitor whether or not a timing pulse has been generated regardless of the timing pulse generation phase. If the timing pulse is a strobe that extends over two cycles, it is sufficient to monitor the value of the register for the generation of the strobe corresponding to that cycle. In addition, since n-cycle distribution is used, low-speed monitoring according to the number of distributions is sufficient even if the timing pulse is high. As a result, a monitor circuit can be used with a simple circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a strobe monitor circuit of an IC tester according to the present invention.

FIG. 2 is a block diagram mainly showing a determination circuit system of the IC tester.

FIG. 3 is a timing chart of the operation of the strobe monitor circuit.

FIG. 4 is a timing chart of a determination process in a high-speed test for read timing of an SRAM or the like;

[Explanation of symbols]

1: timing generator, 2: strobe selection circuit, 3:
Digital comparator, 4 ... Analog comparator, 5
... DUT (device under test), 6 ... fail analysis memory, 7 ... variable delay circuit, 8 ... strobe monitor circuit, 10 ... test processor, 11 ... tester bus, 81,
82: distribution circuit, 83, 84, 85, 86, 88: flip-flop, 8
7 ... NG detection circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28 G01R 31/3183 G06F 1/04 301 G06F 1/04 302 G11C 29/00 659

Claims (2)

(57) [Claims] 1. A circuit for monitoring the generation of a timing pulse generated at a predetermined phase with respect to a periodically generated reference pulse. ), A first distribution circuit for distributing each reference pulse in one cycle, n registers for respectively receiving the reference pulses distributed by the first distribution circuit and storing a logic level state of the pulse, and the timing pulse And distributing each timing pulse with n cycles as one cycle, and clearing the storage information of the register at the distribution position corresponding to the distribution of the first distribution circuit with the distributed timing pulse. A circuit for determining whether or not the state of the logic level stored in the register has been cleared at a timing after the occurrence of the distributed timing pulse; A pulse monitor circuit for an IC tester, comprising: a detection circuit for detecting the pulse. 2. The method according to claim 1, wherein the timing pulse is a decision strobe sent to a digital decision circuit, and the register is a flip-flop.
Generated pulse monitor circuit of C tester.