JPH04269676A - Generated pulse monitor circuit for ic tester - Google Patents

Abstract

PURPOSE:To obtain an IC tester provided with a monitor circuit capable of monitoring a strobe with a simple circuit even if it is generated in short time intervals and at high speed. CONSTITUTION:Since the circuit is so constituted as to distribute the generated timing pulse for the unit of plurality of reference pulse cycles, to set the data at a register in accordance with the distributed reference pulse and to reset the set data on the timing pulse side, it can be monitored whether or not the timing pulse is generated regardless of the timing pulse generation phase. As for a timing pulse which is strobe and crosses over more than two cycles, it is enough to monitor the registered value regarding the generation of strobe corresponding to the cycle. Moreover, owing to the n cycle distribution, low speed monitoring in accordance with the distribution number is enough even for a high speed timing pulse.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an IC tester, and more specifically, the present invention relates to an IC tester. The present invention relates to an improvement of a monitor circuit that can be monitored using a circuit that can be used for monitoring.

0002

2. Description of the Related Art An IC tester obtains data regarding the electrical characteristics and performance of a DUT by comparing the output results of the DUT with expected values. The expected value is provided from the pattern generator, and the DUT with the maximum number of measurable inputs/outputs (I/O number) is determined based on the number of outputs. The output of the DUT is
Normally, data is input to an analog comparator, the output of the analog comparator is received by a digital converter, the data input to the digital comparator is collected at the timing of strobe generation, and is stored in a fail analysis memory or the like as a determination result. Therefore, the determination result, the timing of strobe generation, and the presence or absence of the strobe have an important influence on the determination result. Therefore, it is necessary to monitor the status of whether the strobe is being output correctly to ensure the reliability of the determination result.

0003

[Problems to be Solved by the Invention] The conventional DUT output judgment range is up to about 2 cycles for test cycles, and the output judgment interval is 20 ns.
That's about it. Therefore, the strobe monitor area is also designed to meet this condition. However, in recent years, as the operating speed of ICs has improved, there has been a demand for two cycles and an interval that can be set to a limit of 0 ns. For example, in a high-speed test of the read timing of SRAM, etc., as shown in Figure 4, the test cycle spans two cycles, and the strobe generation timing in the second cycle is also narrower than 20 ns, and has high accuracy. are required.

By the way, the strobe generation timing of the tester can be made more accurate with shorter timing by increasing the rate pulse serving as its reference clock and adjusting it using a minute delay circuit. Therefore, in order to monitor this, it is possible to provide the same adjustment circuit on the monitor side. However, this not only complicates the monitor circuit that simply monitors whether or not a strobe is being generated, but also makes the circuit expensive and requires coordination with the strobe generator.

The present invention has been made in response to the problems and previous demands of the prior art, and provides an IC that can monitor high-speed strobes with short time intervals using a simple circuit. The purpose of the present invention is to provide a generated pulse monitor circuit for a tester.

[0006]

[Means for Solving the Problems] A timing generation circuit of the present invention to achieve the above object is a circuit that monitors the generation of a timing pulse that occurs at a predetermined phase with respect to a periodically generated reference pulse. a first distribution circuit that receives a reference pulse and distributes each reference pulse over n cycles (n is an integer of 2 or more); and a reference pulse distributed by the first distribution circuit. n registers that receive timing pulses and store the logic level states of the pulses; a second distribution circuit that clears the information stored in the register with the distributed timing pulse; and a detection circuit that detects whether or not the logic level state stored in the register is cleared at the timing after the distributed timing pulse is generated. It is equipped with a circuit.

[0007]

[Operation] In this way, the timing pulse generation is distributed in units of multiple cycles of the reference pulse, data is set in the register according to the distributed reference pulse, and the set data is reset on the timing pulse side. Therefore, it is possible to monitor whether a timing pulse has been generated or not, regardless of the timing pulse generation phase. In addition, the timing pulse is a strobe,
If the cycle spans two cycles, it is sufficient to monitor the value of the register regarding the occurrence of the strobe corresponding to that cycle. Moreover, since n-cycle distribution is used, even if the timing pulse is high-speed, low-speed monitoring according to the number of distributions is sufficient, and a monitor circuit can be realized with a simple circuit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a strobe monitor circuit of an IC tester according to the present invention, FIG. 2 is a block diagram mainly showing a judgment circuit system of the IC tester, and FIG. 3 is a block diagram of a strobe monitor circuit of an IC tester according to the present invention. It is a timing chart of operation.

In FIG. 2, 1 is a timing generator;
is a strobe selection circuit, 3 is a digital comparator, and 4 is a strobe selection circuit.
is an analog comparator, and 5 is a DUT. This figure shows only one output system of the DUT 5, and in reality, analog comparators 4 and digital comparators 3 are provided according to the number of outputs of the DUT 5, but for convenience of explanation, these are not included. is omitted.

Here, the value of the output of the digital comparator 3 at that time is outputted to the fail analysis memory 6 at the timing of generation of the strobe ST from the strobe circuit 2, and the judgment result is stored in a predetermined address assigned in advance. be done. The strobe selection circuit 2 selects a large number of strobes ST1, ST2, . . . from the timing generator 1.
. . , STn, and selects one of them according to data set by the pattern generator 1 (or test processor 10). The selected strobe is input to a digital comparator 3 and a strobe monitor circuit 8, which will be described later.

The strobe monitor circuit 8 receives a rate pulse (RA) from the timing generator 1 via the variable delay circuit 7.
TE) monitors whether or not a strobe ST is generated in accordance with a rate pulse RT whose timing is adjusted by the variable delay circuit 7. As shown in FIG. 1, the strobe monitor circuit 8 has a circuit configuration including distribution circuits 81 and 82 and flip-flops (F/F) 83 and 8.
4, 85, 86, an NG detection circuit 87, and a flip-flop (F/F) 88 for storing NG data. Then, the data of the flip-flop (F/F) 88 is taken into the test processor 10 via the tester bus 11, and it is determined on the test processor 10 side whether or not the determination is based on the output of the strobe ST. It is confirmed whether the measurement results are correct or not.

The strobe monitor circuit 8 receives the rate pulse RTi (i is an arbitrary integer and indicates the i-th strobe) of the timing generator 1 through a distribution circuit 81, and thereby divides each pulse into one cycle of 4 cycles. The rate pulse RTi is sequentially distributed to the set side (S) of each flip-flop 83, 84, 85, 86. Similarly, a strobe STi (i is an arbitrary integer indicating the i-th strobe) is received by the distribution circuit 82, thereby
The strobe ST is sequentially distributed and outputted to the reset side (R) of each flip-flop 83, 84, 85, 86 for each pulse in one cycle.

Each flip-flop 83, 84, 85, 8
The Q outputs of 6 are each input to the NG detection circuit 87,
Among the Q outputs of each flip-flop 83, 84, 85, 86, the Q output is “1” until the next strobe pulse ST.
If there is even one of them, the NG detection circuit 87 detects this and generates a logic value of "1" at its output,
The state is set in the flip-flop 88 using the rate pulse RT as a gate signal.

FIG. 3 shows the operation. Rate pulse RT from timing generator 1 is applied to strobe monitor circuit 8 through variable delay circuit 7 as a pulse train as shown in (a). These are input to the distribution circuit 81, and as shown in (b), rate pulses RT1, rate pulses RT2, rate pulses RT3, and rate pulses are distributed to the rate pulse RT in (a) using 4 cycles as a unit of one round. RT4, and these are outputted as flip-flops 83 and 8 corresponding to the distribution, respectively.
It is input to the set terminals (S) of 4, 85, and 86.

Similarly, the strobe ST selected by the strobe selection circuit 2 is applied to the strobe monitor circuit 8 as a pulse train as shown in (c). This is input to the distribution circuit 82, and as shown in (d), it is outputted as strobe ST1, strobe ST2, strobe ST3, and strobe ST4, which are distributed to strobe ST in (c) in a unit of 4 cycles,
These are flip-flops 83 corresponding to distribution, respectively.
, 84, 85, 86 are input to the reset terminals (R). As a result, when the strobe ST is normally generated, each flip-flop generates a Q output that is set by the rate pulse RT and reset by the strobe ST, as shown in (e). The NG detection circuit 87 receives these outputs and detects whether each Q output has been reset. That is, the NG detection circuit 87 has a Q output as shown in (e) of each flip-flop 83, 84, 85,
86, and its state is detected at the rising edge of the rate pulse RT before being input to the distribution circuit 81. In a normal state in which the strobe pulse ST is normally generated at this timing, the detected value is "0" when the Q output has a logical value of "0".

Normally, the Q output of a flip-flop is delayed from the rising edge of the first rate pulse RT because there is an operational delay (or a special operational delay may be provided). The Q output generation is delayed so that the rising edge of each rate pulse RT is necessarily before the rising edge of the Q output that occurs as a result of its distribution. As a result, the rate pulse R
The rising edge of T corresponds to the detection state of the previous Q output. In other words, detecting each Q output is
This is the rate pulse RT at the next timing of the rate pulse RT related to distribution. So, until the next timing, Q
Whether or not the strobe pulse ST has been generated can be determined based on whether or not the output = "1" has been generated. In addition, in order to ensure that the Q output is detected at the next rate pulse RT or at a later timing, a timing adjustment circuit such as a delay circuit, flip-flop, or other logic circuit is provided to ensure that the Q output continues. It may also be detected whether or not it is being output.

By the way, in the mode spanning two cycles shown in FIG.
Monitor whether or not 2 has occurred. For this purpose, the distribution circuit 81 generates a 1/2 frequency divided output (see (f)) that is frequency-divided according to the falling edge of the rate pulse RT. The detection result of the 2nd cycle is locked at the HIGH level (="1") and only the strobe ST of the 2nd cycle is valid and monitored.

From the above, for example, the nth (
If the strobe ST (n is an arbitrary integer) is not generated, the Q output of the flip-flop 83 is no longer reset, and the Q output of the flip-flop 83 continues to be generated as shown by the dotted line in (e). As a result, the next n
The NG detection circuit 87 detects the +1st rate pulse RT and stores "1" in the flip-flop 88.

The detection information stored in the flip-flop 88 is information generated in connection with the generation of the strobe ST itself, which must be generated in response to the rate pulse RT. Therefore, it becomes irrelevant to the generation phase of strobe ST. Therefore, in principle, the present invention can be applied even when the phase relationship between the rate pulse RT and the strobe ST is "0". In addition, since flip-flops are provided for each distributed strobe ST, it is possible to determine whether or not a strobe ST has occurred.
Even if the generation cycle of the strobe ST extends over the next cycle, it is sufficient to simply invalidate the previous determination result.

By the way, the data in the flip-flop 88 is then sent to the test processor 1 via the tester bus 11.
It will be read to 0. Since many other registers corresponding to the flip-flop 88 are provided corresponding to the pins, the reading in this case is passed to the test processor 10 at once, including other similar data.

As described above, the embodiment shows an example in which the rate pulse RT and the strobe ST are distributed and detected in four cycles, but the four cycles are just an example, and the present invention It is sufficient that the detection is performed by distributing multiple cycles as one round. Further, in the embodiment, a flip-flop is provided corresponding to each distributed cycle, but it is sufficient if there is a register for storing information in accordance with each distribution.

Although strobe monitoring is described in the embodiments, the present invention is not limited to strobe monitoring, but the present invention is not limited to strobe monitoring. It can also be applied to edge monitoring of timing pulses, which monitors the occurrence of timing pulses.

[0023]

As described above, in this invention, the generation of timing pulses is distributed in units of multiple cycles of a reference pulse, data is set in a register according to the distributed reference pulse, and the set data is Since it is configured to be reset on the timing pulse side, it is possible to monitor whether or not a timing pulse has been generated, regardless of the timing pulse generation phase. Furthermore, if the timing pulse is a strobe and it spans two cycles, it is sufficient to monitor the value of the register regarding the occurrence of the strobe corresponding to that cycle. Furthermore, since n-cycle distribution is used, even if the timing pulse is high-speed, monitoring can be performed at a low speed corresponding to the number of distributions. As a result, a simple monitor circuit is sufficient.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a strobe monitor circuit of an IC tester according to the present invention.

FIG. 2 is a block diagram centered on the determination circuit system of the IC tester.

FIG. 3 is a timing chart of the operation of the strobe monitor circuit.

FIG. 4 is a timing chart of determination processing in a high-speed test regarding read timing of SRAM and the like.

[Explanation of symbols]

1... Timing generator, 2... Strobe selection circuit, 3...
Digital comparator, 4...Analog comparator, 5
...DUT (device under test), 6...Fail analysis memory, 7...Variable delay circuit, 8...Strobe monitor circuit, 10...Test processor, 11...Tester bus, 81,
82...Distribution circuit, 83, 84, 85, 86, 88...Flip-flop, 8
7...NG detection circuit.

Claims (2)

[Claims] 1. A circuit that monitors the generation of a timing pulse that occurs at a predetermined phase with respect to a periodically generated reference pulse, which receives the reference pulse and processes it for n cycles (n is an integer of 2 or more). ), a first distribution circuit that distributes each reference pulse in one cycle; n registers that each receive the reference pulse distributed by the first distribution circuit and store the logic level state of the pulse; and the timing pulse. and a second distribution of distributing each timing pulse using the n cycles as one round and clearing the stored information in the register at the distribution position corresponding to the distribution of the first distribution circuit with the distributed timing pulses. and a detection circuit for detecting whether or not the logic level state stored in the register is cleared at a timing after generation of the distributed timing pulse. monitor circuit. 2. The generated pulse monitor circuit for an IC tester according to claim 1, wherein the timing pulse is a judgment strobe sent to a digital judgment circuit, and the register is a flip-flop.