JPS6279377A - Self-diagnosing apparatus for timing generation circuit - Google Patents

Abstract

PURPOSE:To impart a function of detecting missed generation of a rate signal, by delaying a timing signal by one cycle with respect to the rate signal to hold a comparison output signal in comparison between the rate signal and the delayed timing signal. CONSTITUTION:A timing generation circuit 1 generates a specified cycle of rate signal Srt and a strobe clock Ssc delayed by a specified time from the signal Srt. A rate signal diagnosing circuit 6 is made up of a comparison circuit 7 using an exclusive OR gate in which the signal SRT is applied direct to one input terminal, a delay circuit 8 which provides a specified delay time T1 to a clocks Ssc to be applied to the other input terminal of the circuit 7, a pulse detection circuit 9 for detecting the rise of the signal Srt, a delay circuit 10 which gives a specified delay time T2 to an output pulse of the circuit 9 to make an enable signal Sco to applied to the circuit 7, a register 11 for holding an output signal thereof 10 and the like. Thus, a function of detecting missed generation of a rate signal can be imparted.

Description

Detailed Description of the Invention 1. Field of Industrial Application] The present invention provides self-diagnosis of a timing generation circuit that generates a rate signal with a predetermined period and at least one timing signal delayed by a predetermined time with respect to the rate signal. The present invention relates to a diagnostic device, and more specifically, to a low-cost diagnostic device that has a relatively simple circuit configuration and high reliability.

[Prior Art] For example, as shown in FIG. 3, the timing generation circuit 1 of an LSI test device uses a rate l! No. 3rt
rate signal generation circuit 2 that generates a test pair, ILS
a format clock generation circuit 3 that generates a format clock SfC that is delayed by a predetermined time with respect to a rate signal 3rt in order to set the edge timing of a test pattern applied to a test pattern I (hereinafter referred to as DUT);
A strobe clock generation circuit 4 is used which generates a strobe clock Ssc delayed by a predetermined time with respect to the rate signal 3rt in order to take in a response pattern output from a test pattern corresponding to the test pattern and compare it with an expected pattern. It is being

By the way, in such a timing generation circuit 1, as mentioned above, the rate signal Srt is different from the other timing signal 3fC.
, 33C, it is desirable to monitor whether the rate signal 3rt is normal.

Therefore, conventionally, for example, as shown in FIG. 3, a time interval counter 5 has been used to determine the repetition period +91 of the G1-signal Srt.

Problems to be solved by the invention However, according to such a conventional configuration, the rate
Occurrence of rt (unable to detect. For this reason, single-shot extension due to removal of format clock 3fc or strobe clock 3sc); there is a possibility that operation cannot be detected.

Furthermore, it is necessary to use a time interval counter 5 whose measurement resolution is equal to or higher than the repetition period of the rate signal 3rt, which complicates the circuit configuration and increases costs.

Furthermore, the reliability of such a counter 5 can only be expected to be on the same level as that of the rate generation circuit 2, considering the circuit configuration of 9 circuits, scale of 2, and resolution.

Furthermore, from the perspective of self-diagnosis, the rate signal 3r
An actual measurement value of the repetition period of t is not necessary, and it is only necessary to clarify whether or not a repetition signal of a predetermined period is being output.

The present invention has been made with attention to such points, and its purpose is to provide an r
An object of the present invention is to provide a highly reliable, low-cost timing generation circuit self-diagnosis device with a medium circuit configuration.

[Means for Solving the Problems] The present invention achieves the above object by
a timing generation circuit that generates a rate signal and at least one timing signal delayed by a predetermined time with respect to the rate signal; a delay circuit that delays the timing signal by one period with respect to the rate signal; The present invention is characterized in that it is comprised of a comparison circuit that compares the delayed timing signal and a register that holds the output signal of the comparison circuit.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention, and the same parts as in FIG. 3 are given the same reference numerals. 1st
In the figure, 6 is a rate diagnosis circuit. The rate diagnosis circuit 6 includes: 1) a comparison circuit 7 using a 1-alternative OR gate to which C818 3rt is directly applied to one input terminal;
In addition to the other input terminal of the comparator circuit 7, a delay circuit 8 provides a predetermined delay time T1 to the stroke clock 3sc, which is applied to the input terminal of the comparator circuit 7. A predetermined delay time T2 is given to the output pulse of , and +J11 is sent to the comparator circuit 7 as an enable signal @3en.ii! extension circuit 10, comparator circuit 7
It is composed of a register 11 that holds the output signal of.

Regarding the operation of the circuit constructed in this way, the second Δ~
This will be explained using the waveform diagram in Figure C.

In these figures, (a) shows the rate signal Sr[, (b) shows the strobe clock Ssc, and (C
) is the strobe clock 5 output from the R extension circuit 8.
sc-, <(1) shows the enable signal Sen, (C) shows the output signal SCO of the comparison circuit 7, and (f)
indicates the output signal SO of the register 11.

Here, the delay time T1 of the delay circuit 8 is 3sc=3rt
-T1. That is, due to the circuit configuration, the strobe clock 3sc is not output for a certain period of time (for example, 20 ns) before the rate signal Srt rises. This period is a preparation period for loading the counter, and the counter is unable to count. Therefore, this period is defined as the delay time T1. Furthermore, since such a delay time is created, for example, by a delay line, it is better to shorten it. As a result, the rate signal 3rt and the strobe clock SSC' delayed by one cycle with respect to the rate signal Srt are applied to the comparison circuit 7.

Further, the delay time T2 of the delay circuit 10 is determined by the rate signal 3r.
The rising edge of t is set to be delayed for a time longer than at least the pulse width of the rate signal Srt.

As a result, the comparator circuit 7 becomes enabled after the time T2 has elapsed since the rise of the rate signal 3rt.

FIG. 2A shows a state in which the rate signal 3rt is normally output. In this state, the rate signal 3rt and the strobe clock SSC' delayed by one cycle with respect to the rate signal 3rt are simultaneously applied to each input terminal of the comparator circuit 7, so the output signal SCO of the comparator circuit 7 is at the L level. The output signal S of register 11 is kept at
o will also be held at L level.

FIGS. 2 and 8 show an abnormal state in which the output cycle of the rate signal 3rt is different from the set value. In this state, each input terminal of the comparator circuit 7 receives the rate signal Srt and the strobe clock SS which is delayed by one period with respect to the rate signal Srt.
C' are applied at different times, so that the output signal 3c of the comparator circuit 7.

goes high at the rising edge of the rate signal Srt, and goes to the high level at the falling edge of the strobe clock 5SC-. Then, the output signal S of the register 11.

changes to H level at the rising edge of the output signal SCO of the comparison circuit 7, indicating that an abnormality has occurred in the rate signal Srt.

FIG. 2.0 shows a state in which a loop has occurred in the rate signal Srt. In this state, the output signal Sco of the comparator circuit 7 corresponds to the strobe clock 5sc- one cycle before the generation of the 1-bit signal in the rate signal Srt. Then, the output signal SO of the register 11 is transmitted to the comparator circuit 7.
The output signal @S Co changes to H level at the rising edge, indicating that an abnormality has occurred in the rate signal Q3rt.

According to such a configuration, it is easier to use than a conventional counter.
11 circuit configuration, low cost and high reliability.
It will be done.

In the above embodiment, an example was shown in which the strobe clock is delayed by a predetermined time and then applied to the comparator circuit, but the present invention is not limited to this, and the format clock may be delayed by a predetermined time and then added.

Furthermore, by switching the strobe clock and format clock in this manner, when an abnormality is detected, the cause of the abnormality can be clarified. In other words, if an abnormality is detected in combination with the strobe clock, it can be determined that the abnormality is in the rate signal system, and an abnormality is detected in combination with the strobe clock. If the abnormality is not detected in combination with the format clock, it can be determined that the abnormality is in the strobe clock system, and in which combination of strobe clocks the abnormality is not detected, but in combination with the format clock, the abnormality is detected. If so, it can be determined that there is an abnormality in the format clock system.

[Effects of the Invention] As explained above, according to the present invention, there is provided a highly reliable, low-cost timing generation circuit self-diagnosis device with a /'ff'41 circuit configuration that has a function of detecting generation omission of a rate signal. This can be realized and has great practical effects.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, and FIG. 3 is a block diagram showing an example of a conventional device. 1... Timing generation circuit, 6... Rate diagnosis circuit, 7... Comparison circuit (exclusive OR gate), 8.10
...3 extension circuit 1.9...Pulse detection circuit, 11...
·register.

Claims (1)

[Claims] a timing generation circuit that generates a rate signal with a predetermined period and at least one timing signal that is delayed by a predetermined time with respect to the rate signal; a delay circuit that delays the timing signal by one period with respect to the rate signal; A timing generation circuit self-diagnosis device comprising a comparison circuit that compares a timing signal delayed by a delay circuit, and a register that holds an output signal of the comparison circuit.