KR100834392B1 - Semiconductor device - Google Patents

Abstract

The present invention detects a logic value of the second DLL clock based on a delay locked loop for receiving first external clocks and generating complementary first and second DLL clocks, and an edge of the first DLL clock. And an error detection means for generating error detection signals of the first and second DLL clocks.

Fixed Delay Loop, Error Detector, DLL Clock

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

1 is a block diagram illustrating a circuit for testing a delay locked loop in the related art.

2 is a block diagram illustrating a circuit for testing a delay locked loop in accordance with the present invention.

FIG. 3 is a timing diagram for describing each signal of FIG. 2. FIG.

4 is a circuit diagram illustrating an example of an error detection unit of FIG. 2.

FIG. 5 is a timing diagram for describing each signal of FIG. 4. FIG.

* Explanation of symbols for the main parts of the drawings

100 semiconductor device 200 buffer portion

300: delayed fixed loop 410: first pad

420: second pad 430: third pad

500: error detection unit 600: reset unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a semiconductor device that detects an error (errer) of a signal generated in a delay locked loop (DLL).

Synchronous semiconductor devices such as DDR SDRAM (Double Data Rate Synchronous DRAM) use an internal clock synchronized with an external clock (hereinafter, referred to as "EXT_CLK") input from an external controller to perform data transfer with external devices. Perform. In this way, the use of the internal clock is for stable data transmission between the external device and the synchronous semiconductor device, and the time synchronization between the external clock EXT_CLK and the data is very important.

In general, the synchronous semiconductor device includes a clock synchronizing circuit to perform this role. Such clock synchronizing circuits typically include a phase locked loop (PLL) and a delay locked loop (DLL). When the frequency of the external clock EXT_CLK and the internal clock are different from each other, the clock synchronous circuit has a frequency multiplier function. The phase locked loop (PLL) is mainly used, and when the frequency of the external clock (EXT_CLK) and the internal clock is the same, most of the delay locked loop (DLL) is used.

Here, the delay locked loop DLL has less noise than the phase locked loop PLL and can be implemented with a small area. Therefore, in the synchronous semiconductor device, the delay locked loop DLL is generally used as the synchronization circuit. . Among them, the most recent technology includes a register that can store a fixed delay value, and when the power is turned off, the fixed delay value is stored in the register when the power is turned off. Register-controlled DLL loops, which can reduce the time required for initial clock lock, are most widely used.

In addition, the delay locked loop DLL compensates for the delay component that occurs when the input external clock EXT_CLK is transferred to the data output terminal of the semiconductor device, thereby generating an internal clock, and finally outputs the input / output data to the edge of the clock. Position it exactly at the edge or center.

On the other hand, as the operation speed of the semiconductor device becomes faster, distortion occurs in the external clock EXT_CLK itself, which frequently causes a shift in the duty cycle of the clock. As such, the delay locked loop DLL in a state in which the duty cycle of the clock is shifted is more likely to cause a malfunction, and the internal clock generated in the delay locked loop DLL may also distort the duty cycle. In this situation, a test for reliability of an internal clock generated from a delay locked loop (DLL) has emerged as an important issue these days.

1 is a block diagram illustrating a circuit for testing a delay lock loop 30 in the related art.

The semiconductor device 10 of FIG. 1 receives the external clock EXT_CLK and a buffer unit 20 for buffering the output signal of the buffer unit 20 and a rising DLL clock (hereinafter, “RCLKDLL”). And outputting a delay locked loop 30 for generating a polling DLL clock (hereinafter, “FCLKDLL”), a first pad 41 for outputting a rising DLL clock (RCLKDLL), and a polling DLL clock (FCLKDLL). A second pad 42 is shown.

Here, since the specific circuit configuration of the buffer unit 20 and the delay lock loop 30 is well known, the detailed description thereof will be omitted.

For reference, the rising DLL clock RCLKDLL and the falling DLL clock FCLKDLL are internal clocks generated by the delay locked loop 30 so that data may be synchronized to the edge of the external clock EXT_CLK. This clock is generated considering the delay of the device. In other words, in order to export data to the rising and falling edges of the external clock EXT_CLK, the delay locked loop 30 has a rising DLL clock RCLKDLL having the same phase as the external clock EXT_CLK. And generate a polling DLL clock (FCLKDLL) with opposite phases. The rising DLL clock (RCLKDLL) and the falling DLL clock (FCLKDLL) must have opposite phases and have the correct duty.

In order to monitor to ensure the reliability of the rising DLL clock RCLKDLL and the falling DLL clock FCLKDLL, a separate test mode is used for the rising DLL clock RCLKDLL and the falling DLL clock. FCLKDLL) is output to the first pad 41 and the second pad 42, respectively, and the clock is analyzed using an oscilloscope device.

However, there is a limit in monitoring the rising DLL clock (RCLKDLL) and the falling DLL clock (FCLKDLL) that are continuously output in units of 'ns' on the time axis. In addition, since the resolution of the oscilloscope itself is limited, it is impossible to continuously display a waveform of several 'ns' units in real time. Furthermore, when the waveform is distorted at one point or two points among the numerous rising DLL clocks RCLKDLL and the falling DLL clock FCLKDLL, it is more difficult to monitor.

In other words, when determining whether the delayed fixed loop 30 is normally operated, reliability of the test result is deteriorated due to the resolution problem of the oscilloscope itself and a monitoring miss due to a problem that cannot be displayed in real time. .

The present invention has been proposed to solve the above-mentioned problems of the prior art, and it is possible to reliably detect the error (errer) of the rising DLL clock RCLKDLL and the falling DLL clock FCLKDLL, which are output signals of the delay locked loop DLL. The object is to provide a semiconductor device that can be.

According to the present invention for achieving the above object, a delay locked loop for receiving the external clock to generate the first and second DLL clock complementary to each other; And error detection means for detecting a logic value of the second DLL clock based on an edge of the first DLL clock, and generating error detection signals of the first and second DLL clocks. to provide.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

2 is a block diagram illustrating a circuit for testing the delay locked loop 300 according to the present invention.

The semiconductor device 100 of FIG. 2 receives the external clock EXT_CLK from the buffer unit 200 for buffering and the output signal of the buffer unit 200 to receive the rising DLL clock RCLKDLL and the falling DLL clock. An error detection unit 500 for detecting the logic value of the polling DLL clock FCLKDLL based on the edge of the delay locked loop 300 for generating FCLKDLL and the edge of the rising DLL clock RCLKDLL and generating an error detection signal DLL_ERR1. ), A reset unit 600 for resetting the error detector 500, a first pad 410 for outputting the rising DLL clock RCLKDLL, and a second output for the polling DLL clock FCLKDLL. The pad 420 and the third pad 430 to which the error detection signal DLL_ERR1 is output are shown.

Herein, the output signals RCLKDLL and FCLKDLL and the error detection signal DLL_ERR1 of the delay locked loop 300 are output from the first to third pads 410, 420, and 430, and the connection may be changed according to a test purpose. have. For example, to test only errors of the rising DLL clock RCLKDLL and the falling DLL clock FCLKDLL, only the error detection signal DLL_ERR1 is output to any one of the first to third pads 410, 420, and 430. Just do it. As a result, the remaining pads can be connected for other tests.

Meanwhile, since a detailed circuit configuration of the buffer unit 200 and the delay lock loop 300 is well known, a detailed description thereof will be omitted. However, in the present invention (FIG. 2), the error detection unit 500 is added in comparison with the public technology (see FIG. 1), and thus an error detection signal DLL_ERR1 may be generated.

In addition, a reset unit 600 according to the present invention may be further provided, and the operation of the reset unit 600 will be described below with reference to FIG. 3.

FIG. 3 is a timing diagram for describing each signal of FIG. 2.

Referring to FIG. 3, the rising DLL clock RCLKDLL is a signal that toggles to a clock synchronized with the rising edge of the external clock EXT_CLK. The polling DLL clock FCLKDLL is a signal that also toggles to a clock synchronized with the polling edge of the external clock EXT_CLK. Therefore, these two signals RCLKDLL and FCLKDLL are complementary relations to each other, i.e., signals RCLKDLL and FCLKDLL that are out of phase with each other. When these two signals RCLKDLL and FCLKDLL are normally toggled, the error detection signal DLL_ERR1 maintains a logic 'low'. On the other hand, when the rising DLL clock RCLKDLL and the falling DLL clock FCLKDLL are not complementary to each other, that is, when the phases are not inverted correctly with each other, the error detection signal DLL_ERR1 is set to logic 'high'. It is enabled. In this case, the activation means that an incorrect rising DLL clock RCLKDLL or / and a falling DLL clock RCLKDLL has been generated in the delay lock loop 300. That is, a tester performing a test may determine a failure due to a malfunction of the delay locked loop 300 based on the error detection signal DLL_ERR1.

Hereinafter, the reset unit 600 of FIG. 2 will be described.

For example, if the error detection signal DLL_ERR1 remains logic 'high' due to a malfunction of the delay locked loop 300, it is impossible to determine how many malfunctions occur in the delay locked loop 300. Therefore, the reset unit 600 plays a role of resetting the error detector 500 after a predetermined time after the error detection signal DLL_ERR1 is activated as logic 'high'. That is, the reset unit 600 generates a pulse signal after a predetermined time from the activation time of the error detection signal DLL_ERR1, like the reset signal ERR_RST of FIG. 3. The error detection unit 500 is reset in response to the reset signal ERR_RST. Therefore, the error detection signal DLL_ERR1 becomes logic 'high' upon error detection and reset to logic 'low' in response to the reset signal ERR_RST, thereby preparing for an error that may occur later.

As such, the reset unit 600 receives a control signal (hereinafter, referred to as "EXT_CTR") input from an outside of the chip and generates a reset signal ERR_RST, wherein the control signal EXT_CTR is an error. Detection information may be included and may also include information for a tester to reset at a desired time.

4 is a circuit diagram illustrating an example of the error detector 500 of FIG. 2.

Referring to FIG. 4, the error detector 500 receives an input of a falling DLL clock FCLKDLL to set an error detection margin of a rising DLL clock RCLKDLL and a falling DLL clock FCLKDLL. Error detection by receiving a margin setting unit 510 delaying for a time set by the tester (D in FIG. 5), and a rising DLL clock RCLKDLL and an output signal D_FCLKDLL of the margin setting unit 510. An error detection signal generation unit 520 for generating a signal DLL_ERR2 is provided.

In one embodiment of the present invention, it is possible to reset the error detector 500 without adding the reset unit 600 of FIG. 2, which will be described in detail with reference to FIG. 5.

The margin setting unit 510 includes a plurality of delay elements, for example, at least one inverter according to the delay time D. FIG. In particular, an odd number of inverters are used to output the signal D_FCLKDLL inverting the polling DLL clock FCLKDLL.

The error detection signal generator 520 is an edge triggered flip-flop, in particular, a positive edge triggered D flip flop. Therefore, the output signal D_FCLKDLL of the margin setting unit 510 inputted at the time when the rising DLL clock RCLKDLL transitions from the logic 'low' to the logic 'high', that is, the polling DLL clock FCLKDLL is inverted. The logic value of the signal D_FCLKDLL is output as the error detection signal DLL_ERR2.

5 is a timing diagram for describing each signal of FIG. 4.

Referring to FIG. 5, the error detection signal DLL_ERR2 becomes a logic low when the rising DLL clock RCLKDLL and the falling DLL clock FCLKDLL are in a normal state, and transitions to a logic high when an error is detected. In addition, even if the reset unit 600 of FIG.

Here, when there is only one inverter of the margin setting unit 510 of FIG. 4, the logic value of the inverted-delayed polling DLL clock D_FCLKDLL is detected with a margin equal to the delay value D by one inverter. Preferably, when the delay value D increases, the error detection signal DLL_ERR2 reacts insensitively to the error, and when the delay value D decreases, the error detection signal DLL_ERR2 reacts sensitively to the error.

As described above, the present invention includes an error detection unit 500 at the output terminal of the delay locked loop 300 to detect an error occurring in a waveform of several 'ns' units. Therefore, it is possible to easily determine whether the monitoring is missed due to a malfunction of the delay locked loop, a resolution problem of the oscilloscope itself, or a problem that cannot be displayed in real time. And because you know when the error occurred, you have a faster approach to solving the problem.

In addition, the present invention is applicable not only to a semiconductor device including a delay locked loop (DLL) but also to any semiconductor device having a clock that is periodically repeated, and will be more useful in an increasingly faster device.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above can quickly and accurately test whether a delayed fixed loop is malfunctioning, and thus, an effect of remarkably shortening the period of failure analysis can be obtained.

Claims (9)

A delay locked loop configured to receive an external clock and generate first and second DLL clocks complementary to each other; And Error detecting means for detecting a logic value of the second DLL clock based on an edge of the first DLL clock and generating error detection signals of the first and second DLL clocks; A semiconductor device comprising a. delete According to claim 1, And a reset unit for generating a reset pulse which is activated after a predetermined time from an activation time of the error detection signal in response to a control signal input from the outside, which is used as a reset signal of the error detection means. Device. According to claim 1, The error detection means, A margin setting unit configured to receive and delay the second DLL clock in order to set an error detection margin between the first DLL clock and the second DLL clock; And An error detection signal generation unit configured to receive the output signal of the first DLL clock and a margin setting unit and generate the error detection signal; A semiconductor device comprising a. The method of claim 4, wherein The margin setting unit includes a plurality of delay units according to the delay time. The method of claim 5, The delay unit includes at least one inverter. The method of claim 4, wherein And the error detection signal generation unit is an edge triggered flip-flop. The method of claim 7, wherein The edge triggered flip-flop is a positive edge triggered outputting an output signal of the margin setting unit input when the first DLL clock transitions from logic 'low' to logic 'high' as the error detection signal. And a flip-flop. According to claim 1, And the first DLL clock is a signal having rising edge information of the external clock and the second DLL clock is a signal having falling edge information of the external clock.

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