JP2001319494A - Built-in self-test device for memory circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a built-in self-test device for memory circuit which can test the timing specification such as setup time, hold-time, or the like prescribed for a memory to be tested by using plural timing signals having a prescribed phase difference. SOLUTION: The built-in self-test device 1 for memory circuit 23 is constituted of an address generator 5 for setting a test address, a data generator 6 for generating write-in test data, a sequence control circuit 2 for controlling these generators, and a comparator 7 for reading out written data and discriminating whether read-out data is correct or not, and, further, contains a PLL circuit 3 for generating plural timing signals having the prescribed phase difference, a timing signal selecting circuit 4 for selecting the prescribed timing from these timing signals, and an inverter 8a for inverting a signal 10 to be tested outputted from the sequence control circuit 2 with rise or fall timing of a control signal outputted from this circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a built-in self-test apparatus for a memory circuit, and more particularly, to a timing spec test of a memory under test using a plurality of timing signals having a predetermined phase difference. The present invention relates to a built-in self-test device for a memory circuit.

[0002]

2. Description of the Related Art A built-in self-test apparatus for a memory circuit includes:
In particular, it is used for facilitating testing of a semiconductor integrated device having one or more embedded memories. Conventionally, in a custom LSI or the like equipped with an embedded memory, a method of directly testing the installed memory from the outside has been adopted. In recent years, the number of mounted memory blocks and the number of memory block terminals have increased remarkably, and problems such as the number of external terminals required for testing, test time, and increase in test pattern length cannot be ignored. By mounting a built-in memory self-test device in such a custom LSI, a high failure detection rate can be obtained in a memory test that cannot be directly tested from the outside. Further, since the self-test apparatus enables simultaneous testing of a plurality of memories, it is possible to reduce the test pattern length and the test time. The self-test device can be operated with a small number of test signals, and the number of test terminals required for the test can be reduced to a small number without depending on the number of memory blocks and the number of terminals of the memory blocks.

As a test pattern for a memory, a march pattern can detect all fixed failures and has a relatively short pattern length, so that it is often used as a standard pattern for a function test. Also in the memory self-test apparatus, the self-test apparatus for executing the march pattern is used as a standard because it can be realized with a small amount of hardware.

As described above, a self-test apparatus for a memory circuit is generally intended only for a function test of a memory.
No consideration is given to performing a test of a timing specification by generating a test signal under the same conditions as a timing specification such as a setup timing and a hold timing defined in an interface portion of a memory block.

However, in recent years, the speed at which embedded memories are operated at high speed near the limit of their ability has been increasing, and not only functional tests but also timing specification tests such as setup timing and hold timing of the embedded memories at the time of product shipment are performed. Is required. The embedded memory is often integrated with a CPU or the like in a custom LSI and used as a storage device of the CPU. In such a case, whether or not the embedded memory satisfies its own timing specification is actually determined by the CPU.
It is necessary to confirm the operation of the embedded memory and to perform a test of the timing specification with the embedded memory alone. When the built-in memory is operated together with the CPU, it is necessary to operate the CPU at the actual speed, which complicates the test process and diminishes the advantage of incorporating the self-test device. Therefore, it is desired to perform not only the function test of the built-in memory but also the timing specification using the self-test apparatus.

The prior art will be described with reference to FIG.

FIG. 11 shows a self test apparatus 1a and a memory unit 2
2 is comprised.

[0008] The memory unit 22 is a clock synchronous memory 2
3 and selectors 24a to 24d. A normal input signal bundle 3 such as a clock 27, an address 26, input data 29, a write enable signal 28, etc.
In addition to 1, a test input signal bundle 30 corresponding to each of the normal input signals is input.

The test input signal bundle 30 is a test address signal 18, a test clock 19, a test write enable signal 20, and test input data 21. The test input signal bundle 30 is connected to a selector in a memory unit to which a normal input signal of the same function is connected, and its output is connected to the clock synchronous memory 23. That is, the test address 18 and the address 26 are connected to the selector 24a, the test clock 19 and the clock 27 are connected to the selector 24b, and the test write enable signal 20
And write enable signal 28 are connected to selector 24c, and test input data 21 and input data 29 are
Connected to selector 24d. Selectors 24a to 24d
Are connected to a clock synchronous memory 23.
The selection operation of the selectors 24a to 24d is performed by the TEST signal 17 input to the memory unit 22 from the outside. When the logic of the TEST signal 17 is “1”, the selectors 24 a to 24 d select the test input signal bundle 30 and
When the logic of the ST signal 17 is “0”, the normal input signal bundle 3
Select 1.

When the TEST signal 17 becomes logic "0",
The self-test apparatus 1a stops functioning and the selectors 24a to 24a-2
4d selects the normal signal bundle 31, and the memory unit 22 functions by the normal signal bundle 31 output from a CPU or the like (not shown). When the TEST signal 17 becomes logic "1", the self-test apparatus 1a starts functioning and the selectors 24a to 24d
Selects the test signal bundle 30, and the memory unit 22 functions with the test signal bundle 30 supplied from the self-test apparatus 1a.

The self test apparatus 1a comprises a sequence control circuit 2, an address generator 5, a data generator 6, and a comparator 7.

Referring to FIG. 11, an external clock 16 and TE
The ST signal 17 is connected to the sequence control circuit 2. When the TEST signal 17 becomes logic “0”, the sequence control circuit 2 stops functioning. When the TEST signal 17 becomes logic “1”, the sequence control circuit 2 functions in synchronization with the external clock 16.

When the sequence control circuit 2 starts functioning, it outputs a test clock 19 in synchronization with the external clock 16. The test clock 19 is supplied to the clock synchronous memory 23 via the selector 24b of the memory unit 22. When the sequence control circuit 2 starts functioning,
The test write enable signal 20 is output in synchronization with the external clock 16. Test write enable signal 20
Are supplied to the clock synchronous memory 23 via the selector 24c of the memory unit 22. Further, when the sequence control circuit 2 starts functioning, it outputs an address control signal 41 in synchronization with the external clock 16.

The address control signal 41 is supplied to the address generator 5. Further, when the sequence control circuit 2 starts functioning, it outputs a data control signal 42 in synchronization with the external clock 16. The data control signal 42 is supplied to the data generator 6.

When an address control signal is supplied from the sequence control circuit 2, the address generator 5 generates an address having a plurality of bit widths corresponding to the configuration of the memory section 22 at the timing of the address control signal 41, and generates a test address. The signal 18 is output. The test address signal 18 is supplied to the clock synchronous memory 23 via the selector 24a of the memory unit 22.

The data generator 6 includes a sequence control circuit 2
When the data control signal 42 is supplied, the data generator 6 operates the memory unit 2 at the timing of the data control signal 42.
2. Output test input data having a plurality of bits corresponding to the configuration of 2. The test input data 21 is supplied to the clock synchronous memory 23 via the selector 24d of the memory unit 22. The data having a plurality of bit widths generated by the data generator 6 is supplied to the comparator 7 as an expected value signal 40.

The comparator 7 compares the output data output from the memory unit 22 with the expected value signal 40 output from the data generator 6. The comparator 7 outputs a logic “1” to the test result output when the expected value data 40 matches the output data, and outputs a logic “0” to the test result output when they do not match.

Referring to FIG. 5, comparator 7 is configured as follows.

That is, a plurality of Es according to the data bit width
XOR (Exclusive OR) gates 32a-3
2c and a NOR gate 33.

The expected value signal 40 and output data are input to the EXOR gates 32a to 32c, and the outputs of the EXOR gates 32a to 32c are input to the NOR gate 33. The output of the NOR gate 33 becomes logic "1" only when the expected value signal 40 matches the output data, and becomes logic "0" when they do not match.

When the TEST signal 17 is logic “0”, the write operation of the memory unit 22 is performed in synchronization with the rising edge of the clock 27. The memory unit 22 latches the write enable signal 28, the address 26, and the input data 29 at the rising edge of the clock 27, and writes the input data 29 to the latched address. The read operation of the memory unit 22 is performed in synchronization with the rising edge of the clock 27. The memory unit 22 has a write enable signal 2
8. Latch the address 26 at the rising edge of the clock 27 and output the data held at the latched address.

When the TEST signal 17 is logic “1”, the write operation of the memory unit 22 is performed in synchronization with the rising edge of the test clock 19. The memory unit 22 latches the test write enable signal 20, the test address 18, and the test input data 21 at the rising edge of the test clock 19, and writes the test input data 21 to the test address 18. The read operation of the memory unit 22 is performed as follows.
This is performed in synchronization with the rising edge of the test clock 19. The memory unit 22 includes a test write enable signal 2
0, the test address 18 is latched at the rising edge of the test clock 19, and the data held in the test address 18 is output.

The write timing and read timing for the memory section 22 will be described with reference to FIG.

In the operation timing chart of FIG.
S is the address setup period required for the address 26 or the test address 18, and tAH is the address 2
6, or a hold period required for the test address 18, tDS is a setup period required for the input data 29 or the test input data 21, tDH is a hold period required for the input data 29 or the test input data 21, and tWS is a hold period required for the input data 29 or the test input data 21. , Write enable 28 or test write enable 20, and tWH represents a hold period required for write enable 28 or test write enable 20. tACC indicates a data access time from the rising edge of the clock. At the time of the read operation and the write operation to the memory unit 22, if it is not performed so as to satisfy the read timing and the write timing,
Its operation is not guaranteed.

Next, the operation of FIG. 11 will be described with reference to FIG.

While the TEST signal 17 is at logic "0", the self test apparatus stops functioning and the selector 2 of the memory section 22
4a to 24d select the normal signal bundle 31. While the TEST signal 17 is at logic “0”, a read operation and a write operation to the memory unit are performed by a CPU (not shown) via the normal signal bundle 31. When the TEST signal 17 becomes logic "1", the sequence control circuit 2 in the self test apparatus 1a starts functioning, and the selectors 24a to 24d of the memory unit 22
Selects the test signal bundle 30.

FIG. 12 shows that the TEST signal 17 is a logical "1".
, The result of comparison between the expected value data 40 and the output data output from the memory unit 22 by the comparator 7 at the time of the write operation and the read operation from the self-test apparatus 1a to the memory unit 22 and the read operation. FIG. 9 is a diagram showing an example of an operation timing for outputting the "?"

A pattern 1 in FIG. 12 shows a timing at which the self-test apparatus 1a writes data D1 to an address A1 of the memory unit 22. The pattern 2 is the address A written in the memory unit 22 by the self-test apparatus 1a in the pattern 1.
1 shows the timing at which data D1 is read from No. 1 and the result of comparing the read output data with the expected value signal 40 is output.

In pattern 1, sequence control circuit 2
Is a test clock 19 having the same signal as the external clock 16.
Is supplied to the memory unit 22.

At the falling edge of the external clock 16 of the pattern 1, the sequence control circuit 2 sets the test write enable signal 20 to logic "0", and sets the operation of the memory unit at the next rising edge of the test clock 19 to the write operation. Switch. Further, the external clock 16 of pattern 1
The sequence control circuit 2 supplies the address control signal 41 to the address generator 5, generates the address A1 in the address generator 5, and outputs it as the test address 18. Further, at the falling edge of the external clock 16 of the pattern 1, the sequence control circuit 2 supplies the data control signal 42 to the data generator 6, and the data generator 6 generates the data D1 and outputs the data D1 as the test input data 21. I do.

At the rising edge of the test clock 19 of the pattern 1, the self test apparatus 1a writes the data D1 to the address A1 of the memory unit 22.

In pattern 2, the sequence control circuit 2
Is a test clock 19 having the same signal as the external clock 16.
Is supplied to the memory unit 22.

At the falling edge of the external clock 16 of the pattern 2, the sequence control circuit 2 sets the test write enable to logic "1", and switches the operation of the memory unit to the read operation at the next rising edge of the test clock 19. Further, at the falling edge of the external clock 16 of the pattern 2, the sequence control circuit 2 supplies the address control signal 41 to the address generator 5, and the address generator 5 generates the address A1, and the test address 1
8 is output. Further, at the falling edge of the external clock 16 of the pattern 2, a data control signal 42 is supplied to the data generator 6, the data generator 6 generates data D 1, and outputs it as an expected value signal 40.

At the rising edge of the test clock 19 of the pattern 2, the self test apparatus 1a reads the data D1 from the address A1 of the memory unit 22. The output data output from the memory unit 22 is input to the comparator 7, which compares the expected value signal 40 with the output data, and outputs the comparison result as a test result output. At this time, if the expected value signal and the output data match, the test result output is PA
The logic becomes "1" indicating SS, and if the expected value signal and the output data do not match, the logic becomes "0" indicating FAIL.

[0035]

Since the operation is performed in synchronization with the external clock, the test signal bundle 30 output from the self-test apparatus 1a has a rising edge or a rising edge of the external clock 16, which is the operation timing of the sequence control circuit 2. This is synchronized with the falling edge. As a result, the setup period and the hold period of the other test signals with respect to the test clock 19 supplied to the memory unit 22 are about half the period of the external clock 19. In order to change the timing of the test signal bundle 30 supplied to the memory unit in such a configuration, it is necessary to increase the frequency of the external clock 19 or change the duty ratio of the external clock. In recent years, as the performance of memory blocks has become higher, the timing specification has been on the order of several nanoseconds. To supply a test signal to the memory unit 22 at the same timing as this condition, the external clock frequency must be increased to several hundred MHz. There is a need to. Further, even if the duty ratio of the external clock is changed, it is necessary to set the high width or the low width to several nanoseconds. Usually, when testing a semiconductor device, an LSI tester is used.

A high-speed LSI tester is expensive. If a high-speed LSI tester is used for testing a semiconductor device, the unit price of the device is affected. When changing the duty ratio of the clock signal, the LSI tester modulates the clock signal using a plurality of timing generation systems. In a general LSI tester, the timing skew between such a plurality of timing generation systems is about several nanoseconds,
It is difficult to obtain an accuracy of several nanoseconds in the duty ratio of the clock signal.

Further, even if an expensive LSI tester can be used and the setup timing or the hold timing of the test signal bundle 31 given from the self-test apparatus 1a to the memory unit 22 can be set to a desired timing, The setup timing and the hold timing of the signal under measurement become the desired timing only in the pattern in which the signal under measurement changes. This means that the test efficiency of the timing specification differs depending on the test pattern given to the memory unit by the self-test apparatus. That is, the test time increases, and L
The test cost of the SI increases, which affects the unit price.

As the timing specifications defined in the memory unit 22, there is a timing specification that defines a delay time of an output signal such as a data access time of output data of the memory unit 22.

The output data of the memory section 22 is input to the comparator 7, and can be indirectly observed from the test result output output from the comparator 7. However,
When the test result output is observed externally, the gate delay time in the comparator 7 and the delay time until the test result output is output to the outside are added, and the delay time is observed as a delay time larger than the actual data access time. Would.
In this case, the delay time for outputting the test result to the outside becomes dominant. For this reason, it is necessary to separately measure and correct the extra delay time to be added, which complicates the test process.

An object of the present invention has been made in view of the above-mentioned points, and an object of the present invention is to use a plurality of timing signals having a predetermined phase difference to define a setup specified in a memory under test. By applying test signals under the same conditions as the timing specifications such as time and hold time, it is possible to test the timing specifications of the memory under test without using an expensive LSI tester. A self-test apparatus is provided.

[0041]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object.

That is, a first embodiment of the built-in self-test device for a memory circuit according to the present invention comprises a memory circuit and a built-in self-test device for the memory circuit. A sequence control circuit receiving a control signal and outputting a control signal; an address generator receiving the control signal to generate an address signal and outputting the address signal to the memory circuit; and generating a test data by receiving the control signal. Then, the data generator that outputs to the memory circuit, the test data that is output by the data generator, and the output data that is read after the memory circuit is provided with the test data after being supplied with the test data are provided and compared. And a comparator for outputting a comparison result as to whether or not the test data is different from the output data. In the self-test apparatus, a PLL circuit that generates a plurality of timing signals having a predetermined phase difference, a timing signal selection circuit that selects a predetermined timing from the plurality of timing signals generated by the PLL circuit, An inverter for inverting a signal under test supplied to the memory unit at a rising or falling timing of the output control signal. The signal under test output from the control circuit is a write enable signal for controlling writing / reading of the memory circuit, and a third mode is a signal under test output from the inverter. The test signal is an address signal designating an address of the memory circuit. The signal under test output from the inverter is a write data signal for the memory circuit, and the fifth aspect is that the signal under test output from the inverter is A sixth aspect is a write enable signal for the memory circuit, and a sixth aspect is a method for reading read data read from the memory circuit based on a second control signal output from the timing selection circuit. A latch for latching is provided. A seventh aspect is the present invention, and an eighth aspect is that the PLL circuit comprises:
A phase comparator for detecting a phase difference between an oscillation clock of a voltage controlled oscillator of the PLL circuit and an external clock; and a charge for controlling an input voltage to the voltage controlled oscillator based on the phase difference detected by the phase comparator. A pump circuit;
A voltage-controlled oscillator in which N stages of inverting logic gates whose current drive capability can be controlled is connected in a ring shape, and a control signal for controlling the inverter or the latch is extracted from the inverting logic gate. Things.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A built-in self-test device for a memory circuit according to the present invention comprises a memory circuit and a built-in self-test device for the memory circuit. An address generator for setting the data, a data generator for generating test data for writing data to the memory circuit, and reading the data written to the memory circuit to determine whether the read data is correct data And a plurality of timing signals having a predetermined phase difference are generated in a built-in self-test device for a memory circuit including a comparator for comparing the address generator and a sequence control circuit for controlling the address generator and the data generator. A PLL circuit and a timer for selecting a predetermined timing from a plurality of timing signals generated by the PLL circuit; A switching signal selecting circuit, and an inverter for inverting a signal under test output from the sequence control circuit at a rising or falling timing of a control signal output from the timing selecting circuit. Things.

Therefore, it is possible to output a test signal at a plurality of timings different from the external clock supplied to the self-test apparatus, and to set up and hold the test signal supplied to the memory circuit as the circuit under test. Arbitrarily can be set for testing.

[0045]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a built-in self-test apparatus for a memory circuit according to the present invention will be described below in detail with reference to the drawings.

(First Specific Example) FIGS. 1 to 7 show a first specific example of a built-in self-test apparatus for a memory circuit according to the present invention. The built-in self-test device 1 for the memory circuit 23,
An address generator 5 for setting a test address of the memory circuit 23; a data generator 6 for generating test data for writing data to the memory circuit 23; 23
And a sequence controller 2 for controlling the address generator 5 and the data generator 6 for comparing the read data with the correct data. In a built-in self-test device for a circuit, a PLL circuit 3 for generating a plurality of timing signals having a predetermined phase difference;
A timing signal selection circuit 4 for selecting a predetermined timing from the plurality of timing signals generated by the timing control circuit 4 and the sequence control circuit 2 at the rising or falling timing of the control signal output from the timing selection circuit 4.
And an inverter 8a for inverting the signal under test (the test address 10 in this specific example) outputted from.

Further, the figure shows a built-in self-test device for a memory circuit, wherein the inverter 8a is constituted by an exclusive OR circuit.

Further, in the figure, the PLL circuit 3 includes a phase comparison circuit 34 for detecting a phase difference between the external clock 16 and the internal clock φN, and a voltage based on the phase difference detected by the phase comparison circuit 34. A charge pump circuit 35 for controlling an input voltage to the control oscillator 36; and a voltage control oscillator 36 in which N stages of inverting logic gates 37a to 37n capable of controlling current driving capability are connected in a ring shape. There is shown a built-in self-test device for a memory circuit, wherein control signals for controlling the inverter 8a are extracted from gates 37a to 37n.

Hereinafter, the first specific example will be described in more detail.

In FIG. 1, reference numeral 1 denotes a built-in self-test device for memory, and 2 denotes a memory unit 22. 1 includes a sequence control circuit 2, an address generator 5, a data generator 6, a comparator 7, a PLL circuit 3, a timing selection circuit 4, and an inverter 8a.

In FIG. 1, the external clock 16 is
Input to the L circuit 3. The PLL circuit 3 generates a plurality of signals φ0 to φN having different phases synchronized with the external clock 16. The plurality of timing signals φ0 to φN having different phases output from the PLL circuit 3
Is input to The timing selection circuit 4 receives a PLL signal from the PLL circuit 3 based on a timing selection signal 15 input from the outside.
An arbitrary timing signal is selected and output from a plurality of timing signals φ0 to φN output therefrom. The output of the timing selection circuit 4 is supplied as an inversion control signal of the inverter 8a. Further, the timing selection circuit 4 supplies one signal φP from the plurality of timing signals having different phases output from the PLL circuit 3 as a sequence control clock φP of the sequence control circuit 2.

The sequence control circuit 2 outputs the TEST signal 1
7 starts the sequence control clock φ
The test clock 19 is output in synchronization with P. The test clock 19 is supplied to the synchronous memory 23 via the selector 24b of the memory unit 22. When the sequence control circuit 2 starts functioning, the sequence control clock φ
The test write enable signal 20 is output in synchronization with P. The test write enable signal 20 is transmitted to the memory unit 22
Is supplied to the clock synchronous memory 23 through the selector 24c. Further, when the sequence control circuit 2 starts functioning, it outputs an address control signal 41 in synchronization with the sequence control clock φP. The address control signal 41 is supplied to the address generator 5. Further, when the sequence control circuit 2 starts functioning, the sequence control clock φ
The data control signal 42 is output in synchronization with P. The data control signal 42 is supplied to the data generator 6.

When an address control signal 41 is supplied from the sequence control circuit 2 to the address generator 5, an address having a plurality of bit widths corresponding to the configuration of the memory section 22 is generated in accordance with the address control signal 41, and 8a.

The inverter 8 a receives the output of the timing selection circuit 4, inverts the signal input from the address generator 5, and outputs the result as a test address 18. Specifically, during the period when the logic of the inversion control signal is “0”, the inversion logic of the input signal of the inverter 8a is output, and when the logic of the inversion control signal is “1”, the input signal of the inverter 8a is output. Output as is. The test address 18 output from the inverter 8a is
The data is supplied to the clock synchronous memory 23 via the selector 24a of the memory unit 22.

The data generator 6 includes the sequence control circuit 2
When the data control signal 42 is supplied, data having a plurality of bit widths corresponding to the configuration of the memory unit 22 is generated according to the data control signal 42, and the test input data 21 is output. The test input data 21 is supplied to the clock synchronous memory 23 via the selector 24d of the memory unit 22. Further, data having a plurality of bit widths generated by the data generator 6 is supplied to the comparator 7 as an expected value signal 40.

The comparator 7 compares the output data output from the memory unit 22 with the expected value signal 40 connected from the data generator 6. The comparator 7 outputs a logic “1” to the test result output when the expected value data 40 and the output data match, and outputs a logic “0” to the test result output when they do not match.

Referring to FIG. 2, PLL circuit 3 is configured as follows.

That is, it comprises a phase comparison circuit 34, a charge pump circuit 35, and a voltage controlled oscillation circuit 36. The external clock 16 is input to a phase comparison circuit 34. The phase comparison circuit 34 detects a phase difference between the external clock 16 and the internal clock φN.
To control the input voltage to the voltage controlled oscillation circuit 36. The voltage-controlled oscillation circuit 36 has multi-stage inverted logic gates 37a to 37n whose current drive capability can be controlled by a voltage connected to a ring. The frequencies of the signals φ0 to φN extracted from each stage of the voltage controlled oscillation circuit 36 are substantially the same as the frequency of the external clock 16. The delay time of each stage is determined by the frequency of the external clock and the number of inverted logic gate stages, and is equal to one cycle of the external clock 16 divided by the number of inverted logic gate stages.

Referring to FIG. 3, a timing chart of the PLL circuit 3 is shown. φ0 to φN are signals output from each stage of the voltage controlled oscillation circuit. In particular, the signal φP is a signal whose phase is shifted from the external clock 16 by almost 180 degrees from the signal φ0. The signal φN changes at the same timing as the external clock 16.

Next, the timing selection circuit 4 is configured as shown in FIG.

That is, the signal φ output from the PLL circuit 3
A plurality of 3-state buffers 5a to 5c for inputting a plurality of timing signals 0 to φN;
And a decoder circuit 4a for activating a selection signal of one three-state buffer from a plurality of three-state buffers 5a to 5c.

The inverter 8a is configured as shown in FIG. That is, a plurality of EXNORs (Exclusive NOR) for inverting an input signal having a plurality of bit widths.
The gates 8aa to 8ac are configured such that an inversion control signal from the timing selection circuit 4 and an address signal 10 from the address generator 5 are input to the inputs of the EXNOR gate. The EXNOR gate outputs the input signal as it is when the logic of the inverted control signal is “1”, and outputs the inverted logic of the input signal when the inverted control signal is “0”.

Next, the operation of the first specific example will be described with reference to FIG.

FIG. 7 shows that the address setup period tAS required for the memory unit 22 corresponds to a delay time of one stage of the inverted logic gate of the voltage controlled oscillation circuit 36, and the self test apparatus 1 supplies the memory unit 22 with the address setup period tAS. This is a timing when the test address 18 is output at a timing earlier than the rising edge of the test clock 19 by one stage of the inverted logic gate and the test of the address setup period tAS is performed.

In FIG. 7, a signal .phi.P is supplied to the sequence control circuit 2 as a sequence control clock, and as an inversion control signal of the inverter 8a, the inverted logic gate 1 is inverted from the signal .phi.P by the input of the timing selection signal 15.
FIG. 9 shows a timing chart of an example in which the signal φN at a timing earlier by the stage is supplied.

A pattern 1 in FIG. 7 shows a timing at which the self-test apparatus 1 writes data D1 to the address A1 of the memory unit 22. The pattern 2 indicates the timing at which the self test apparatus 1 reads the data D1 from the address A1 written to the memory unit 22 in the pattern 1 and outputs the result of comparison with the expected value signal 40.

In pattern 1, sequence control circuit 2
Supplies a test clock 19 of the same signal as the sequence control clock φP to the memory unit 22.

At the falling edge of sequence control clock φP of pattern 1, sequence control circuit 2 sets test write enable signal 20 to logic “0” and sets memory unit 2 at the next rising edge of test clock 19.
2 is switched to a write operation. Further, at the falling edge of the external clock 16 of the pattern 1, the sequence control circuit 2 sends the address control signal 41 to the address generator 5
The address A5 is generated by the address generator 5 and supplied to the inverter 8a. The inverter 8a outputs the address A1 as it is during the logic “1” of the inversion control signal φN, and inverts the logic of the address A1 and outputs it to the memory unit 22 during the logic “0” of the inversion control signal φN. I do. Further, at the falling edge of the sequence control clock φP of the pattern 1, the sequence control circuit 2 supplies the data control signal 42 to the data generator 6, and the data generator 6 generates data D1. Data generator 6
Outputs data D1 as test input data 21.

At the rising edge of the test clock 19 of the pattern 1, the self test apparatus 1 writes the data D1 to the address A1 of the memory unit 22.

In pattern 1, the period from the rising edge of the inversion control signal to the rising edge of test clock 19 is the address setup period. Test clock 19 is equal to signal φP output from PLL circuit 3,
The inversion control signal is equal to the signal φN. Therefore, during the address setup period of pattern 1, the inverted logic gate 1
The number of stages is equal to the address setup period tAS requested by the memory unit 22. On the other hand, a period from the rising edge of the test clock 19 to the falling edge of the inversion control signal φN is an address hold period. At this time, if the setup period and the hold period of the test address 18 required by the memory unit 22 are not satisfied during the write operation of the pattern 1, the test input data D1 is written to the incorrect address in the pattern 1.

Also in the pattern 2, the sequence control circuit 2 supplies a test clock 19 of the same signal as the sequence control clock φP to the memory unit 22.

At the falling edge of the sequence control clock φP of the pattern 2, the sequence control circuit 2 sets the test write enable signal 20 to logic “1”, and the memory unit 22 at the next rising edge of the test clock 19
Is switched to the read operation. Further, at the falling edge of the sequence control clock φP of the pattern 2, the sequence control circuit 2 supplies the address control signal 41 to the address generator 5, generates the address A1 in the address generator 5, and supplies it to the inverter 8a. I do. Inverter 8a
Means that during the period of the logic “1” of the inversion control signal φN, the address A
1 is output as it is, and during the period of the logic “0” of the inversion control signal φN, the logic of the address A1 is inverted and output to the memory unit 22. Further, the sequence control clock φ of pattern 2
At the falling edge of P, a data control signal 42 is supplied to the data generator 6, and the data generator 6 generates data D1 and outputs it as an expected value signal 40.

At the rising edge of the test clock 19 of the pattern 2, the self-test apparatus 1 reads the data D1 from the address A1 of the memory unit 22. The output data output from the memory unit 22 is input to the comparator 7, which compares the expected value signal 40 with the output data, and outputs the comparison result as a test result output. At this time, the expected value signal 4
If 0 and the output data match, the test result output is P
The logic becomes "1" indicating ASS, and if the expected value signal 40 does not match the output data, the logic "0" indicates FAIL.
Becomes

In pattern 2, the period from the rising edge of the inversion control signal to the rising edge of test clock 19 is the address setup period. Test clock 19
Is equal to the signal φP output from the PLL circuit 3, and the inversion control signal is equal to the signal φN. Therefore, pattern 2
The address setup period is equivalent to one stage of the inverted logic gate, and is equal to the address setup period tAS requested by the memory unit 22. On the other hand, a period from the rising edge of the test clock 19 to the falling edge of the inversion control signal φN is an address hold period. If the setup period and the hold period of the test address 18 required by the memory unit 22 are not satisfied during the read operation of the pattern 2, the read is performed from the incorrect address in the pattern 2.

In the case where a write operation for an illegal address is performed in pattern 1 and the case where a read operation is performed from an illegal address in pattern 2, incorrect output data is input to the comparator 7 and the test result is output. The signal is FA
The state becomes the IL state.

In the patterns 1 and 2, the signal φN was selected as the inversion control signal of the inverter, and the test of the address setup period tAS was performed.
Therefore, if the different timing signal is selected and the address hold period is changed, the test can be similarly performed for the address hold period tAH of the memory unit 22.

As described above, the self-test apparatus 1 according to the first specific example has the test clock 19 output to the memory unit 22.
In contrast, the setup period and the hold period of another test signal can be changed with the accuracy of the delay time of one stage of the inversion logic gate in the PLL circuit. The delay time of one stage of the inverted logic gate is determined by the frequency of the external clock 16 and the PLL circuit 3.
Is determined by the number of inverted logic gate stages of the voltage controlled oscillation circuit 36, so that the delay time of one inverted logic gate stage can be determined only from the frequency of the external clock 16 and the number of inverted logic gate stages. That is, the delay time of one stage of the inverted logic gate can be controlled by changing the frequency of the external clock 16 as well as the number of stages of the inverted logic gate. By selecting an appropriate timing signal from the delay time per one stage of the inverted logic gate and the timing specification required for the memory unit 22, the test clock 19 supplied from the self-test apparatus 1 to the memory unit 22 and the other tests The timing relationship with the signal can be set to the same condition as the timing specification required for the memory unit 22. In such a state, the self-test apparatus is operated to perform the write operation or the read operation. If the desired output data cannot be obtained in the read operation, the test result output signal from the comparison circuit becomes the FAIL state.

Therefore, P output from the self-test device 1
The timing specification of the memory unit 22 can be tested based on the ASS / FAIL state.

Furthermore, not only the test signal output timing is set, but the test signal logic before and after the test signal output is inverted, so that the test signal always changes at the test signal output timing. Therefore, there is an effect that the timing specification test can be easily performed without depending on the test pattern.

(Second Specific Example) FIGS. 8 to 11 are diagrams showing a second specific example of a built-in self-test apparatus for a memory circuit according to the present invention. Will be described in more detail.

In FIG. 8, the address generator output 10 output from the address generator 5 is input to the inverter 8a. The inverter 8a receives the inversion control signal 100, performs an inversion operation on the address generator output 10, and supplies the result to the memory unit 22 as the test address 18. The write enable output 12 output from the sequence control circuit 2 is input to the inverter 8b. The inverter 8b outputs the inversion control signal 20
0, an inversion operation of the write enable output 12 is performed, and a test write enable signal 20 is output to the memory unit 2.
Supply to 2. The data generator output signal 13 output from the data generator 6 is input to the inverter 8c. The inverter 8 c receives the inversion control signal 300, performs an inversion operation of the data generator output signal 13, and supplies the result as test input data 21 to the memory unit 22. The output data signal output from the memory unit 22 is output to the comparator 7 via the latch 9.
To enter.

The timing selection signals 15a to 15d
Is connected to the timing selection circuit 4a. The timing selection circuit 4a outputs a PL in accordance with the timing selection signal 15a.
A plurality of timing signals φ0 to φ supplied from the L circuit 3
A timing signal is selected from N and supplied to the inverter 8a as an inversion control signal 100. Further, the timing selection circuit 4a selects a timing signal from a plurality of timing signals φ0 to φN supplied from the PLL circuit 3 according to the timing selection signal 15b, and supplies it to the inverter 8b as an inversion control signal 200. Further, the timing selection circuit 4a
Selects a timing signal from a plurality of timing signals φ0 to φN supplied from the PLL circuit 3 in accordance with the timing selection signal 15c, and supplies the selected timing signal as an inversion control signal 300 to the inverter 8c. Further, the timing selection circuit 4a selects a timing signal from a plurality of timing signals φ0 to φN supplied from the PLL circuit 3 according to the timing selection signal 4d, and supplies the selected timing signal to the latch 9 as a latch clock.

The latch 9 latches the output data signal at the rising edge of the latch clock supplied from the timing selection circuit 4a.

The timing selection circuit 4a is configured as shown in FIG.

That is, φ0 output from the PLL circuit 3
a plurality of three-state buffers 5aa to 5ec for inputting a plurality of timing signals of φN;
a to 15d and a plurality of three-state buffers 5aa
.. 5ec to make a selection signal of a predetermined three-state buffer active.

The timing selection circuit 4a outputs the timing selection signal 15a supplied from the outside to the decoder circuit 4aa.
And the timing signals φ0 to φ0 supplied to the plurality of three-state buffers 5aa to 5ac by the decoder circuit 4aa.
One timing signal is selected from a plurality of timing signals of φN and output as an inversion control signal 100. Also,
The timing selection circuit 4a inputs a timing selection signal 15b supplied from the outside to the decoder circuit 4ab, and the decoder circuit 4ab controls the plurality of three-state buffers 5b.
a to 5bc supplied to a plurality of timing signals φ0 to φ5
N, one timing signal is selected, and the inversion control signal 2
Output as 00. Further, the timing selection circuit 4a
Connects the timing selection signal 15c supplied from the outside to the decoder circuit 4ac, selects one timing signal from the plurality of timing signals φ0 to φN supplied to the plurality of tristate buffers 5ca to 5cc by the decoder circuit, Output as the inversion control signal 300. Further, the timing selection circuit 4a inputs a timing selection signal 15d supplied from the outside to the decoder circuit 4ad, and outputs a plurality of timing signals φ supplied to the plurality of three-state buffers 5da to 5dc by the decoder circuit 4ad.
One timing signal is selected from 0 to φN and output as a latch signal. Further, the timing selection circuit 4a
A timing signal (for example, φP) selected from a plurality of timing signals φ0 to φN output from the PLL circuit 3 is output as a sequence control clock without using a decoder circuit. With such a configuration, in the process of selecting the timing signal in the timing selection circuit 4a, the delay time generated in the timing signal can be given to the sequence control clock, and the delay between the sequence control clock and the output timing signal can be controlled. It is possible to eliminate skew.

The timing selection circuit 4a and the inverter 8a
FIG. 10 is a timing chart of the operation of the self-test device 1b when the latches 9 to 8d are used.

FIG. 10 is a timing chart for testing the address setup period tAS, data setup period tDS, write enable hold period tWH, and data access time tACC required for the memory section 22 in this specific example.

In FIG. 10, it is assumed that the address setup period tAS required for the memory section 22 corresponds to a delay time of one stage of the inversion logic gate of the voltage controlled oscillation circuit 36. It is assumed that the data setup period tDS required for the memory unit 22 corresponds to a delay time corresponding to two stages of the inverted logic gates of the voltage controlled oscillation circuit 36. Further, it is assumed that the write enable hold period tWH required for the memory unit 22 corresponds to a delay time corresponding to two stages of the inverted logic gates of the voltage controlled oscillation circuit 36. The data access time tACC required for the memory unit 22
Is equivalent to the delay time of one stage of the inverted logic gate of the voltage controlled oscillation circuit 36.

In FIG. 10, the sequence control circuit 2
, A signal φP is supplied as a sequence control clock, and φN at a timing earlier by one stage than the signal φP by an input of the timing selection signal 15a is supplied as an inversion control signal 100 of the inverter 8a.
As the inversion control signal 200 of the inverter 8b, a signal φ2 at a timing two stages later than the signal φP by the input of the timing selection signal 15b is supplied as the inversion control signal 200, and as the inversion control signal 300 of the inverter 8c, the timing selection signal 15c , A signal φN−2 at a timing two stages earlier than the signal φP by the inverted logic gate is supplied. As a latch clock 400 for the latch, a signal at a timing one stage later than the signal φP by the inverted logic gate by the input of the timing selection signal 15d FIG. 4 shows a timing chart of an example in which φ1 is supplied.

The pattern 1 shown in FIG.
Shows the timing at which the data D1 is written to the address A1 of the memory unit 22. The pattern 2 indicates the timing at which the self-test apparatus 1b reads the data D1 from the address A1 written to the memory unit 22 in the pattern 1 and outputs the result of comparison with the expected value signal 40.

In pattern 1, sequence control circuit 2
Supplies the test clock 19 of the same signal as the sequence control clock φP to the memory unit 22.

At the falling edge of the sequence control clock φP of the pattern 1, the sequence control circuit 2 sets the write enable output 12 to the logic level in order to switch the operation of the memory section 22 to the write operation at the next rising edge of the test clock 19. It is set to "0" and supplied to the inverter 8b. The inverter 8b outputs the write enable output 12 as it is during the logic “0” of the inversion control signal 200 (φ2), and outputs the write enable output 12 during the logic “1” period of the inversion control signal 200 (φ2). And outputs it to the memory unit 22 as the test write enable signal 20.

Further, at the falling edge of the external clock 16 of the pattern 1, the sequence control circuit 2 supplies an address control signal 41 to the address generator 5, and the address generator 5 generates the address A1, and the inverter 8a To supply. The inverter 8a outputs an inversion control signal 100 (φN)
During the period of logic "0", the address A1 is inverted, and during the period of logic "1" of the inversion control signal 100 (φN), the address A1 is output to the memory unit 22. Further, at the falling edge of the sequence control clock φP of the pattern 1, the sequence control circuit 2 supplies the data control signal 42 to the data generator 6, generates the data D1 in the data generator 6, and supplies the data D1 to the inverter 8c. I do. The inverter 8c outputs the data D during the period of the logic “0” of the inversion control signal 3 (φN−2).
1 is inverted, and the data D1 is output to the memory unit 22 during the period of the logic “1” of the inversion control signal 3 (φN−2).

At the rising edge of the test clock 19 of the pattern 1, the self test apparatus 1 writes the data D1 to the address A1 of the memory unit 22.

In pattern 1, the period from the rising edge of the inversion control signal to the rising edge of test clock 19 is the address setup period. Test clock 19
Is equal to φP output from the PLL circuit 3, and the inversion control signal 100 is equal to φN. Therefore, pattern 1
The address setup period is equivalent to one stage of the inverted logic gate, and is equal to the address setup period tAS requested by the memory unit 22.

Since the inversion control signal 300 is equal to φN−2, the data setup period of the pattern 1 is equal to two stages of inversion logic gates, and is equal to the data setup period tDS required by the memory unit 22. Further, since the inversion control signal 200 is equal to φ2, the write enable hold period of the pattern 1 corresponds to two stages of inversion logic gates, and the write enable hold period t required by the memory unit 22
Equal to WH.

At this time, if the write timing of the setup period or the hold period required by the memory unit 22 is not satisfied during the write operation of the pattern 1, the test input data D1 is written to an incorrect address in the pattern 1.

In pattern 2, the sequence control circuit 2
Supplies the test clock 19 of the same signal as the sequence control clock φP to the memory unit 22.

At the falling edge of the sequence control clock φP of the pattern 2, the sequence control circuit 2 sets the write enable output 12 to the logical level in order to switch the operation of the memory unit 22 to the read operation at the next rising edge of the test clock 19. "1" is supplied to the inverter 8b. The inverter 8b performs the inversion logic of the write enable output 12 during the period of the logic “0” of the inversion control signal 200 (φ2), and the write enable output 12 during the period of the logic “1” of the inversion control signal 200 (φ2). Is output to the memory unit 22 as the test write enable signal 20 as it is. Further, at the falling edge of the external clock 16 of the pattern 2, the sequence control circuit 2 supplies the address control signal 41 to the address generator 5, generates the address A1 in the address generator 5, and supplies it to the inverter 8a. . The inverter 8a inverts the address A1 during the period of the logic “0” of the inversion control signal 100 (φN),
During the period of logic “1” of (φN), the address A1 is output to the memory unit 22. Further, at the falling edge of the sequence control clock φP of the pattern 2, the data control signal 4
2 is supplied to the data generator 6, and the data generator 6 generates data D1, and at the same time, outputs the expected value signal 40.

At the rising edge of the test clock 19 of the pattern 2, the self test apparatus 1b reads the data D1 from the address A1 of the memory unit 22. Output data output from the memory unit 22 is supplied to the latch 9.
The latch 9 captures output data at the rising edge of the latch clock 400 (φ1) and outputs it as a comparator input signal 14. The comparator 7 compares the expected value signal 40 with the comparator input signal 14 and outputs the comparison result as a test result output. At this time, the expected value signal 40 and the comparator input signal 14
And the test result output becomes logic “1” indicating PASS, the expected value signal 40 and the comparator input signal 14
If they do not match, the logic becomes "0" indicating FAIL.

In the pattern 2, the period from the rising edge of the inversion control signal to the rising edge of the test clock 19 is the address setup period. The test clock 19 is equal to φP output from the PLL circuit 3, and the inversion control signal 100 is equal to φN. Therefore, the address setup period of the pattern 2 is equivalent to one stage of the inverted logic gate, and is equal to the address setup period tAS required by the memory unit 22. The inversion control signal 200 is φ
Therefore, the write enable hold period of the pattern 2 is equal to two stages of the inverted logic gates, and is equal to the write enable hold period tWH required by the memory unit 22. Further, since the latch clock 400 is equal to φ1,
The output data latch timing of the pattern 2 is delayed by one stage of the inverted logic gate from the rising timing of the test clock 19, and is equal to the data access time tACC required by the memory unit 22.

At the time of the read operation of the pattern 2, the memory section 22
Does not satisfy the required read timing such as the setup period and the hold period, the pattern 2 is read from an incorrect address. Further, when the data access time required for the memory unit 22 is not satisfied, incorrect data is input to the comparator 7.

As described above, in this example, a plurality of different timing signals output from the timing selection circuit 4a are further supplied as control signals for the inverters 8a to 8c.

As a result, the self-test apparatus 1b transmits the test signals of the test address 18, the test input data 21, and the test write enable signal 20 to the timing selection signal 15
a to 15c can be supplied to the memory unit 22 at different output timings, and by providing an appropriate timing selection signal, the self-test apparatus 1b enables the self-test apparatus 1b to have the same timing specifications as those required for the memory unit 22. Test signals can be output under certain conditions.

Therefore, a test signal is output from the self-test apparatus 1b under the same conditions as the timing specifications required for the memory unit 22, and a read operation and a write operation to the memory unit 22 are performed. It is possible to confirm whether or not the required timing specifications are satisfied based on the PASS or FAIL state of the test result signal output from the comparator 7.

Further, in this embodiment, the output data signal input to the comparator 7 is latched by the latch clock 400 supplied from the timing selection circuit 4a, and the latched output data 14 is supplied to the comparator 7. Therefore, it is possible to set the timing at which the output data of the memory unit 22 is taken into the comparator 7.

As a result, a latch clock having a timing equivalent to the data access time tACC required for the memory unit 22 is selected, and data access is determined depending on whether output data during a read operation of the memory unit 22 can be normally latched. Time can be tested. If the latched output data is normal, the comparator 7 outputs PASS. If the latched output data is abnormal, the comparator 7 outputs FAIL.
Is output.

Therefore, the memory section 22 is determined by the PASS or FAIL state of the test result signal output from the comparator 7.
The data access time can be confirmed.

[0110]

Since the built-in self-test device for a memory circuit according to the present invention is constructed as described above, a high-speed LS
Without using an I tester, it is possible to test timing specifications such as a setup time and a hold time specified for a memory circuit under test.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first specific example of a built-in self-test device for a memory circuit according to the present invention.

FIG. 2 is a detailed configuration diagram of the PLL circuit of FIG. 1;

FIG. 3 is a diagram showing the timing of each signal in FIG. 2;

FIG. 4 is a detailed configuration diagram of a timing selection circuit of FIG. 1;

FIG. 5 is a detailed configuration diagram of the comparator of FIG. 1;

FIG. 6 is a detailed configuration diagram of the inverter of FIG. 1;

FIG. 7 is a timing chart for explaining the operation of the first specific example;

FIG. 8 is a block diagram of a second specific example of the present invention.

FIG. 9 is a detailed configuration diagram of a timing selection circuit according to a second specific example.

FIG. 10 is a timing chart for explaining the operation of the second specific example;

FIG. 11 is a block diagram of a conventional technique.

FIG. 12 is a timing chart for explaining the operation of FIG. 11;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Self-test apparatus 2 Sequence control circuit 3 PLL circuit 4 Timing selection circuit 5 Address generator 6 Data generator 7 Comparator 8a-8c Inverter 13 Data generator output signal 14 Comparator input signal 18 Test address 19 Test clock 20 Test Write enable 21 Test input data 22 Memory unit 23 Clock synchronous memory 24a to 24d Selector 40 Expected value signal 41 Address control signal 42 Data control signal 100, 200, 300, 400 Inversion control signal φ0 to φN Timing signal

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA07 AB01 AB06 AC03 AC09 AD06 AD07 AE07 AE08 AE10 AE11 AG03 AG07 AH03 AK01 AL02 5B018 GA03 HA31 JA12 JA21 MA01 PA01 5L106 DD22 DD23 GG03 GG05 GG07 9A001 BB03 BB06 LL

Claims (8)

[Claims] 1. A sequence control circuit comprising a memory circuit and a built-in self-test device for the memory circuit, the sequence control circuit receiving a clock and a test start signal and outputting a control signal; , An address generator for generating an address signal and outputting the address signal to the memory circuit; a data generator for receiving the control signal to generate test data and outputting the test data to the memory circuit; The output test data and the output data read and written after the memory circuit is supplied with the test data are given and compared, and a comparison result as to whether the test data is different from the output data A built-in self-test device for a memory circuit comprising a comparator for outputting a plurality of timing signals having a predetermined phase difference. A PLL circuit to generate; a timing signal selection circuit to select a predetermined timing from a plurality of timing signals generated by the PLL circuit; and a memory at a rising or falling timing of a control signal output from the timing selection circuit. A built-in self-test device for a memory circuit, comprising: an inverter for inverting a signal under test applied to the section. 2. The built-in memory for a memory circuit according to claim 1, wherein the signal under test output from the sequence control circuit is a write enable signal for controlling writing / reading of the memory circuit. Testing equipment. 3. The built-in memory circuit according to claim 1, wherein the signal under test output from the inverter is an address signal indicating an address of the memory circuit. Self test equipment. 4. The built-in self-test device for a memory circuit according to claim 1, wherein the signal under test output from the inverter is a write data signal of the memory circuit. . 5. The built-in self-test device for a memory circuit according to claim 1, wherein the signal under test output from the inverter is a write enable signal for the memory circuit. . 6. A latch according to claim 1, further comprising a latch for latching read data read from said memory circuit based on a second control signal output from said timing selection circuit. A built-in self-test device for the described memory circuit. 7. The built-in self-test device for a memory circuit according to claim 1, wherein said inverter is constituted by an exclusive OR circuit. 8. The PLL circuit includes: a phase comparison circuit that detects a phase difference between an oscillation clock of a voltage controlled oscillator of the PLL circuit and an external clock; and a voltage comparison circuit that detects the voltage difference based on the phase difference detected by the phase comparison circuit. A charge pump circuit that controls the input voltage to the control oscillator, and a voltage control oscillator in which N stages of inverting logic gates whose current drive capability can be controlled are connected in a ring shape, and the inverter or 8. The built-in self-test device for a memory circuit according to claim 1, wherein a control signal for latch control is extracted.