JPH11312400A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable performing output monitoring of a high speed semiconductor device even for a test device of which operation is slow. SOLUTION: This circuit is provided with a clock synchronizing type memory 20 receiving a control signal CTL, an address signal ADR and a data input DI, and supplying an internal data output IDOUT, an internal clock generating circuit 30 generating an internal clock signal ICLK1 having higher frequency than an external clock signal CLK, a clock selecting circuit 40 selecting either of the external clock signal CLK and the internal clock signal ICLK1 and supplying it to the clock synchronizing type memory 20, a data output conversion circuit 50 converting internal data output IDOUT to an external data output DOUT synchronizing with a clock signal having a lower frequency than the internal clock signal ICLK1, and a data output selection circuit 60 selecting either of the internal data output IDOUT and the external data output DOUT and outputting it.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit (semiconductor device) that can be inspected even when it operates faster than the operation of an inspection apparatus.

2. Description of the Related Art Conventionally, an inspection technique called dynamic burn-in for aging a semiconductor device has been known. According to this technique, in order to exclude a device which causes a failure depending on time and stress, screening is performed at a constant temperature by applying a power supply voltage exceeding a rated voltage to the device and applying an input signal close to normal operation to the device. I do. The monitored burn-in device is an inspection device having a device output monitoring (monitoring / observation) function in addition to the dynamic burn-in function. In recent years, the speed of operation of semiconductor devices has been increased, and the maximum operating frequency has been increased. JP-A-6
According to the technique disclosed in Japanese Patent Application Publication No. 187797, the frequency of the external clock signal is increased inside the device so that the inspection device having a slow operation can inspect the high-speed memory device. An address signal synchronized with the clock signal is generated. However, there is no disclosure concerning monitoring of device output in the publication.

According to the above-described monitored burn-in apparatus, monitoring of the device output is repeatedly performed at predetermined time intervals. However, during monitoring, the power supply voltage of the device is reduced to the rated voltage, so that the voltage stress is reduced. Therefore, there is a strong demand for reducing the time required for each monitoring. For this purpose, it is desirable that a device capable of high-speed operation be operated at high speed even during output monitoring during burn-in as in normal operation. However, conventionally, due to various restrictions on the inspection apparatus side, even a device capable of high-speed operation is actually operated at low speed during output monitoring under burn-in. Monitoring of device output is indispensable even in the function test of high-speed devices. However, conventionally, this could not be realized with a slow-operation inspection apparatus. An object of the present invention is to enable output monitoring of a high-speed device even with a slow-moving inspection apparatus.

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention reduces the rate of change of the output of a high-speed device within the device so that a signal having a low rate of change is output from the device. It is designed to be able to output. According to one aspect, a semiconductor device according to the present invention includes a functional circuit for outputting data at a first frequency in synchronization with a clock signal, and a functional circuit for outputting data at a second frequency lower than the first frequency. Data holding means for taking in and holding the first data from the functional circuit in the first cycle of the first frequency cycle in the first cycle;
Data capturing means for capturing the second data from the functional circuit in a second cycle after the first cycle in the cycle of the frequency of (i), and the held first data and the captured second data. And a data output conversion means for generating third data based on the data and outputting the third data at a second frequency. According to this configuration, of the data output of the first frequency of the functional circuit, the first data in a certain period and the second data in another period are provided to the data output conversion unit. The data output converter outputs the third data generated based on the two data at a second frequency lower than the first frequency. Therefore, the output monitoring of the device is
It can be performed even with a slow-moving inspection device. For efficient output monitoring by the inspection device, the data output conversion means determines that the number of states that the third data can take is the number of states that the first data can take and the number of states that the second data can take. Transform the data to be less than the number of any combination of. According to another aspect, a semiconductor device according to the present invention is a device having a normal operation mode and a test mode, comprising: a functional circuit for supplying a binary logic signal that changes at a certain frequency; A conversion circuit for converting the binary logic signal supplied from the above into a multi-valued logic signal that changes at a frequency lower than the change frequency of the binary logic signal, and a binary logic signal supplied from the functional circuit in the normal operation mode. In the test mode, a configuration is employed in which a signal is selected in the test mode from an output selection circuit for selecting a multi-valued logic signal as a signal to be output from the device. The multi-valued logic signal is, for example, a three-valued logic signal having a high impedance state representing a third logic value in addition to a high level representing a logic value 1 and a low level representing a logic value 0. is there. According to this configuration, the output monitoring of the device can be executed even by an inspection apparatus that operates slowly. Moreover, the amount of information (first information rate) output per unit time by the multi-level logic signal in the inspection mode is changed by the amount of information output per unit time by the binary logic signal (the first information rate) in the normal operation mode. 2 information rate). However, it is also possible to select the number of logic values of the multi-valued logic signal and its change frequency so that the second information rate is lower than the first information rate.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor integrated circuit according to the present invention will be described with reference to the drawings. The following description is
Synchronous DRAM (dynamic random access memor
y) and the like when the present invention is applied to a clock synchronous memory. FIG. 1 shows a configuration example of a semiconductor integrated circuit (semiconductor device) according to the present invention. In FIG. 1, reference numeral 10 denotes a clock synchronous memory 2 similar to the conventional one.
0 is a semiconductor device. The clock synchronous memory 20 includes a control signal CTL, an address signal ADR, and a data input DI received from outside the device 10 and an external clock signal CLK or an internal clock signal ICLK1 received through the clock selection circuit 40, respectively.
And a function circuit for supplying the internal data output IDOUT. Internal clock generation circuit 30
During an inspection, an external clock signal CLK is output based on an external clock signal CLK and a delayed external clock signal DCLK received from an inspection apparatus in response to an inspection control signal TEST received from outside the device 10.
Internal clock signal ICLK1 having a higher frequency than
Is a circuit means for generating. Clock selection circuit 4
0 selects one of the internal clock signal ICLK1 and the external clock signal CLK received from outside according to the received test control signal TEST, and supplies the selected clock signal to the clock synchronous memory 20. Circuit means. The data output conversion circuit 50 converts the internal data output (binary logic signal) IDOUT that changes at a certain frequency in response to the received test control signal TEST into the external data output (binary logic signal) that changes at a lower frequency than the binary logic signal. 3
(Value logic signal) DOUT. Specifically, the data output conversion circuit 50 synchronizes with the external clock signal CLK or a clock signal equivalent thereto based on the internal data output IDOUT supplied in synchronization with the internal clock signal ICLK1 from the clock synchronous memory 20. The generated external data output DOUT is generated. The data output selection circuit 60 receives the test control signal TE
This is a circuit means for selecting one of the external data output DOUT and the internal data output IDOUT in accordance with ST and supplying the selected data output to the outside of the device 10 as the data output DO. Semiconductor device 10 of FIG.
Will be described. For normal operation,
The external clock signal CLK is supplied to the clock synchronous memory 20 via the clock selection circuit 40 as it is.
Then, the internal data output IDOU supplied from the clock synchronous memory 20 in synchronization with the external clock signal CLK
T is output to the device 10 via the data output selection circuit 60.
Is output as it is as a data output DO. Next, an operation of the semiconductor device 10 when an inspection is performed using a low-speed operation inspection apparatus will be described with reference to FIGS. FIG. 2 shows the clock generation circuit 30 in FIG.
The operation of FIG. As shown in FIG. 2, the inspection apparatus generates an external clock signal CLK having a period T and a delayed external clock signal DCLK whose phase is delayed by T / 4 with respect to the external clock signal CLK. Then, as shown in FIG. 1, the generated external clock signal CLK and the delayed external clock signal DCLK are supplied to the device under test 10, respectively. In FIG. 1, at the time of inspection, an inspection control signal T
EST becomes active. As a result, the internal clock generation circuit 30
EX and EX based on the delayed external clock signal DCLK.
The internal clock signal I is generated by OR (exclusive OR) logic.
CLK1 is generated. As shown in FIG. 2, the frequency of the internal clock signal ICLK1 is
Becomes twice the frequency of the external clock signal CLK supplied to the external clock signal CLK. Next, the generated internal clock signal ICLK1 is supplied to the clock synchronous memory 2 via the clock selection circuit 40.
0. Therefore, internal data output IDOU
T is supplied from the clock synchronous memory 20 in synchronization with the internal clock signal ICLK1 having a frequency twice that of the external clock signal CLK. If the supplied internal data output IDOUT is to be inspected by the inspection device as it is, the operating frequency of the inspection device must be twice the external clock signal CLK. Therefore, the clock synchronous memory 20 is operated by the internal clock signal ICLK1 having a frequency twice as high as that of the external clock signal CLK, and the operation result is transmitted to the external clock signal CLK.
It is necessary that the inspection can be performed by an inspection device using a hologram. For this purpose, the device 10 of the present embodiment
Has a data output conversion circuit 50 for degenerating the internal data output IDOUT in the time axis direction. FIG.
2 shows a detailed configuration example of the data output conversion circuit 50 in FIG. In FIG. 3, a frequency dividing circuit 51 is controlled by a test control signal TEST, divides the received internal clock signal ICLK1, and divides the frequency of the received internal clock signal ICLK1 by one half (double the period). Is a circuit means for generating. The EXOR circuit 52 includes an internal data output IDOUT and a divided internal clock signal ICL.
It is a comparison means for supplying a comparison result signal CMP formed of an exclusive OR with K2. Timing generator 53
Is a circuit means for supplying first and second timing signals PH1 and PH2 which are controlled by the test control signal TEST and whose frequency-divided internal clock signal ICLK2 is respectively delayed by a predetermined time. The first timing signal PH1 and the second timing signal PH2 are signals for determining the timing in the first half and the second half of one cycle of the divided internal clock signal ICLK2, respectively. The D flip-flop 54 is circuit means for latching the received comparison result signal CMP and supplying the first half data DF in response to the first timing signal PH1 received as a clock input. D flip-flop 5
Reference numeral 5 denotes circuit means for latching the received first half data DF and supplying the delayed first half data DDF in response to the second timing signal PH2 received as a clock input. Both D flip-flops 54 and 55 take in the first data from the clock synchronous memory 20 during the period specified by the first timing signal PH1, and hold and output this during the period specified by the second timing signal PH2. And a data holding means for performing the operation. The D flip-flop 56 is a circuit means for latching the received comparison result signal CMP and supplying the second half data DL in response to the second timing signal PH2 received as a clock input. A data fetching means for fetching the second data from the clock synchronous memory 20 during the designated period and holding and outputting the second data is constituted. EX
The OR circuit 57 receives the delayed first half data D
It is a comparison means for supplying a buffer control signal ENA consisting of an exclusive OR of DF and second half data DL. Three-state output buffer 58 provides buffer control signal E
This is an output buffer for outputting the delayed first half data DDF as it is or for setting the output to high impedance (“Hi-Z”) according to the NA. Data output conversion circuit 5
The operation of 0 will be described with reference to FIGS.
FIG. 4 is a timing chart showing the operation of the data output conversion circuit 50 of FIG. An internal clock signal ICLK1 generated based on the external clock signal CLK and a delayed external clock signal DCLK (not shown) is frequency-divided by a frequency dividing circuit 51 using a toggle flip-flop or the like to generate a frequency-divided internal clock signal ICLK2. Generate. As shown in FIG. 4, the divided internal clock signal ICLK2 has a waveform equivalent to that of the external clock signal CLK. In some cases, an external clock signal CLK may be used instead of the divided internal clock signal ICLK2. The EXOR circuit 52 outputs the divided internal clock signal ICLK2 and the internal data output IDOU.
T and supplies a comparison result signal CMP. The comparison result signal CMP becomes a low level “L” when the level between the divided internal clock signal ICLK2 and the internal data output IDOUT is “match”, and becomes a high level “H” when the level does not match. That is, the comparison result signal CMP is a signal indicating whether the divided internal clock signal ICLK2 and the internal data output IDOUT are "matched" or "mismatched" at a certain point in time of the divided internal clock signal ICLK2. For example, if the internal clock signal ICLK1 is "0",
As in the case of repeatedly changing to “1”, the internal data output IDOUT is output every cycle of the internal clock signal ICLK1.
Is repeatedly changed to “0” and “1”,
Since the two inputs of the EXOR circuit 52 are always “matched”,
The comparison result signal CMP always maintains a constant “L” level. In contrast to the internal clock signal ICLK1 repeatedly changing to "0" and "1", the internal clock signal ICLK
The internal data output IDOUT is “1” every one cycle of 1,
In the case of repeatedly changing to "0", since the two inputs of the EXOR circuit 52 are always "mismatch", the comparison result signal CMP always maintains a constant "H" level. Upon receiving the first timing signal PH1 as a clock input, the D flip-flop 54 outputs the divided internal clock signal I
The comparison result signal CMP is latched in the first half of each cycle T1, T2,..., T4,... Of the CLK2, and in the first half of each cycle, the divided internal clock signal ICLK2 and the internal data output IDOUT are "matched" or "mismatched". Is supplied. Similarly, the D flip-flop 56 that has received the second timing signal PH2 as a clock input generates a signal TCLK for each period T of the divided internal clock signal ICLK2.
, T4,..., T4, latch the comparison result signal CMP in the latter half, and divide the internal clock signal ICL in the latter half of each cycle.
The second half data DL indicating whether K2 and the internal data output IDOUT are "match" or "mismatch" is supplied.
Also, the first half data DF latched in the first half of each cycle,
In order to compare the second half data DL latched in the second half of each cycle, the D flip-flop 55 supplies delayed first half data DDF, which is delayed first half data DF, in accordance with the second timing signal PH2. EXOR circuit 57
Supplies a buffer control signal ENA consisting of an exclusive OR of the first half data DDF and the second half data DL. Therefore, the first half data DF and the second half data DL are compared at the same timing. Three-state output buffer 58 receives buffer control signal EN
When A is “H” (disable), the output is set to high impedance (“Hi-Z”), and when “L” (enable), the output is set to low impedance and the received first half data DDF received is Output as is. The output of the three-state output buffer 58 is connected to the external data output DOU supplied from the data output conversion circuit 50.
It becomes T. FIG. 5 shows the data output conversion circuit 50.
Divided internal clock signal ICLK2 and internal data output ID
7 shows the relationship between the comparison result with OUT and the external data output DOUT. As shown in FIG. 5, when the level of frequency-divided internal clock signal ICLK2 and internal data output IDOUT match in both the first half and the second half of the cycle of frequency-divided internal clock signal ICLK2 (in the case of T4 in FIG. 4) ), The external data output DOUT becomes “0”. On the other hand, if there is a mismatch between the first half and the second half (T2 in FIG. 4), the external data output DOUT becomes “1”. The external data output DOUT is both high impedance (“1” in the case of a match in the first half and mismatch in the second half (T1 in FIG. 4) and “2” in the case of mismatch in the first half and match in the second half (T3 in FIG. 4). Hi-Z ")
become. Although there are four possible combinations of the state of the internal data of the first half of the divided internal clock signal ICLK2 and the state of the internal data of the second half of the divided internal clock signal ICLK2, the state of the external data output DOUT is “0”. ,
“1” and “Hi-Z” are used. In this manner, the internal data output IDOUT is converted into the external data output DOUT having a half frequency (double the period). In addition, both the case of the first half match and the latter half mismatch and the case of the first half mismatch and the latter half match both the external data output D
When OUT = “Hi-Z”, degeneration occurs. As an example of the inspection pattern, consider a stripe pattern in a monitored burn-in device. A stripe pattern in which data repeats “0” and “1” every cycle is written to and read from the clock synchronous memory 20. When the clock synchronous memory 20 is operating normally, that is, when the internal data output IDOUT synchronized with the internal clock signal ICLK1 is the same as the expected value prepared by the inspection apparatus in advance according to the stripe pattern, Since the condition of “match in the first half and match in the second half” or “match in the first half and mismatch in the second half” of FIG. 5 is always satisfied, the external data output DOUT always maintains a constant value “0” or “1”. . On the other hand, in the stripe pattern, when the internal data output IDOUT becomes “0”, “0” or “1”, “1” (in the case of T3 or T1 in FIG. 4, respectively), the external data output DOUT becomes high. Since the impedance becomes “Hi-Z”, an operation failure of the clock synchronous memory 20 can be determined. As described above, according to the semiconductor device of FIG. 1, the output of two cycles of the functional circuit operating with the clock signal having the high frequency is output in correspondence with one cycle of the clock signal having the low frequency. Thus, the operation of the functional circuit can be inspected by using the inspection device that operates at a low speed. Therefore, since the functional circuit itself is operated by the clock signal having a high frequency to test the functional circuit, the inspection time can be reduced and the inspection cost can be reduced. Further, since it is not necessary to provide a clock signal having a high frequency in the inspection apparatus, the apparatus cost can be reduced. In the above description, the test apparatus generates the delayed external clock signal DCLK delayed by 1/4 cycle with respect to the external clock signal CLK. May be generated inside the. The timing of this delayed clock signal (corresponding to the delayed external clock signal DCLK in FIG. 2) is, as shown in FIG.
The phase delay does not necessarily have to be 1/4 cycle because it only affects the duty ratio of CLK1 and does not affect its cycle. The logic of the data output conversion circuit 50 is not limited to that shown in FIG. The circuit may be configured to output only two levels of “H” and “L” without using the high impedance state. Also, EXO in FIG.
Omitting the arrangement of the R circuit 52, the internal data output IDOU
T may be directly supplied to the D flip-flops 54 and 56. FIG. 6 shows another configuration example of the semiconductor integrated circuit (semiconductor device) according to the present invention. In FIG. 6, 10a is a so-called DDR (double data rat).
e) having a clock synchronous memory 20a for performing an operation;
It is a semiconductor device. Clock synchronous memory 20a
Operate based on a control signal CTL, an address signal ADR, a data input DI, and an external clock signal CLK received from the outside of the device 10a, respectively, and are synchronized with both rising and falling edges of the external clock signal CLK. This is a functional circuit for supplying the internal data output IDOUT. The data output conversion circuit 50a outputs the internal data output (binary logic signal) IDOUT that changes at a certain frequency in response to the received test control signal TEST.
A circuit means for converting an external data output (ternary logic signal) DOUT which changes at a lower frequency than the value logic signal. Specifically, the data output conversion circuit 50a synchronizes with the external clock signal CLK or a clock signal equivalent thereto based on the internal data output IDOUT supplied in synchronization with the external clock signal CLK from the clock synchronous memory 20a. The generated external data output DOUT is generated. The data output selection circuit 60a receives the test control signal T
A circuit means for selecting one of the external data output DOUT and the internal data output IDOUT in accordance with the EST, and supplying the selected data output to the outside of the device 10a as the data output DO. The operation of the semiconductor device 10a in FIG. 6 will be described. When performing a normal operation, the internal data output IDOU supplied from the clock synchronous memory 20a in synchronization with the external clock signal CLK
T is the device 1 via the data output selection circuit 60a.
0a is output as it is as data output DO. Next, the operation of the semiconductor device 10a when an inspection is performed using a low-speed operation inspection apparatus will be described with reference to FIGS. FIG. 7 shows a detailed configuration example of the data output conversion circuit 50a in FIG. In FIG. 7, an EXOR circuit 52 is a comparison unit for supplying a comparison result signal CMP formed by an exclusive OR of the internal data output IDOUT and the external clock signal CLK. The timing generator 53 is controlled by the test control signal TEST, and the first and second timing signals PH1 and PH1, in which the external clock signal CLK is delayed by a predetermined time, respectively.
Circuit means for supplying PH2. The first timing signal PH1 and the second timing signal PH2 are signals for determining the timing in the first half and the second half of one cycle of the external clock signal CLK, respectively. The D flip-flop 54 is circuit means for latching the received comparison result signal CMP and supplying the first half data DF in response to the first timing signal PH1 received as a clock input. D flip-flop 5
Reference numeral 5 denotes circuit means for latching the received first half data DF and supplying the delayed first half data DDF in response to the second timing signal PH2 received as a clock input. The D flip-flops 54 and 55 take in the first data from the clock synchronous memory 20a during the period specified by the first timing signal PH1,
This constitutes a data holding means for holding and outputting this during a period designated by the second timing signal PH2. The D flip-flop 56 is a circuit means for latching the received comparison result signal CMP and supplying the second half data DL in response to the second timing signal PH2 received as a clock input. A data fetching means for fetching the second data from the clock synchronous memory 20a during a designated period and holding and outputting the second data is constituted. E
The XOR circuit 57 is a comparing means for supplying a buffer control signal ENA formed by an exclusive OR of the received first half data DDF and second half data DL.
The three-state output buffer 58 is an output buffer for outputting the delayed first half data DDF as it is or for setting the output to high impedance (“Hi-Z”) according to the buffer control signal ENA. Data output conversion circuit 5
The operation at 0a will be described with reference to FIG. FIG.
FIG. 8 is a timing chart illustrating the operation of the data output conversion circuit 50a of FIG. The EXOR circuit 52 receives the external clock signal CLK and the internal data output IDOUT, and supplies a comparison result signal CMP. Comparison result signal C
MP is an external clock signal CLK and an internal data output ID.
If the level with OUT is “match”, the level becomes low level “L”, and if the level does not match, the level becomes high level “H”.
That is, the comparison result signal CMP corresponds to the external clock signal CL.
A signal indicating whether the external clock signal CLK and the internal data output IDOUT are "matched" or "mismatched" at a certain point of K. D flip-flop 5 receiving first timing signal PH1 as a clock input
4 is each cycle T1, T2, of the external clock signal CLK.
, T4, latch the comparison result signal CMP in the first half,
In the first half of each cycle, the first half data DF indicating whether the external clock signal CLK and the internal data output IDOUT are “match” or “mismatch” is supplied. Similarly, the D flip-flop 56 that has received the second timing signal PH2 as a clock input outputs the comparison result signal CM in the latter half of each cycle T1, T2,.
And latches the external clock signal CLK in the latter half of each cycle.
And the internal data output IDOUT are supplied with the latter half data DL indicating whether it is “match” or “mismatch”. Further, in order to compare the first half data DF latched in the first half of each cycle with the second half data DL latched in the second half of each cycle, the D flip-flop 55 delays in accordance with the second timing signal PH2. It supplies the delayed first half data DDF which is the first half data DF obtained. EXOR circuit 57
Supplies a buffer control signal ENA consisting of an exclusive OR of the first half data DDF and the second half data DL. Therefore, the first half data DF and the second half data DL are compared at the same timing. Three-state output buffer 58 receives buffer control signal EN
When A is “H” (disable), the output is set to high impedance (“Hi-Z”), and when “L” (enable), the output is set to low impedance and the received first half data DDF received is Output as is. The output of the three-state output buffer 58 is supplied to the external data output DO supplied from the data output conversion circuit 50a.
UT. As described above, according to the semiconductor device of FIG. 6, during normal operation (DDR operation), data that changes in synchronization with both rising and falling edges of the external clock signal CLK is output. Since the frequency of change of output data is sometimes reduced by half, the operation of the functional circuit can be inspected using a low-speed operation inspection device. Therefore, the cost of the inspection device can be reduced. Note that the data output conversion circuit 50a does not use the high impedance state,
The circuit may be configured to output only two levels of “H” and “L”. The arrangement of the EXOR circuit 52 in FIG. 7 may be omitted, and the internal data output IDOUT may be directly supplied to the D flip-flops 54 and 56. The case where the present invention is applied to the clock synchronous memory has been described above. However, the present invention is applicable not only to the memory but also to other devices as long as the device has a functional circuit that outputs data in synchronization with a clock signal. Can be applied.
Further, the present invention can be applied not only to monitoring of a device output by a monitored burn-in device but also to a general function inspection scene.

As described above, according to the present invention, the change frequency of the output of a high-speed device is reduced inside the device, so that a signal having a low change frequency can be output from the device. Therefore, an effect is obtained that the output of the device can be monitored even with a slow-moving inspection device. Thereby, the cost of the inspection device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a timing chart showing an operation of the internal clock generation circuit in FIG.

FIG. 3 is a circuit diagram showing a detailed configuration example of a data output conversion circuit in FIG. 1;

FIG. 4 is a timing chart illustrating an operation of the data output conversion circuit of FIG. 3;

FIG. 5 is a diagram for explaining an output of the data output conversion circuit of FIG. 3;

FIG. 6 is a block diagram showing another configuration example of the semiconductor integrated circuit according to the present invention.

FIG. 7 is a circuit diagram showing a detailed configuration example of a data output conversion circuit in FIG. 6;

FIG. 8 is a timing chart showing an operation of the data output conversion circuit of FIG. 7;

[Explanation of symbols]

10, 10a Semiconductor integrated circuit (semiconductor device) 20, 20a Clock synchronous memory (functional circuit) 30 Internal clock generation circuit (clock generation means) 40 Clock selection circuit (clock selection means) 50, 50a Data output conversion circuit (data output) Conversion means) 51 frequency dividing circuit (frequency dividing means) 52 EXOR circuit (first comparing means) 53 timing generator 54, 55, 56 D flip-flop 57 EXOR circuit (comparing means, second comparing means) 58 three-state Output buffer 60, 60a Data output selection circuit (data output selection means) ADR address signal CLK external clock signal CMP comparison result signal CTL control signal DCLK delayed external clock signal DDF delay first half data DF first half data DI data input DL second half data DO data output DOUT external data output (third data) ENA buffer control signal ICLK1 internal clock signal ICLK2 frequency-divided internal clock signal IDOUT internal data output (first and second data) PH1, PH2 timing signal TEST test control signal

Claims (13)

[Claims] 1. A function circuit for outputting data at a first frequency in synchronization with a clock signal, and a cycle of the first frequency in one cycle of a second frequency lower than the first frequency. A data holding unit for taking in and holding first data from the functional circuit in a first cycle, and a second data cycle after the first cycle in the cycle of the first frequency in the one cycle. Data capturing means for capturing second data from the functional circuit in a second cycle; generating third data based on the held first data and the captured second data; A semiconductor integrated circuit comprising: a data output converter for outputting at a second frequency. 2. The semiconductor integrated circuit according to claim 1, wherein the data output conversion means determines whether the number of states that the third data can take is the number of states that the first data can take and the number of states that the second data can take. A semiconductor integrated circuit that converts data so that the number of combinations is smaller than the number of possible combinations of states. 3. The semiconductor integrated circuit according to claim 1, wherein the data output from the functional circuit at the first frequency when the semiconductor integrated circuit operates normally based on the received test control signals. Further comprising a data output selecting means for supplying the third data as a data output to the outside of the semiconductor integrated circuit when the semiconductor integrated circuit is inspected. circuit. 4. The semiconductor integrated circuit according to claim 1, wherein said functional circuit synchronizes data with a frequency twice as high as a frequency of said clock signal in synchronization with both a rising edge and a falling edge of said clock signal. A semiconductor integrated circuit, which outputs the following. 5. The semiconductor integrated circuit according to claim 4, wherein said second frequency is equal to a frequency of said clock signal. 6. The semiconductor integrated circuit according to claim 1, wherein said data output conversion means includes a comparison means for comparing said first data with said second data. Integrated circuit. 7. The semiconductor integrated circuit according to claim 1, further comprising: receiving an external clock signal from outside the semiconductor integrated circuit, and generating an internal clock signal having the first frequency based on the external clock signal. A clock generation unit, based on the test control signals received, when the semiconductor integrated circuit is tested, the internal clock signal;
And a clock selecting unit for supplying the external clock signal to the functional circuit when the semiconductor integrated circuit operates normally. 8. The semiconductor integrated circuit according to claim 7, wherein said data output conversion means divides said internal clock signal to generate a divided internal clock signal having said second frequency. Means, first comparing means for comparing a logical value of data received from the functional circuit with a logical value of the frequency-divided internal clock signal, and the first and second cycles in the first cycle and the second cycle. A semiconductor integrated circuit comprising: a second comparing unit for comparing outputs of the first comparing unit. 9. The semiconductor integrated circuit according to claim 1, wherein said functional circuit is a clock synchronous memory. 10. A semiconductor integrated circuit having a normal operation mode and a test mode, comprising: a functional circuit for supplying a binary logic signal that changes at a certain frequency; and the binary logic supplied from the functional circuit. A conversion circuit for converting a signal into a multi-valued logic signal that changes at a lower frequency than the change frequency of the binary logic signal; and a conversion circuit that converts the binary logic signal in the normal operation mode and the multi-valued signal in the test mode. An output selection circuit for selecting a logic signal as a signal to be output from the semiconductor integrated circuit. 11. The semiconductor integrated circuit according to claim 10, wherein the semiconductor integrated circuit sets a first frequency in the normal operation mode, and sets a second frequency lower than the first frequency in the test mode. A clock generation circuit for receiving an external clock signal having an external clock signal and generating an internal clock signal having a frequency higher than the second frequency from the external clock signal in the test mode; A clock selection circuit for selecting a clock signal as a clock signal to be supplied to the functional circuit in the test mode, wherein the clock supplied from the clock selection circuit is further provided. Same as either rising edge or falling edge of signal The semiconductor integrated circuit and supplying a signal which varies in as said binary logic signal. 12. The semiconductor integrated circuit according to claim 10, wherein the functional circuit sets a signal that changes in synchronization with both a rising edge and a falling edge of a given external clock signal as the binary logic signal. A semiconductor integrated circuit characterized by supplying. 13. The semiconductor integrated circuit according to claim 10, wherein said functional circuit is a clock synchronous memory.