JP3735696B2 - Test circuit and test method for semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a test circuit for a reliability test of a semiconductor memory device.
[0002]
[Prior art]
FIG. 1 is a block diagram showing a general synchronous memory test circuit. That is, a mode register 10 that controls the operation mode of the memory, a latency controller 20 that operates according to the output of the external clock CLK and the mode register 10 and generates a latency CL, the external clock CLK and the mode register 10 The internal column address generator 30 that generates the column address CAi from the address Ai, and the column that operates in accordance with the external clock CLK, decodes the column address CAi, and provides the column selection signal CSL to the memory array 50. An address decoder 40, an input / output control unit 60 that controls data input / output of the memory array 50 by operating according to the external clock CLK and the latency CL, and an output data from the input / output control unit 60 that operates according to the latency CL Data input / output terminal A data input buffer 80 for transmitting input data that is input from the data output buffer 70 and data input terminal DQ transmitted to Q to output control unit 60, are provided.
[0003]
[Problems to be solved by the invention]
Currently, solid state memory is developing in two directions. One is an increase in memory density, and the other is an increase in bandwidth, that is, an increase in operation speed. These two methods require a longer test time and appropriate test facilities, leading to an increase in test costs and a decrease in productivity.
[0004]
In the conventional test circuit having the configuration shown in FIG. 1, various effective methods for increasing the memory density have been proposed. For this reason, the test corresponding to a high-density memory is possible by using the existing test equipment as it is with a slight change. However, in the case of high-speed memory, the effective situation is that most effective countermeasures have not been proposed yet, and the problem of the bandwidth of existing equipment cannot be solved, and there is a problem that high-frequency equipment must be newly provided. There is.
[0005]
SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a test circuit that makes it possible to test a high bandwidth memory with a low bandwidth test facility.
[0006]
[Means for Solving the Problems]
For this purpose, the present invention provides a mode register for controlling the operation mode, a Layton Sea controller for operating in accordance with the mode register to control the latencies of the clock frequency, and generating a column address by operating in accordance with the mode registers. An internal column address generator, a column address decoder for selecting a column of the memory array by decoding the column address, and an input / output control unit for controlling data input / output of the memory array by operating according to the Layton Sea controller And a data output buffer and a data input buffer for data input / output between the data input / output control unit and the outside, and control by multiplying the external clock provided from the outside by an integer Generating a clock, said Layton Sea controller, A frequency multiplier that synchronizes the column address generator, the column address decoder, and the input / output control unit; and a test control unit that determines a multiple (multiplication factor) of the frequency multiplier according to the mode register, Provided is a test circuit characterized in that it can operate at a frequency higher than that of an external clock.
[0007]
Accordingly, in the present invention, in a test method of a semiconductor memory device capable of multi-data input / output, data input in parallel according to an external clock is synchronized with a clock frequency obtained by increasing the external clock frequency in the memory chip. A test method characterized by writing as a large number of serial data is provided.
[0008]
The present invention is a technique that enables a memory having a high frequency operation to be tested even at a low frequency. That is, a memory that performs high-speed operation can be tested with an existing low-bandwidth test facility, test costs are reduced, and productivity of a high-bandwidth memory is improved.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.
[0010]
Here, a method of testing a synchronous DRAM (Synchronous Dynamic Random Access Memory: SDRAM) operating at a high bandwidth with a low bandwidth test facility is taken as an example. The features of this synchronous DRAM are as follows.
[0011]
[1]: Command and data input / output are controlled in synchronization with an external clock (system clock). [2]: In the read operation, the column address strobe (CAS) latency is set to CL, which clock number is used to read data after the read command is input, and the CL The memory frequency is determined according to the value. For example, CL1 = 33 MHz, CL2 = 66 MHz, CL3 = 100 MHz. [3]: Burst read, burst write (Burst write) According to the determined burst length, continuous data can be input / output. Possible burst lengths are 1, 2, 4 and 8 pull pages. Continuous (sequential) data changes in synchronization with the clock. [4]: CAS latency and burst length are determined by storing the key signal input from the address terminal at a specific timing in an internal register (mode register) and combining them. This value is maintained unless it is updated (updated) by programmable timing or powered off. That is, one memory can operate in various modes. In addition to these features, there are many features compared to other dynamic products.
[0012]
In the test circuit of this embodiment, a low-frequency clock equipped with a low-bandwidth test equipment is received and a high-frequency clock (an integer multiple of the input clock frequency) is generated in the circuit, and a high-bandwidth operation is performed accordingly. FIG. 2 shows a block diagram of the test circuit. That is, the frequency multiplier 100 implemented using the phase locked loop PLL and the delay locked loop DLL and the test control unit 200 for controlling the multiple are added to the conventional configuration shown in FIG.
[0013]
3A to 3C are waveform diagrams showing clock combinations at the time of testing.
[0014]
FIG. 3A shows the case where the CAS latency is CL1, and the maximum frequency at this time is 33 MHz. Therefore, it is only necessary to perform a test up to 33 MHz. However, when CL3 is reached, 100 MHz becomes the maximum frequency. Therefore, a test facility having a bandwidth capable of verifying such a frequency band is necessary for the test. Become. Therefore, the control clock φCLK is generated by using the frequency multiplier 100 and the external clock CLK is multiplied by an integer to cope with it. That is, as shown in FIG. 3B and FIG. 3C, the frequency multiplier 100 increases the frequency of the control clock φCLK by 2 times in the test in the case of CL2, and 3 times in the test in the case of CL3.
[0015]
As a result, the internal operation of the chip is the same as in the case of 66 MHz and 100 MHz, respectively, and if the data output is inspected at the rising edge (Rising Edge) with the clock CLK of the test equipment of 33 MHz, the test can be performed even on the existing equipment with low bandwidth. Is possible. However, in this case, since the output data DQ is output at 66 MHz and 100 MHz, data which is ignored without being inspected as shown by hatching in FIGS. 3B and 3C appears. In response to this, the output data DQ of all cells can be inspected by appropriate address scramble. An example is shown below.
[0016]
FIG. 4 shows the control timing of the column selection line CSL in the test mode. In the same figure, if a read or write command is performed every 33 MHz of the external clock CLK and one address is input, the chip operates internally at 100 MHz and is internally used during one cycle T1 (30 ns) of 33 MHz. Two more column addresses are generated. However, as shown in the figure, if the addresses are sequentially input in the order of [0] → [1] → [2] for each of the clocks (1), (2), and (3) of the external clock CLK, the column address [0-1-2] → [1-2-3] → [2-3-4]...
[0017]
In the case of the read operation, the chip outputs data output DQ corresponding to each of the three column addresses during one cycle T1 due to the operating condition of 100 MHz as shown in FIG. 3C. The two hatched output data DQ are not inspected. However, for example, the output data DQ that is not checked among the three output data DQ output in response to the address [0] is data corresponding to the addresses [1] and [2]. Since the addresses are input in 2 ▼ and 3), it can be inspected at this time. Therefore, the test can be performed even when the control clock φCLK has a higher frequency than the external clock CLK. The same applies to the case of FIG. 3B.
[0018]
As described above, in the case of reading, it is possible to test without problems if the addresses are sequentially input according to the clock CLK of the test equipment as usual. On the other hand, in the case of the writing operation, the input data DIN ( In addition to the valid data a, b, and c of DQ), there is invalid data such as a shaded portion, which is troublesome if it is written according to the internal additional column address. Therefore, the two column selection lines CSL (the one following in the 66 MHz test) following the column selection line CSL that is first enabled in each cycle are disabled, as in the portion A shown in the write CSL waveform. As a result, only valid data can be written.
[0019]
5 and 6 are a timing chart and a circuit block diagram showing a method of data scrambling in a multi-data output type memory. That is, in the case of a multi-data type having a large data width, a method of receiving data in parallel and writing it in series is possible in order to perform a write operation in accordance with an internally increased frequency. . As shown in FIG. 6, among data input buffers 801 to 803 that receive data DQ0 to 1 input in parallel, delay circuits 804 and 805 are provided for data input buffers 802 and 803, and delay circuit 804 has one cycle T1. The second clock of the control clock φCLK in the delay circuit 805 is configured to delay and output data with the third clock of the control clock φCLK in one cycle T1, and then DATA0, DATA1, DATA2 through the data input multiplexer. Is generated. Thus, assuming that data A0 is supplied to DQ0, data B0 is supplied to DQ1, and data C0 is supplied to DQ2 in accordance with the external clock CLK, DATA0, DATA1, and DATA2 are A0 in accordance with the control clock φCLK in the chip during one cycle T1, respectively. → B0 → C0 serial data.
[0020]
7 and 8 are circuit diagrams of the frequency multiplier 100 using DLL. As shown in the figure, the frequency of the external clock CLK can be multiplied by an integer by generating the divided clocks CCLK1 to CCLK5. Clocks CCLK1 to CCLK1 generated by the circuit of FIG. 7 are input to a multiplication factor controller 300 having the configuration of FIG. 8 and according to a multiplication factor m (in this case, m1 to m3) input from the test control unit 200. By combining them, the control clock φCLK is generated from the pulse generator 400. During normal operation, control clock φCLK is generated using CCLK5 according to multiplication factor m1, CCLK2 and CCLK5 are used according to multiplication factor m2 when doubled, and CCLK1 according to multiplication factor m3 when tripled. , CCLK3, CCLK5 are used to generate the control clock φCLK. The multiplication factor m is determined by the test control unit 200 according to the mode register 10, and the Layton Sea controller 20 and the internal column address generator 30 are controlled accordingly.
[0021]
When entering the test mode, the logic “high” of the address A7 in the conventional WCBR test mode is used. At this time, the addresses A1, A2, and A3 are used as external control signals, and the test control unit 200 is multiplied. Determine the value of the factor. If it is not the test mode, m1 is always set. By such a method, even if the frequency applied to the chip is low, a high frequency clock can be generated inside the chip (2 times and 3 times), and a high frequency characteristic test can be performed.
[0022]
【The invention's effect】
The present invention makes it possible to test a high bandwidth memory with a test facility having a low bandwidth. Therefore, it is not necessary to update the test equipment every time the frequency increases, and the productivity is improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a conventional test circuit.
FIG. 2 is a block diagram showing a test circuit according to the present invention.
FIG. 3 is a signal waveform diagram showing the relationship between an external clock, a control clock generated by a test circuit, and output data.
FIG. 4 is a signal waveform diagram showing control timing of a column selection line in a test mode.
FIG. 5 is a signal waveform diagram illustrating a data scramble method in a multi data type.
6 is a block diagram of a data input circuit for timing in FIG. 5;
FIG. 7 is a circuit diagram of a frequency multiplier using DLL.
FIG. 8 is a circuit diagram of a multiplication factor controller in FIG. 7;
[Explanation of symbols]
10 Mode Register 20 Layton Sea Controller 30 Internal Column Address Generator 40 Column Address Decoder 50 Memory Array 60 Input / Output Control Unit 70 Data Output Buffer 80 Data Input Buffer 100 Frequency Multiplier 200 Test Control Unit

Claims (2)

A mode register that controls the operating mode; and
A Layton Sea controller that operates according to the mode register to control the latencies of the clock frequency;
An internal column address generator that operates according to the mode register to generate a column address;
A column address decoder for decoding the column address to select a column of the memory array;
An input / output control unit that operates according to the Layton Sea controller to control data input / output of the memory array;
In a test circuit of a semiconductor memory device having a data output buffer and a data input buffer for data input / output between the data input / output control unit and the outside,
An externally provided external clock is multiplied by an integer to generate a control clock, and a frequency with a variable multiplication factor for synchronizing the latency controller, the column address generator, the column address decoder, and the input / output control unit is variable. A multiplier,
A test control unit for determining a multiple of the frequency multiplier according to the mode register;
With
The internal column address generator generates a column address according to the control clock, and one column address among the plurality of column addresses generated by the internal column address generator is enabled during a period of one cycle of the external clock. are other column address is disabled,
A test circuit characterized in that it can operate at a frequency higher than that of the external clock. In a test method of a semiconductor memory device capable of inputting / outputting data in parallel,
An external clock input from the outside to the semiconductor memory device is multiplied in the semiconductor memory device to generate a control clock,
The parallel data input from the outside to the semiconductor memory device according to the external clock is converted into serial data for writing synchronized with the control clock in the semiconductor memory device, and writing is performed.
A test method characterized by that.

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