JP3695902B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a write operation of a synchronous DRAM (Dynamic Randum Access Memory) having a 2-bit prefetch function, and more particularly to a semiconductor memory device capable of shortening a write time.
[0002]
[Prior art]
The synchronous DRAM receives an address, a control command, and the like from the system side that controls the memory in synchronization with the clock, and performs internal read and write operations in synchronization with the clock. As a result, the memory can be operated at high speed.
[0003]
Further, the synchronous DRAM has a burst mode function for accessing a column address given from the outside and a memory cell of the column address and the column address continuous thereto. In this burst mode, it is possible to read or write data by accessing memory cells at successive column addresses of 2 bits, 4 bits, and 8 bits according to the burst length from a given column address.
[0004]
In order to perform this burst mode more efficiently, a 2-bit prefetch function is provided. The 2-bit prefetch function latches a given column address or an internally generated first column address, and generates a second column address obtained by adding 1 bit to the first column address. The memory cell is accessed with the column address of. The memory cell array side includes an odd-numbered side memory cell array, a corresponding column address decoder and an output data holding circuit, and an even-numbered side memory cell array, a corresponding column address decoder and an output data holding circuit. When the first column address is an even number, the first column address is given to the even-numbered column address decoder, and the second column address is given to the odd-numbered column address decoder. When the first column address is odd, the first column address is given to the odd-numbered column address decoder and the second column address is given to the even-numbered column address decoder. Then, the even-numbered data is output to the outside, or the odd-numbered data and the even-numbered data are continuously output to the outside. Alternatively, in the case of writing, even-numbered data and odd-numbered data are sequentially written together with even-numbered first column addresses, or odd-numbered data and even-numbered data are written sequentially together with odd first column addresses.
[0005]
As described above, a synchronous DRAM generally receives a control signal and an address signal from the outside in synchronization with a clock, and internally performs various operations in synchronization with the clock.
[0006]
[Problems to be solved by the invention]
However, it is necessary to supply write data from the outside to the data input / output terminal (DQ terminal) of the memory during the write operation. The data input / output terminal has a large load capacity, unlike the input terminal for the command signal and address signal. The reason is that the input terminal for the command signal and address signal is an input-only terminal, so that only the input circuit is connected to the internal circuit. On the other hand, the data input / output terminal is connected to the output circuit together with the input circuit, and its load capacity increases.
[0007]
Therefore, the system side can provide a command signal and an address signal in synchronization with the clock relatively easily. However, when a write data signal is given to a data input / output terminal with a large load capacity, the data signal is rounded, so that the data signal is stored in the memory accurately in synchronization with the rising and falling edges of the clock. It becomes difficult to give. That is, the command signal and the address signal can be accurately given to the command signal and address signal input terminals having a small input load capacity by using the common clock as the strobe signal. However, it is difficult to provide a write data signal with the same clock as a strobe signal for data input / output terminals having a larger input load capacity than those. Moreover, since the write data signal is given at high speed in synchronization with the rising edge and falling edge of the clock, it becomes increasingly difficult.
[0008]
Therefore, it has been proposed that the system side synchronizes the supply of the write data signal with a data strobe signal asynchronous with the clock. The data strobe signal has the same frequency as the clock, but is not phase-synchronized with the clock.
[0009]
Thus, with the introduction of the data strobe signal asynchronous with the clock, it is necessary to solve the problem of how to control the internal write operation. It has not yet been proposed to perform an optimum write operation using an externally applied clock and a data strobe signal.
[0010]
Accordingly, an object of the present invention is to provide a semiconductor memory device capable of performing an optimum write operation using a clock and an asynchronous data strobe signal in order to solve the above-described conventional problems. .
[0011]
Furthermore, another object of the present invention is to provide a semiconductor memory device capable of performing the shortest write operation using a clock and a data strobe signal asynchronous to the clock.
[0012]
Furthermore, another object of the present invention is to provide a semiconductor memory device capable of shortening a write operation in a memory to which a command, an address, and a write data signal are supplied in synchronization with a clock.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a semiconductor memory device to which at least an address signal is supplied in synchronization with an external clock supplied from the outside.
A memory cell array having a plurality of memory cells for storing data;
A data signal input circuit for holding a write data signal supplied in synchronization with an external data strobe signal supplied from the outside in response to an internal data strobe signal generated in response to the external data strobe signal;
A write circuit for supplying a write data signal held by the data signal input circuit to the memory cell array in response to a write signal generated later than the internal data strobe signal in response to the external data strobe signal. It is characterized by.
[0014]
In the above invention, the write data signal applied in synchronization with the external data strobe signal is latched internally in response to the internal data strobe signal generated in response to the external data strobe signal. In response to a write signal generated from the strobe signal, a write data signal is supplied from a write circuit such as a write amplifier to the memory cell array. On the other hand, the address signal is taken in by an external clock. Therefore, the drive of the data bus line connected to the memory cell array from the write amplifier, which is the write operation inside the memory, is started according to the external data strobe signal, so the write operation can be performed in the shortest time from the input of the write data signal Can be terminated.
[0015]
The above invention is particularly effective when the memory has a 2-bit prefetch function. That is, a 2-bit write data signal is supplied in time series in synchronization with the external data strobe signal. Since the internal write operation can be started after waiting for the input of the second write data signal, the shortest write operation is enabled.
[0016]
Further, as an internal write operation, a column address signal, a redundancy comparison result signal, and the like are applied to a corresponding column decoder of the memory cell array in response to a column selection signal generated in response to an external data strobe signal.
[0017]
In addition to the above-mentioned invention, the address signal given in synchronization with the external clock can be compared with the redundancy comparison circuit in response to the address latch signal generated in response to the external clock. In addition, the writing operation can be speeded up. In particular, in the case of having a 2-bit prefetch function, it takes a time for one clock cycle to capture a 2-bit write data signal. During this period, a comparison operation with a redundant address is performed in a redundant comparison circuit. As a result, at the point in time when the writing data signal has been taken in, the preparation for supplying the redundancy comparison result signal to the column decoder is finished.
[0018]
Another invention for achieving the above object is a semiconductor memory device in which at least a command signal and an address signal are supplied in synchronization with an external clock supplied from the outside.
The command signal and the address signal are supplied in synchronization with a first clock of the external clock, and
A memory cell array having a plurality of memory cells for storing data;
A defective address corresponding to a defective memory cell of the memory cell array; And given A redundant comparison circuit that compares the obtained address;
A data input circuit for holding a write data signal supplied from the outside in response to an internal data strobe signal generated in response to a second clock supplied after the first clock of the external clock;
A write circuit for supplying a write data signal held by the data input circuit to the memory cell array in response to a write signal generated later than the internal data strobe signal in response to the second clock;
And an address latch circuit for supplying the address signal to the redundancy comparison circuit in response to an address latch signal generated in response to the first clock.
[0019]
In the above invention, in the memory to which the command, address and write data signal are supplied in synchronization with the external clock, the command and address are given in synchronization with the first clock, and the write data signal follows the first clock. When given in synchronization with the second clock, a redundancy comparison operation or the like in the redundancy comparison circuit is performed in response to the first clock. As a result, the redundant comparison operation can be performed in advance until the input operation of the write data signal applied in synchronization with the second clock is completed, and the write operation can be shortened.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, examples of embodiments of the present invention will be described with reference to the drawings. However, such an embodiment does not limit the technical scope of the present invention.
[0021]
FIG. 1 is a schematic diagram showing a relationship between a plurality of memories and a control unit that controls the memories. In this example, four SDRAMs 12, 14, 16, and 18 are connected to the control unit 10 on the system side. In this example, the command signal COMMAND and the address signal ADDRESS are given in synchronization with the clock CLK. The write data signal is supplied to the data input / output terminal DQ in synchronization with the data strobe signal DS. In this way, the strobe signal DS for the data input / output terminal DQ having a large load capacity can be made asynchronous with the clock CLK, which is the strobe signal for the command signal, address signal, etc. ~ 18 can be given.
[0022]
FIG. 2 is a diagram showing a schematic timing chart of the write operation using the clock CLK and the data strobe signal DS asynchronous to the clock CLK. In this example, a write command is given to the command signal COMMAND and a column address is given to the address signal ADDRESS in synchronization with the clock clk1. On the other hand, write data D0, D1, D2, and D3 are applied to the data input / output terminal DQ in synchronization with the rising and falling edges of the data strobe signal DS.
[0023]
Although the data strobe signal DS is asynchronous with the clock CLK, the standard determines that the data strobe signal DS has the same frequency and is within tDSS when the phase is advanced, and within tDSH when the phase is delayed. Therefore, (a) in the figure shows the relationship between the data strobe signal DS and the data written to the data input / output terminal DQ when the phase of the data strobe signal DS is advanced by the maximum tDSS. Further, (b) in the figure shows the relationship between the data strobe signal DS and the write data of the data input / output terminal DQ when the phase of the data strobe signal DS is delayed by the maximum tDSH.
[0024]
In the case of (a) in the figure, the write data D0 given to the data input / output terminal DQ is taken in at the timing when a predetermined time has elapsed from the rising edge of the data strobe signal DS, and further the next falling edge of the data strobe signal DS. The write data D1 given to the data input / output terminal DQ is taken in at a timing when a predetermined time has passed since the start. Similarly, write data D2 and D3 are captured in synchronization with the data strobe signal DS. Accordingly, the fetch of the 2-bit write data D0 and D1 has already been completed at the timing of the clock clk1.5, and the address input has also been completed. Thus, it will be understood that the internal write operation can be initiated at any time.
[0025]
In the figure, as an example, it is shown that the internal write operation starts at the timing of the clock clk2.
[0026]
On the other hand, in the case of (b) in FIG. 2, the data strobe signal DS rises at a timing delayed by the time tDSH from the timing of the clock clk1. As in the case of (a) above, the write data D0 applied to the data input / output terminal DQ is taken in at a timing when a predetermined time has elapsed from the rising edge of the data strobe signal DS, and further after the data strobe signal DS. The write data D1 applied to the data input / output terminal DQ is taken in at a timing when a predetermined time has elapsed from the falling edge of. Accordingly, in this case, the input of both data D0 and D1 is completed at a timing slightly earlier than the clock clk2.
[0027]
FIG. 3 is a schematic configuration diagram of the memory when the internal write operation is performed in synchronization with the clock CLK. In this example, the memory cell region includes an odd-numbered side memory cell array 20 and an even-numbered side memory cell array 21. Corresponding to both memory cell arrays 20 and 21, an odd-numbered side sense amplifier 22, an even-numbered side sense amplifier 23, an odd-numbered side column decoder 24, and an even-numbered side column decoder 25 are provided.
[0028]
FIG. 3 shows a write data input circuit portion and a column address signal processing circuit portion in the peripheral circuit for this memory cell array.
[0029]
FIG. 4 is a timing chart when the phase of the data strobe signal DS is advanced by tDSS from the reference clock. FIG. 5 is a timing chart when the phase of the data strobe signal DS is delayed by tDSH from the reference clock.
[0030]
First, the write data input circuit portion shown in FIG. 3 will be described. An input buffer 30 is connected to the data input / output terminal DQ, and applied write data signals D0 and D1 are input using a reference level Vref applied from the outside. The writing data signal is taken in at the rising edge or falling edge of the data strobe signal DS as described above. For this purpose, a data strobe signal DS given from the outside is inputted by the buffer circuit 46, and the inputted internal data strobe signal int.DS is delayed by a delay time by a delay circuit 48 for a data strobe signal DDS. Become. Then, the delayed data strobe signal DDS is supplied to a rising edge (H side edge) trigger circuit 50, and the rising edge trigger circuit 50 generates a first data strobe signal DSPZ that takes in the first write data signal DQ. . As a result, the write data signal D0 (internal write data signal int.DQ in the drawing) is taken into the first data latch circuit 32 at the timing of the first data strobe signal DSPZ.
[0031]
Further, the second data strobe signal DSPX synchronized with the falling edge of the data strobe signal DS is generated by the falling edge (L side edge) trigger circuit 52, and the second write data signal D1 inputted thereto is the first data strobe signal DSP1. The data is fetched into the second data latch circuit 36 at the timing of the second data strobe signal DSPX. At the same time, the first write data signal D 0 in the data latch circuit 32 is latched in the data shift register 34. Up to this point, the write data signals D0 and D1 are taken in in synchronization with the data strobe signal DS.
[0032]
The first and second write data DQE1 and DQO1 latched in the data shift register 34 and the data latch circuit 36, respectively, are at the timing of the data transfer signal DQTZ synchronized with the clock generated by the transfer clock generation circuit 56, respectively. The data transfer circuits 38 and 40 are latched. The transfer clock generation circuit 56 is supplied with a clock CLK (internal clock int.CLK in the figure) input by the buffer 54. Therefore, the data transfer signal DQTZ is generated at a timing that is a predetermined time after the timing of the clock clk2 at which the capture of the two write data D0 and D1 is reliably completed. As a result, the write data signal synchronized with the data strobe signal becomes a signal synchronized with the clock in the data transfer circuits 38 and 40. In this example, the first write data D0 is an even-numbered write data, and the second write data D1 is an odd-numbered write data.
[0033]
Then, at the timing of the write signal WRTZ generated by the write clock generation circuit 58, the even-side write amplifier 42 and the odd-side write amplifier 44 are activated, and the write data signal is output to the data buses 43 and 45, respectively.
[0034]
On the other hand, the column address processing part is as follows. The column address signal supplied to the column address terminal ADDRESS is taken in by the address buffer 62 at a timing synchronized with the rising edge of the clock clk1. Then, the column address signal CAxxZ (xx means an address number) fetched inside is a timing control signal 65 generated by the transfer clock generation circuit 56 at a timing delayed by a predetermined time from the timing of the clock clk1. It is input to the internal column address latch / counter circuit 66 at the timing.
[0035]
The internal column address latch / counter circuit 66 latches a given column address and generates a continuous column address by a counter function of adding +1 thereto. When the first column address is an even number, the column address is given to the even-numbered predecoder or the like, and the second column address added by +1 is given to the odd-numbered predecoder or the like.
[0036]
Then, the write clock generation circuit 58 generates the address generation signal ADLZ at the timing when a predetermined time has elapsed from the timing of the clock clk2, similarly to the write signal WRTZ. As a result, in response to the address generation signal ADLZ, the internal column address latch counter 66 converts the odd side column address CAxxZ1O and the even side column address CAxxZ1E to the redundancy comparison circuit 68, 80 And predecoder 70, 78 Give to each. Each circuit generates comparison result signals COMZO and COMZE and predecode signals PCAxxZO and PCAxxZE, respectively.
[0037]
In response to the timing signal CSZ generated by the write clock generation circuit 58, the column selection pulse generation circuit 60 generates the column selection signal CSELZ and compares it with the column decoders 24 and 25 at substantially the same timing as the write signal WRTZ. The drivers 72, 74, 82, 84 are driven so as to give the result signals COMZ1O, COMZ1E and the predecode signals PCAxxZ1O, PCAxxZ1E. That is, in synchronization with the timing of the clock clk2, the write signal WRT and the column selection signal CSELZ are generated, the output of the write data to the data buses 43 and 45, the predecode signal corresponding to the column address and the redundancy comparison result The timing of the signal output to the column decoder circuits 24 and 25 is matched.
[0038]
Therefore, in the memories shown in FIGS. 3 to 5, the write data signal is captured in synchronization with the data strobe signal DS, but the internal write operation is performed by the data transfer signal DQTZ generated in response to the timing of the clock clk2. It is controlled on the basis of.
[0039]
However, as can be understood from the above description, one cycle of the clock CLK is required to capture the first and second write data signals. This is because the first and second write data signals are taken in at the rising edge and falling edge of the data strobe signal DS. For this reason, it can be said that it is appropriate to start the internal write operation at the timing of the clock clk2 one cycle after the clock clk1.
[0040]
However, as shown in FIG. 4, when the data strobe signal DS is input at an early timing, the capture of the write data D0 and D1 has already been completed at an intermediate timing between the clocks clk1.5 and clk2 in the figure. . Further, the column address is also given in synchronization with the clock clk1. In that case, waiting until the timing of the clock clk2 causes a longer writing time.
[0041]
Furthermore, since column address generation, comparison with redundant addresses, and predecoding are started in response to the address generation signal ADLZ, the column selection signal CSELZ is generated after the redundant comparison result signal and predecode signal are generated. The timing to do becomes late.
[0042]
FIG. 6 is a schematic configuration diagram of a memory in which an internal write operation is performed in synchronization with a data strobe signal according to an embodiment of the present invention. FIG. 7 is a timing chart when the phase of the data strobe signal DS is advanced by tDSS from the reference clock in FIG. FIG. 8 is a timing chart when the phase of the data strobe signal DS is delayed by tDSH from the reference clock in FIG.
[0043]
The memory shown in FIG. 6 has a write data input circuit section in the upper left half and a column address processing section in the lower left half, as in the configuration of the memory in FIG. The memory cell array portion on the right side in the figure has the same configuration. Accordingly, the same reference numerals are assigned to the portions corresponding to FIG.
[0044]
In the example of the memory in FIG. 6, the write data signal DQ (D0, D1) is taken in in synchronization with the data strobe signal DS, and the internal write timing is controlled based on the data strobe signal DS. . Specifically, the write data signals D0 and D1 from the data input / output terminal DQ are taken in by the first data strobe signal DSPZ and the second data strobe signal DSPX. Further, on the basis of the second data strobe signal DSPX, the write clock generation circuit 58 generates a write signal WRTZ for activating the write amplifiers 42, 44, and the column selection pulse generation circuit 60 further generates a column selection signal CSELZ. Is generated.
[0045]
Further, in the example of the memory of FIG. 6, the column address signal ADDRESS is taken in at the timing synchronized with the clock CLK, the address is increased by +1, and the redundancy comparison circuits 68 and 78 and the predecoders 70 and 80 are used. Is controlled.
[0046]
Accordingly, a schematic operation includes column address fetching, counter operation, predecode operation, redundant comparison operation, etc. at the timing of the clock clk1. On the other hand, a write data signal is taken in at the rising edge and falling edge of the data strobe signal DS, and the internal write operation is performed at the timing when the falling edge of the data strobe signal is started. In the internal write operation, the write amplifiers 42 and 44 are activated to output a write data signal to the data bus line, and the column selection signal CSELZ is used to output the redundant comparison result signal COMZ3 and the predecode signal PCAxxZ3 to the column of the memory cell array. This is supplied to the decoders 24 and 25.
[0047]
In order to perform the above operation, in the memory shown in FIG. 6, unlike FIG. 3, the write clock generation circuit 58 responds to the second data strobe signal DSPX generated from the data strobe signal DS in response to the write signal. Generate WRT. The column selection pulse generation circuit 60 generates a column selection signal CSELZ based on the signal CSZ generated by the write clock generation circuit 58. This is also different from FIG. Therefore, the data transfer circuits 38 and 40 in FIG. 3 do not exist in the example of FIG.
[0048]
Furthermore, in the memory shown in FIG. 6, compared with FIG. 80 And predecoder 70, 78 Is controlled in advance at the timing of the clock timing clk1 of the clock CLK, separately from the internal write operation. Therefore, the output timing of the column address CAxxZ1 by the internal column address latch / counter 66 is controlled by the address generation signal ADLZ generated by the internal clock generation circuit 90.
[0049]
The configuration and operation of FIG. 6 will be described below with reference to FIG. FIG. 7 shows a case where the data strobe signal DS has a phase earlier by tDDS than the clock clk1. The first write data D0 input from the data input / output terminal DQ is generated by the first data strobe signal DSPZ generated at the timing of the rising edge of the delayed data strobe signal DDS generated from the data strobe signal DS. It is latched by the data latch circuit 32. Further, the second write data D1 is latched in the second data latch circuit 36 by the second data strobe signal DSPX generated at the timing of the falling edge of the delayed data strobe signal DDS thereafter. At the timing of the second data strobe signal DSPX, the write data D0 latched in the first data latch circuit 32 at the same time is held in the data shift register 34.
[0050]
After the timing of the second data strobe signal DSPX, since the two write data signals D0 and D1 are latched, the write clock generation circuit 58 generates the write signal WRTZ in response to the signal DSPX. Further, based on the signal CSZ generated by the write clock generation circuit 58, the column selection pulse generation circuit 60 generates a column selection signal CSELZ.
[0051]
On the other hand, at the timing of the clock clk1, the address buffer 62 takes in the column address ADDRESS by the address buffer latch signal ABL generated by the internal clock generation circuit 90, and the internal column address CAxxZ is generated. Here, xx indicates that there are a plurality of column addresses.
[0052]
Further, the internal column address latch / counter circuit 66 generates a next column address incremented by +1 from the given internal column address CAxxZ, for example, generates an even side column address CAxxZ1E and an odd side column address CAxxZ1O. To do. The even-side column address CAxxZ1E and the odd-side column address CAxxZ1O are supplied to the odd-numbered redundancy comparison circuit 68 and the predecoder 70 at the timing of the address generation signal ADLZ, and to the even-numbered redundancy comparison circuit. 80 And predecoder 78 Are given respectively. The address generation signal ADLZ is generated by the internal clock generation circuit 90 based on the clock clk1.
[0053]
Therefore, the generation of an increased address, the comparison with the redundant address, the predecode operation, and the like with respect to the column address signal ADDRESS are performed at an early timing at the timing based on the clock clk1, regardless of the data strobe signal DS. Therefore, the output timing of the comparison result signals COMZO and COMZE and the predecode signals PCAxxZO and PCAxxZE by the drivers 72, 74, 76, and 78 can be made earlier than in the case of FIG. The timing is the timing of the column selection signal CSELZ.
[0054]
As shown in FIG. 7, the internal write operation substantially starts at timing t10 slightly delayed from the clock clk1.5. Therefore, as compared with the case where the internal write operation is started from the clock clk2 in the case of FIG. 3, the internal write operation can be started earlier by the time ΔT as shown in the center of FIG. In order to perform the internal write operation at such an early timing, it is necessary to start the column address processing early according to the timing of the clock clk1, as described above. In the example of FIG. 3, the column address processing is performed after the clock clk2.
[0055]
FIG. 8 is a timing chart when the phase of the data strobe signal DS is delayed by the time tDSH from the clock clk1. The operation of the configuration shown in FIG. 6 in this case is the same as that in FIG. As shown in FIG. 8, column address processing is performed in advance according to the timing of the clock clk1. Then, the first write data signal D0 is latched at the rising edge (first data strobe signal DSPZ) of the data strobe signal DS given after the time tDSH from the clock clk1, and the falling edge (second data strobe signal DSPX). Thus, the second write data signal D1 is latched. Then, the internal write operation is started from time t10 with the second data strobe signal DSPX as a starting point.
[0056]
Therefore, in the case of FIG. 8, the internal write operation starts at the same time as in FIG. However, in the case of FIG. 3, as shown in FIGS. 4 and 5, since the internal write operation starts at time t10, the redundancy comparison operation and the predecode operation are performed as indicated by t20 in the figure. The comparison result signals COMZO and COMZE and the predecode signals PCAxxZO and PCAxxZE that are the results of the above are generated thereafter. On the other hand, in the case of the memory shown in FIG. 6, as shown in FIG. 8, before time t10 when the internal write operation starts, as shown by t20 in the figure, the redundancy comparison operation and the predecode operation are performed. Is called. Therefore, the comparison result signals COMZO and COMZE generated by the column address signal processing and the predecode signals PCAxxZO and PCAxxZE are already generated before the internal write operation start time t10. Therefore, as a whole, the time until completion of writing is shortened.
[0057]
As described above, since the column address signal is captured in synchronization with the clock clk1, it is subsequently generated at the control timing synchronized with the clock clk1 by preceding the column address signal with redundancy comparison or predecode operation. The processing time for the internal write operation can be shortened.
[0058]
FIG. 9 shows drivers 72, 74, 82,84 FIG. The driver circuit shown in FIG. 6 is supplied with three control signals TCS1, TCS2, and CSELZ. However, the detailed configuration is not shown due to space limitations. Therefore, the detailed configuration and operation will be described with reference to FIG.
[0059]
As shown in FIG. 9, the three control signals TCS 1, TCS 2, and CSELZ control the previous stage gates of the latch circuit 92, the latch circuit 94, and the final drive circuit 96. The timing control signal TCS1 generated by the internal clock generation circuit 90 is inverted by the inverter 102 and controls the N-type transistor 100 and the P-type transistor 101 constituting the CMOS transfer gate. That is, the redundancy comparison circuit 68, in response to the timing control signal TCS1. 80 Comparison result signal COMZ and predecoder 70, 78 And the predecode signal PCAxxZ from is latched by the latch circuit 92. The latch circuit 92 includes two inverters 103 and 104. As a result, the result of the redundancy comparison operation or the predecode operation is latched in the driver circuit by the timing control signal TCS1 generated from the clock clk1. As a result, the latched result signal COMZ1 and predecode signal PCAxxZ1 are held in the node n1.
[0060]
Next, the CMOS transfer gates 105 and 106 are opened by the second timing control signal TCS2 generated by the write clock generation circuit 58, and the signal at the node n1 is latched by the latch circuit 94. The second timing control signal TCS2 is a signal generated by the data strobe signal DS, and the comparison result signal and the predecode signal are latched by the latch circuit 94 in response to the start of internal writing. Therefore, the latch circuit 94 changes from the control synchronized with the clock CLK to the control synchronized with the data strobe signal. Migration It has the function of a transfer circuit for this purpose. The latch circuit 94 includes a NAND gate 108 and an inverter 109, and the latched result signal COMZ2 and predecode signal PCAxxZ2 are held at the node n2.
[0061]
Here, finally, the column selection signal generated by the column selection pulse generation circuit 58 is generated. No. CS ELZ opens NAND gate 110, and inverter 111 supplies result signal COMZ3 and predecode signal PCAxxZ3 to column decoders 24 and 25 provided in the memory cell array. That is, the result signal COMZ3 and the predecode signal PCAxxZ3 are output in accordance with the operation of the write amplifier circuits 42 and 44. Therefore, the internal write operation is controlled in synchronization with the data strobe signal DS.
[0062]
As described above, the driver circuits 72, 74, 82,84 The latch circuit 94 holds the predecode signal PCAxxZ and the comparison result signal COMZ according to the H level of the second timing control signal TCS2. Then, the predecode signal PCAxxZ2 and the comparison result signal COMZ2 held by the latch circuit 94 during the H level period of the column selection signal CSELZ are supplied to the column decoders 24 and 25 as the predecode signal PCAxxZ3 and the comparison result signal COMZ3, respectively. . Therefore, the second timing control signal TCS2 and the column selection signal CSELZ enable the internal write operation at the control timing synchronized with the data strobe signal DS. The first timing control signal TCS1 is controlled in synchronization with the clock clk1, and latches the redundant comparison result signal COMZ and the like performed in advance in the latch circuit 92.
[0063]
When the read signal READ is at the H level, the NAND gates 112 and 108 are opened, and the predecode signal and the comparison result signal are directly supplied to the NAND gate 110. Therefore, at the time of reading, the timing control signals TCS1 and TCS2 are not used, and are only output to the column decoder at a timing controlled by the column selection signal CSELZ.
[0064]
FIG. 10 is a diagram showing an example of specific circuits of the first and second data latch circuits 32 and 36 and the data shift register circuit 34 shown in FIG. The first data latch circuit 32 that takes in the even-numbered write data D0 input first by the first data strobe signal DSPZ Reve Type flip-flop circuit. The CMOS gates 120 and 121 are turned on by the H level of the first data strobe signal DSPZ, and the first write data signal D0 is latched in the latch circuit on the slave side constituted by the two inverters 123 and 124. Then, the CMOS gate 125, the L level of the first data strobe signal DSPZ 126 Is conducted and held in a master side latch circuit composed of two inverters 127 and 128.
[0065]
The second data latch circuit 36 and the data shift register 34 have the same configuration as the first data latch circuit 32. Due to the H level of the second data strobe signal DSPX synchronized with the falling edge of the data strobe signal DS, the second write data D1 is latched by the latch circuit comprising the inverters 143 and 144 of the second data latch circuit 36. The At the same time, the data signal DQE held by the first data latch circuit 32 is also latched by the latch circuit including the inverters 133 and 134 of the data shift register 34. Then, depending on the L level of the second data strobe signal DSPX, the write data D0 and D1 are transferred to the latch circuit composed of the inverters 137 and 138 and the latch circuit composed of the inverters 147 and 148 in the circuits 34 and 36, respectively. Retained. As a result, the even-side write data signal DQE1 and the odd-side write data signal DQO1 are generated by the circuits 34 and 36, respectively.
[0066]
FIG. 11 is a diagram illustrating another example of a specific circuit of the data latch circuits 32 and 34. This example includes a front-stage latch circuit 176 and a rear-stage latch circuit 178. The pre-stage latch circuit 176 includes P-type transistors 150, 151, 158, 161 and N-type transistors 152, 153, 154, 159, 160, 162, 163. Further, the latch circuit 178 in the subsequent stage includes two inverters 172 and 173.
[0067]
To briefly explain the operation, while the control signals DSPZ and DSPX are at the L level, the data latch circuit is inactive and there is no current consumption. That is, the transistors 150 and 151 are turned on, and the nodes n10 and n11 are both at the H level. As a result, node n12 is at L level by inverter 166, and node n13 is also at L level by inverter 167. Accordingly, the transistors 168 to 171 are all non-conductive, and the nodes n14 and n15 are in a high impedance state. As a result, the latter-stage latch circuit 178 holds the previous state.
[0068]
Next, when the write data signals D0 and D1 are applied to the internal input / output terminal int.DQ, when the control signals DSPZ and DSPX are at the H level, the transistors 150 and 151 are turned off, the transistor 154 is turned on, and the write is performed. A differential amplifier composed of transistors 152 and 153 to which data D0 and D1 and their inverted signals are applied is activated. If the write data signal is at H level, the transistor 152 is turned on, the node n10 is at L level, and the node n11 is at H level. Accordingly, the transistor 168 is turned on, the transistor 169 is turned off, and the node n14 is at H level. On the other hand, transistor 171 conducts and node n15 is at L level. The signals at these nodes n12 and n13 are fed back to the transistors 160 and 163 to facilitate the latching of the latch circuit 176 in the previous stage. Further, the post-stage latch circuit 178 latches the data by the nodes n14 and n15.
[0069]
This data latch circuit can detect the write data signals D0 and D1 only at the rising edges of the control signals DSPZ and DSPX and can latch them in the subsequent latch circuit 178. Therefore, a higher-speed operation is possible than the master-slave type circuit that latches by the rising and falling of the control signal shown in FIG. In addition, the energy-saving type consumes current only while the control signal is at the H level.
[0070]
FIG. 12 is a diagram showing a schematic configuration of a memory according to the second embodiment of the present invention. In FIG. 12, parts corresponding to those in FIGS. 3 and 6 are given the same reference numbers. FIG. 13 is a flowchart of the operation of FIG. In FIG. 13, the same reference numerals are assigned to the portions corresponding to FIGS.
[0071]
A characteristic point in the circuit example of FIG. 12 is not a specification in which the write data signal is given in synchronization with the data strobe signal, but a specification in which the write data signal is given in synchronization with the external clock CLK.
[0072]
In general, the column address signal ADDRESS is given in synchronization with the rising edge of the clock clk1 together with the write command signal. Therefore, in the memory shown in FIG. 12, after the write command is decoded and the write mode is recognized, the write data signal is given to the input / output terminal DQ at the timing of the next clock clk2. The current consumption of the input buffer circuit 30 can be kept low. That is, after the write command is recognized, the input buffer circuit 30 may be activated by the enable signal EN and waited. Therefore, in this example, the write data signals D0 and D1 are given to the data input / output terminal DQ from the system side in synchronization with the rising edge of the clock clk2 and the falling edge of the clock clk2.5.
[0073]
Therefore, the capture of the write data signal and the start of the internal write operation accompanying it are controlled at the timing of the internal control signal starting from the clock clk2. However, since the column address ADDRESS is input in synchronization with the rising edge of the clock clk1, the column address processing such as the redundancy address comparison operation and the predecode operation is performed in advance by a control signal starting from the clock clk1. Thus, the internal write operation can be started immediately after the write data signals D0 and D1 inputted thereafter are latched.
[0074]
In order to enable the above operation, the first data strobe signal DSPZ and the second data strobe signal DSPX are set to rising edges in response to the internal clock int.CLK acquired by the buffer circuit 46. It is generated by the trigger circuit 50 and the falling edge trigger circuit 56. The write clock generation circuit 58 that controls the internal write operation is controlled by the second data strobe signal DSPX generated from the clock int.CLK. The generation of the write signal WRT, the column selection signal CSELZ, and the like by the write clock generation circuit 58 is equivalent to the case of the circuit of FIG.
[0075]
Further, the internal clock generation circuit 90 starts from the clock clk1 to which the column address ADDRESS is applied, and the column on the even and odd sides from the address buffer latch signal ABL, the first timing control signal TCS1, and the internal column address latch / counter circuit. An address latch signal ADLZ for generating addresses CAxxZ1O and CAxxZ1E is generated. With this configuration, the redundant address comparison operation precedes the redundant address comparison circuit 68, starting from the clock clk1. 80 And the predecode operation is performed by the predecoder 70, 78 Can be performed.
[0076]
Drivers 72, 74, 82,84 6 is the same as that shown in FIGS. 6 and 9, and the first timing control signal TCS2 latches the redundancy comparison result signals COMZO, COMZE and the predecode signals PCAxxZO, PCAxxZE, and the second timing control signal. TCS 2 Then, the same signal is further latched, and these signals COMZ3O, COMZ3E and PCAxxZ3O, PCAxxZ3E are output to the column decoders 24, 25 at the timing of the column selection signal CSELZ.
[0077]
As shown in the operation timing chart of FIG. 13, the column address signal is taken in at the timing of the clock clk1, and the operations in the redundancy comparison circuits 68 and 78 and the predecoders 70 and 80 precede at the time indicated by t20 in the figure. Done. Then, at the timing of the clock clk2, the write data signals D0 and D1 are sequentially fetched, and the internal write operation is started from time t10. Specifically, a write signal WRT is supplied to the write amplifiers 42 and 44, and a column selection signal CSELZ is supplied to the drivers 72, 74, and 82.84. Since the redundancy comparison operation or the like is performed in advance, the internal write operation can be started by the column selection signal CSELZ immediately after taking the write data signal.
[0078]
FIG. 14 is a diagram showing a specific circuit of the input buffer circuit 30 connected to the data input / output terminal DQ. This input buffer circuit is a circuit that detects an H level or an L level of a write data signal based on externally supplied write data signals D0 and D1 and a reference signal Vref, and converts it to a CMOS level. The P-type transistors 180 and 181 constitute a current mirror circuit, and the transistors 182 and 183 having the load as a load constitute a differential amplifier circuit. The current source transistor 184 is turned on by the enable signal EN generated by the command decoder 189 and activates the differential amplifier circuit. The command decoder 189 is supplied with control signals / RAS, / CAS, / CS1, / WE, and a write command is given by a combination of these control signals.
[0079]
When the command decoder 189 detects that the write command is given from the combination of the control signals, the command decoder 189 sets the enable signal EN to the H level, activates the input buffer circuit 30, and waits to receive the write data signal. Therefore, since the input buffer 30 is activated only at the time of writing, power consumption can be greatly saved.
[0080]
Incidentally, the internal write data signal int.DQ which has been waveform-shaped by the inverters 185, 186 and 187 and converted to the CMOS level is generated.
[0081]
FIG. 15 is a diagram showing an improved example of the second embodiment shown in FIG. In this example, a delayed lock loop circuit 194 is used to generate the internal clock int.CLK from the external clock CLK.
[0082]
The delayed lock loop circuit 194 is a circuit that generates an internal clock int.CLK that is synchronized with the clock CLK input from the input buffer 46 and has the same phase. The delayed locked loop circuit 194 includes a delay circuit 196, a delay control circuit 198 that controls the delay amount of the delay circuit 196, and a phase comparison circuit 199. Further, it further includes a buffer circuit 200 in a pseudo manner.
[0083]
The delayed lock loop circuit 194 is well known, but the basic operation principle is that the phase of the external clock CLK and the internal clock int. As described above, the delay control circuit 198 controls the delay amount of the delay circuit 196. Since the pseudo buffer circuit 200 has a delay characteristic equivalent to that of the input buffer 46, for example, the internal clock int.CLK is a clock having a phase that is delayed by one cycle from the external clock CLK. Since the clock repeats the H level and the L level one after another, the external clock CLK and the internal clock int.CLK are apparently having the same phase. That is, as shown by the broken line of the internal clock int.CLK in FIG.
[0084]
When the data strobe signal DSPZ synchronized with the rising edge of the clock and the data strobe signal DSPX synchronized with the falling edge of the clock are generated using the internal clock, the latch timing in the data latch circuit 190 is shown in FIG. Can be faster than if. Accordingly, in the example of FIG. 15, the data input / output terminal DQ is not directly connected to the data latch circuit via the input buffer 30 as in the example of FIG. 12, but is directly connected to the data latch circuits 190 and 192. Therefore, these latch circuits also have an input buffer function.
[0085]
The example of FIG. 15 is otherwise the same as that of FIG. 12, and the corresponding circuit is denoted by the same reference number. That is, at the timing of the clock clk1, the column address is fetched and the redundancy comparison operation is performed. On the other hand, the write data D0 and D1 are fetched from the data input / output terminal DQ at the timing of the clock clk2, and the internal write operation is performed.
[0086]
FIG. 16 is a diagram showing a circuit example of the data latch circuits 190 and 192 in FIG. The data latch circuit is also supplied with an external clock CLK and an external reference voltage Vref. Data strobe signals DSPZ and DSPX are given as control clocks. While the control clock is at the L level, the P-type transistors 214 and 215 are in the conductive state, and the nodes n20 and n21 are both maintained at the H level. Accordingly, the transistors 228 to 231 are disabled, and the nodes n22 and n23 are in a high impedance state.
[0087]
Therefore, when the control clocks DSPZ and DSPX become H level, the transistors 214 and 215 are turned off, the N-type transistors 218 and 219 are turned on, and the write data is written by the differential circuit including the transistors 216 and 217. A buffer operation is performed to determine whether the signals D0 and D1 are higher or lower than the reference voltage Vref. In response, one of the nodes n20 and n21 falls from the H level to the L level. For example, when the write data signal is at the H level, the transistor 216 is turned on and the node n20 is lowered to the L level.
[0088]
Accordingly, transistor 228 conducts, node n22 goes to H level, transistor 231 conducts, and node n23 goes to L level. Those node states are latched by a latch circuit including inverters 232 and 233.
[0089]
That is, the data latch circuit shown in FIG. 16 is controlled by the early timing data strobe signals DSPZ and DSPX generated from the internal clock having the same phase as the external clock CLK, and thus has a buffer function and the control clock DSPZ, Only the rising edge of DSPX has a function of latching the input write data signal at high speed. Therefore, it is suitable as the data latch circuit of FIG.
[0090]
FIG. 17 is a diagram showing another improved example of the second embodiment shown in FIG. This example also uses a delayed lock loop circuit 194 to generate the internal clock int.CLK from the external clock CLK. Further, in this example, one data latch circuit 190 is provided for the data input / output terminal DQ, the write data signals D0 and D1 are taken in time series by the data strobe signals DSPZ and DSPX, and the even number is given by the demultiplexer 202. Side write data signal DQE1 and odd side write data signal DQO1.
[0091]
The data latch circuit 190 has the same configuration as the data latch circuit of FIG. In the demultiplexer circuit 202, in response to the control signals DDSPZ and DDSPX obtained by delaying the data strobe signals DSPZ and DSPX, the data latched by the data latch circuit 190 is converted into even-numbered and odd-numbered write data DQE1 and DQO1. Distribute.
[0092]
FIG. 18 is a diagram illustrating an example of the demultiplexer circuit. This circuit has three latch circuits 250, 260 and 270. In this demultiplexer circuit, the internal data IDQ latched by the data latch circuit 190 is latched in the latch section comprising the inverters 255 and 256 in the latch circuit 250 by the control signal DDSPZ obtained by delaying the first data strobe signal DSPZ. Is done. The CMOS gates 262, 263, 272, and 274 are turned on by the control signal DDSPX obtained by delaying the second data strobe signal DSPX, and the second write data signal D 2 Is latched in the latch part of the inverters 275 and 276 in the latch circuit 270 and the data DQ latched in the latch circuit 250 E (D1) is The latch circuit 260 is latched by a latch unit including inverters 265 and 266.
[0093]
The memory shown in FIG. 17 is the same as the memory shown in FIG. 15 except that the demultiplexer circuit described above is provided. Accordingly, the corresponding reference numbers are assigned to the corresponding portions. The data latch circuit 190 and the demultiplexer circuit 202 shown in FIGS. 17 and 18 are not limited to the second embodiment shown in FIG. 12, but the buffer circuit 30 of the first embodiment shown in FIG. The present invention can also be applied in place of the data shift registers 34 and 36.
[0094]
Although the above embodiment has been described by taking a synchronous DRAM as an example, the present invention is not limited to a synchronous DRAM but can be widely applied to a memory to which an address or the like is given in synchronization with an external clock.
[0095]
【The invention's effect】
As described above, according to the present invention, in the memory using the external clock and the asynchronous external data strobe signal, the internal write operation is started immediately after the write data signal is input in response to the external data strobe signal. The write operation can be speeded up. Furthermore, the write operation can be further speeded up by performing the redundancy comparison operation or the like without waiting for the internal write operation to the address signal given in synchronization with the external clock.
[0096]
In addition, in a memory in which an address and a command are supplied in synchronization with the first external clock and a write data signal is supplied in synchronization with the second external clock following the first external clock, the first external clock Since the redundancy comparison operation and the like are performed after the address signal is input in synchronization, the time required for the internal write operation can be shortened.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a relationship between a plurality of memories and a control unit that controls the memories.
FIG. 2 is a diagram showing a schematic timing chart of a write operation using a clock CLK and an asynchronous data strobe signal DS.
FIG. 3 is a schematic configuration diagram of a memory when an internal write operation is performed in synchronization with a clock CLK.
FIG. 4 is a timing chart when the phase of a data strobe signal DS is advanced by tDSS from a reference clock.
FIG. 5 is a timing chart when the phase of a data strobe signal DS is delayed by tDSH from a reference clock.
FIG. 6 is a schematic configuration diagram of a memory in which an internal write operation is performed in synchronization with a data strobe signal.
7 is a timing chart when the phase of the data strobe signal DS is advanced by tDSS from the reference clock in FIG. 6;
FIG. 8 is a timing chart when the data strobe signal DS is delayed in phase by tDSH from the reference clock in FIG. 6;
FIG. 9 is a diagram illustrating a circuit configuration of a driver.
FIG. 10 is a diagram illustrating specific circuit examples of first and second data latch circuits and a data shift register circuit;
FIG. 11 is a diagram showing another example of a specific circuit of the data latch circuit.
FIG. 12 is a diagram showing a schematic configuration of a memory according to a second embodiment of the present invention.
FIG. 13 is a flowchart of the operation of FIG.
FIG. 14 is a diagram showing a specific circuit of an input buffer circuit connected to a data input / output terminal DQ.
FIG. 15 is a diagram showing an improved example of the second embodiment shown in FIG.
16 is a diagram illustrating a circuit example of data latch circuits 190 and 192 in FIG. 15;
FIG. 17 is a diagram showing another improved example of the second embodiment shown in FIG.
FIG. 18 is a diagram illustrating an example of a demultiplexer circuit.
[Explanation of symbols]
CLK External clock
SD External data strobe signal
D0, D1 Write data signal
DQ data input / output terminal
ADDRESS address signal
20, 21 Memory cell array
24, 25 column decoder
32, 34, 36 Write data signal input circuit
42,44 Write circuit, write amplifier
WRTZ write signal
72, 74, 82, 84 Driver circuit
CSELZ Column selection signal

Claims (23)

A data input circuit that captures a data signal in response to a strobe signal and outputs the data signal in response to an external clock signal;
An address input circuit that captures an address signal in response to the external clock signal, and outputs the address signal in response to the external clock signal delayed by one clock cycle or more from the external clock signal that captures the address signal;
An internal circuit for writing a data signal output from the data input circuit to a memory cell corresponding to the address signal output from the address input circuit.   The data input circuit is provided in parallel with a first data latch circuit that takes in the data signal in response to a rise of the strobe signal, and in response to a fall of the strobe signal. The semiconductor memory device according to claim 1, further comprising a second data latch circuit that takes in the data signal. The data input circuit receives the first data from the first data latch circuit and the second data from the second data latch circuit according to a data transfer signal in response to the external clock signal. The semiconductor memory device according to claim 2, further comprising a circuit. In response to said external clock signal, the data transfer signal further comprises a transfer clock generation circuit for generating, the transfer clock generation circuit, the external clock signal from one clock cycle or delay the data receiving said address signal 4. The semiconductor memory device according to claim 3, wherein a transfer signal is output.   A write amplifier for receiving first and second data from the data transfer circuit in parallel and transferring the first and second data to a data bus in response to a write timing signal in response to the external clock signal; 5. The semiconductor memory device according to claim 3, further comprising:   2. The semiconductor memory according to claim 1, wherein the address input circuit includes an address buffer circuit that receives the address signal, and an address latch circuit that receives the address signal from the address buffer circuit in response to the external clock signal. apparatus. And address pre-decoding circuit for decoding an address signal from the address input circuit in response to the external clock signal, characterized by further comprising an address driver circuit for outputting an address signal from said address predecoding circuit The semiconductor memory device according to claim 1. In response to said external clock signal, the capture address signal having the external clock signal from one clock cycle or delayed address transfer signal further address transfer signal generation circuit for generating said address input circuit said address transfer signal in response, a semiconductor memory device according to claim 7, wherein the outputting the address signal to the address predecoder circuit. A write amplifier that transfers a data signal from the data input circuit to a data bus in response to the external clock signal;
A memory cell array comprising an odd cell array and an even cell array;
8. The write amplifier and the address driver circuit are provided corresponding to the odd cell array and the even cell array, respectively, and simultaneously supply a data signal and an address signal to the odd cell array and the even cell array. Semiconductor memory device.   10. The address signal according to claim 1, wherein the address signal is captured in response to a rise of the external clock signal, and the data signal is captured in response to a rise and a fall of the strobe signal. Semiconductor memory device.   11. The semiconductor memory device according to claim 1, wherein the strobe signal has a phase difference within a predetermined value at the same frequency as the external clock signal. In a semiconductor memory device that captures a data signal in response to an external strobe signal,
And write no address input circuit takes the address signal in response to an external clock signal,
An address driver circuit that outputs an address signal from the address input circuit in response to the external strobe signal;
A semiconductor memory device comprising: an internal circuit for writing the data signal in a memory cell corresponding to an address signal output from the address driver circuit.   13. The semiconductor memory device according to claim 12, further comprising a data input circuit that takes in the data signal in response to the external strobe signal and outputs the data signal in response to the external strobe signal.   The data input circuit is provided in parallel with a first data latch circuit that takes in the data signal in response to a rise of the external strobe signal, and in parallel with the first data latch circuit. 14. The semiconductor memory device according to claim 13, further comprising a second data latch circuit that takes in the data signal in response.   15. The semiconductor memory device according to claim 14, wherein the first and second data latch circuits are constituted by master-slave flip-flop circuits.   15. The semiconductor memory device according to claim 14, wherein the first and second data latch circuits are constituted by differential amplifier circuits.   17. The address input circuit includes an address buffer circuit that receives the address signal, and an address latch circuit that takes in the address signal from the address buffer circuit in response to the external clock signal. Or a semiconductor memory device. Further comprising an address pre-decoding circuit for decoding an address signal from the address input circuit, the address driver circuit, a response to the address pre-decode takes an address signal from de circuit write no thing to the external clock signal The semiconductor memory device according to claim 12, wherein: 19. The semiconductor memory device according to claim 18, wherein the address driver circuit performs an output operation in response to a fall of the external strobe signal. A write amplifier for transferring a data signal from the data input circuit to a data bus in response to the external strobe signal;
A memory cell array comprising an odd cell array and an even cell array;
20. The write amplifier and the address driver circuit are provided corresponding to the odd cell array and the even cell array, respectively, and supply a data signal and an address signal to the odd cell array and the even cell array at the same time. The semiconductor memory device described.   The address driver circuit is held by the first latch circuit that captures an address signal from the address input circuit in response to the external clock signal and the first latch circuit in response to the external strobe signal 21. The semiconductor memory device according to claim 18, further comprising a second latch circuit that takes in an address signal.   22. The semiconductor memory device according to claim 21, wherein the address driver circuit includes a bypass circuit that bypasses the first latch circuit during a read operation.   23. The semiconductor memory device according to claim 12, wherein the external strobe signal has a phase difference within a predetermined value at the same frequency as the external clock signal.

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