JPH0475976U

JPH0475976U -

Info

Publication number: JPH0475976U
Application number: JP11949490U
Authority: JP
Priority date: 1990-11-15
Filing date: 1990-11-15
Publication date: 1992-07-02

Description

[Brief explanation of the drawing]

第１図は本考案のＬＳＩテスタの第１の実施例
を示した構成ブロツク図、第２図は本考案のＬＳ
Ｉテスタのストローブ信号エラーの回路図、第３
図はストローブ信号エラーの動作を説明するタイ
ムチヤート、第４図は本考案のＬＳＩテスタの第
２の実施例を示した構成ブロツク図である。１……タイミングジエネレタ、２……プログラ
ムカウンタ、７……コンパレータ、８……ストロ
ーブ信号エラー検出回路、９……第１のフエイル
・メモリ、１０……第２のフエイルメモリ。 FIG. 1 is a configuration block diagram showing the first embodiment of the LSI tester of the present invention, and FIG. 2 is a block diagram of the LSI tester of the present invention.
I tester strobe signal error circuit diagram, 3rd
The figure is a time chart illustrating the operation of a strobe signal error, and FIG. 4 is a block diagram showing a second embodiment of the LSI tester of the present invention. DESCRIPTION OF SYMBOLS 1... Timing generator, 2... Program counter, 7... Comparator, 8... Strobe signal error detection circuit, 9... First fail memory, 10... Second fail memory.

Claims

[Claims for Utility Model Registration] (1) A pattern memory in which a test pattern is stored, a DUT (device under test) that outputs a response signal in response to the test pattern read from the pattern memory, and this DUT. an expect memory that stores an expected value to be compared with a response signal output from the DUT; a comparator that compares the expected value read from the expect memory with the response signal output from the DUT; and a comparison of the comparator. An LSI tester having a fail memory for storing results, the LSI tester comprising an error detection circuit that checks whether a strobe signal is generated to be output to the comparator and the fail memory each time the test pattern is output. LSI tester. (2) a pattern memory in which a test pattern is stored; a DUT that outputs a response signal in response to the test pattern read from the pattern memory;
an expect memory that stores an expected value to be compared with a response signal output from the DUT; a comparator that compares the expected value read from the expect memory with the response signal output from the DUT; The LSI tester has a fail memory that stores the comparison results of , and is capable of writing fail data into the fail memory using a strobe signal for each address, as well as writing whether or not the strobe signal has been input. An LSI tester featuring the following features.