JPH0553929A - Central processing unit with fault information preserving function - Google Patents

Abstract

PURPOSE:To shorten time for analyzing a fault by preserving operations until the fault is generated at a central processing unit. CONSTITUTION:Normally in the case of performing access from a central processing unit 1 to a main storage device 2, a memory access trace control circuit 4 fetches information on an address bus 6 and a data bus 7 at the timing of an R/W signal on an R/W signal line 8, and the information is stored in the address of a trace information preservation memory 3 designated by the pointer of the memory access trace control circuit 4. When one kind of information is stored, the pointer is incremented by '+1' When the fault is generated, the central processing unit 1 informs the fault generation to the memory access trace control circuit 4 by a fault report signal line 5, and the memory access trace control circuit 4 stops storing the information in the trace information preservation memory 3 and stores the final pointer in the inside register.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit having a failure information storage function.

[0002]

2. Description of the Related Art In a conventional central processing unit, failure information is detected by software or firmware as failure information and then the failure information is collected and saved.

[0003]

In this conventional central processing unit, since the fault information is collected after the fault is detected, there is a time lag between the fault occurrence and the fault detection, so that accurate fault information cannot be obtained and the fault cannot be obtained. There was a problem that analysis took time.

[0004]

A central processing unit with a fault information storage function of the present invention comprises a trace information storage memory for storing an address and data of an accessed main storage device,
A memory access trace control circuit for controlling reading / writing of the trace information storage memory is provided.

[0005]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a central processing unit with a failure information storage function of the present invention.

In this embodiment, a central processing unit 1, a main storage unit 2, which are connected to each other via an address bus 6, a data bus 7, and a read / write signal line (hereinafter, R / W signal line) 8.
Memory access trace control circuit 4 and central processing unit 1
And a trace information storage memory 3 for storing the address and data of the main storage device 2 accessed by.

Next, the operation of this embodiment will be described.
In normal times, when the central processing unit 1 accesses the main memory device 2, the memory access trace control circuit 4 uses the information on the address bus 7 and the data bus 8 at the timing of the R / W signal on the R / W signal line 8. Is stored in the address of the trace information storage memory 3 designated by the pointer of the memory access trace control circuit 4. The pointer is incremented by “+1” when one piece of information is stored. When a failure occurs, the central processing unit 1 notifies the memory access trace control circuit 4 of the failure occurrence through the failure notification signal line 5, and the memory access trace control circuit 4 stops storing information in the trace information storage memory 3 and The final pointer is stored in an internal register (not shown). The failure is analyzed by tracing the contents of the trace information storage memory.

[0008]

As described above, according to the present invention, the failure information storage means including the trace information storage memory and the memory access trace control circuit is added to the central processing unit, so that the failure occurs in the central processing unit. It is possible to save the movement, and it is possible to shorten the failure analysis time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a central processing unit with a failure information storage function of the present invention.

[Explanation of symbols]

 1 central processing unit 2 main memory unit 3 trace information storage memory 4 memory access trace control circuit 5 fault notification signal line 6 address bus 7 data bus 8 R / W signal line

Claims (1)

[Claims] 1. A fault, comprising: a trace information storage memory for storing an address and data of an accessed main storage device; and a memory access trace control circuit for controlling reading / writing of the trace information storage memory. Central processing unit with information storage function.