JPS59226954A - Type-based recorder of memory access - Google Patents

Abstract

PURPOSE:To attain the effects which are effective to the program debug and evaluation by using a type-based recorder of memory access to record the presence or absence of accesses and the access-based information for each address of a memory. CONSTITUTION:A type-based recorder PDBG of memory access is connected to a system bus BUS for debug or evaluation. When a program to be tested is driven, the data, etc. which are transferred between a processor CPU and a memory MEM are delivered to the corresponding buses respectively. All types of information are recorded to a trace memory in the PDBG in response to addresses when the CPU writes data to the MEM and reads data out of the MEM. In such a way of recording, it is possible to understand at a glance the changing process of a certain memory as well as its memory. This is effective to the program debug and evaluation.

Description

Detailed Description of the Invention (a) 1 Technical Field of the Invention The present invention relates to a memory access type recording device, and particularly to a memory access type recording device that is effective for program depacking and evaluation. .

Prior Art and Problems When a program to drive a digital time-division electronic exchange is created and actually run, various program errors such as memory corruption occur, and it becomes necessary to depack the program. Even if there is no line that destroys memory, it is often necessary to investigate insufficiencies in memory usage and modify and improve the created program.

As described above, the conventional technology has the disadvantage that improving program creation is a very time-consuming task.

(C)9 OBJECTS OF THE INVENTION An object of the present invention is to provide a memory access type recording device that is effective in program depacking and evaluation in order to improve conventional program creation and modification methods.

(d) 0 Structure of the Invention According to the present invention, in a system having a processor and a memory, reading of address information and instructions when accessing the memory from the processor is difficult. This is achieved by providing a memory access type recording device characterized in that it receives access type information identifying whether it is a write, and records whether or not there is an access and the access type information in units of addresses of the memory.

(e) 8 Embodiments of the Invention FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, CPU is a processor, MEM is a memory, 10C is an input/output device, 5BUS is a system bus, and PDBG is a memory access type recording device according to the present invention.

FIG. 2 is a diagram illustrating one embodiment of a system bus according to the present invention. In the figure, REQ is a bus access signal, ACK is a response signal to the bus access signal REQ, and MEM/
IO is access to memory MEM or input/output device IOC
W/R is a write/read identification signal, 1/P is a signal that identifies whether to access the memory MEM, instruction I or operand (data) P, Address is the address, and Data is the The data are shown respectively.

FIG. 3(a) is a diagram showing the sequence when the processor CPU writes data to the memory MEM, and FIG. 3(b) is a diagram showing the sequence when the processor CPU reads data from the memory MEM. It is.

The present invention will be described in detail below with reference to the drawings.

When attempting to depack or evaluate a program to be tested using the memory access type recording device according to the present invention, connect the memory access type recording device PDBG to the system bus 5BUS as shown in FIG. do.

The system bus 5BUS is configured as shown in FIG.

When the program to be tested runs, data exchanged between the processor CPU and the memory MEM,
Address Address, identification signal 1/P, identification signal W/R, iii separate signal MEM/IO, hash access signal REQ, and response signal ACK are output to corresponding buses, respectively.

For example, when writing data to the memory MEM from the processor CPU, first write the data to the memory MEM as shown in Cal in Figure 3.
Signal MEM/10 for identifying access to M or input/output device 10C, write/read identification signal W/R, signal 1 for identifying whether instruction ■ or operand (data) P when accessing memory MEM /
Four types of information are applied: P and Address indicating which address in the memory MEM is to be written, and then a bus access signal REQ is applied.

Note that the data Data is the memory access type recording device PD.
Not input to BG.

By applying this bus access signal REQ, all of the above four types of information are input to the memory access type recording device PDBG according to the present invention, and this information is stored in the trace memory in the memory access type recording device PDBG. (for example, approximately 64, which is arbitrarily selected depending on the size of the target program).

When the processor CPU reads data from the memory MEM, all information is similarly recorded in the trace memory in the memory access type recording device PDBG in correspondence with the address, as shown in [b] of FIG.

As described above, the memory access type recording device P according to the present invention
Since all information is recorded in the trace memory in the DBG in an address-corresponding format, it becomes obvious at a glance which address's memory changed over what process, and becomes effective data for program depacking and evaluation.

FIG. 4 is a diagram showing the configuration of a memory access type recording device according to the present invention. In the figure, CTL is a control circuit, RAM
is a random access memory used as a trace memory, DISP is a display, AC is an address counter, SEL is a selection circuit, AMPI, AMP2,
AMP3 is an amplifier, INVI and I#V2 are in-hook, G1 and G2 are AND gates, and G3-G5 are OR gates.

As mentioned above, the signal MEM/10 identifies access to the memory MEM or the input/output device IOC, the write/read identification signal W/R, and the instruction I or operand (data) when accessing the memory MEM.
Four types of information are applied: a signal I/P that identifies whether the data is written in the memory MEM, and an address Address that indicates which address in the memory MEM is to be written, and then a bus access signal REQ is applied. By applying this bus access signal REQ,
The control circuit CTL operates, takes appropriate timing, issues a write signal to the trace memory RAM, and determines whether the command is to write data (Dll) or read data (DI).
2) or instruction (DIO),
Write to the specified address in the trace memory RAM.

Amplifier AMP2, AMP3, i7verter INV1, IN
V2, AND gates G1 and G2 constitute the above-mentioned identification circuit.

Note that OR gates 03 to G5 already have instructions that use arbitrary addresses, and those (DIO) are “
1", when a command to write data (or read data) to that address comes, the previous (DIO)'s "1"
This is a circuit that takes a "0 OR" after the signal is turned off once.

Further, by setting the address counter AC from the outside and applying a selection signal to the selection circuit SEL, the contents of a desired address in the trace memory RAM can be displayed on the display DISP.

(f) 1. Effects of the Invention As explained in detail above, according to the present invention, it is possible to see the memory usage status at a glance, thereby realizing a memory access type recording device that is effective for program depacking and evaluation. There are great effects that can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a diagram illustrating one embodiment of a system bus according to the present invention. FIG. 3(a) is a diagram showing the sequence when the processor CPU writes data to the memory MEM, and FIG. 3(b) is a diagram showing the sequence when the processor CPU reads data from the memory MEM. be. FIG. 4 is a diagram showing the configuration of a memory access type recording device according to the present invention. 3Pt Town Figure 2

Claims (1)

[Claims] In a system having a processor and a memory, address information when accessing the memory from the processor and access type information identifying whether to read an instruction, read data, or write data are received, and an address unit of the memory is received. A memory access type recording device, characterized in that it records whether or not there is an access and the access type information.