JPS63298452A - Tracer circuit - Google Patents

Abstract

PURPOSE:To collect the trace information in accordance with the working state of a system by controlling the start and the stop of recording the control information to a trace memory in response to the trace control information which is set previously in response to the control information stored in an information processor and also shows said start and stop of the recording of the control information. CONSTITUTION:The instruction bits for the start and the stop of a tracing action are written into a trace control memory 5 which uses a part of a trace objective signal 11 as an address. Then the supply and the stop of the address are controlled to a trace memory 2 in accordance with said instruction bits. At the same time, the supply/stop of a write enable signal 24 is controlled so that the start/stop of writing of a write data signal (trace subject signal 11) is controlled to the memory 2. In such a way, the start/stop of a tracing action is flexibly controlled and set freely. Then the trace information can be collected in response to the working state of a system.

Description

TECHNICAL FIELD The present invention relates to a tracer circuit, and more particularly to a tracer circuit that sequentially records control information within an information processing device.

BACKGROUND TECHNOLOGY In general, a tracer circuit includes a trace counter that increases in synchronization with a system clock, a trace memory that sequentially records microinstruction addresses and various control information using the output value of this trace counter as an address, and a trace counter that updates and updates the trace counter. It consists of a trace control circuit that controls writing to the trace memory.

Conventionally, in a tracer circuit configured in this way,
Tracing is started by an instruction from an external unit (for example, a diagnostic unit, etc.), and similarly, tracing is stopped by an instruction from an external unit or when a certain hardware condition is met (for example, by a hardware software error occurred).

In such conventional tracer circuits, the trace start and stop conditions are fixed in terms of hardware.
The drawback was that the trace operation could not be controlled flexibly.

In other words, in the case of failures that occur when multiple conditions are combined, the setting of stop conditions is limited, so it is not possible to collect trace information in a timely manner, or the I/O (1nput 10putput) related control processor When performing address tracing, if there is a part such as a wait routine that runs at the same address for a long time, most of the trace information will be occupied by the address of that routine, and no previous address information will remain. The problem was that there was no.

Purpose of the Invention The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional methods.It is possible to flexibly control the start and stop of tracing, and to collect trace information that matches the operating status of the system. The purpose of the present invention is to provide a tracer circuit that can perform the following steps.

Structure of the Invention A tracer circuit according to the present invention is a tracer circuit having a trace memory for sequentially recording control information in an information processing device, the tracer circuit being set in advance in correspondence with the υ control information, and the Storage means for storing trace control information indicating start and stop of recording of control information is provided, and the trace control information is read from the storage means in response to input of the control information, and the trace control information is stored in the trace memory in response to input of the control information. The present invention is characterized in that the start and stop of recording of control information is controlled.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a tracer circuit according to an embodiment of the present invention includes a register 1, a trace memory 2, a trace counter 3, a multiplexer 4, and traces t and II.
It is composed of a tll memory 5 and a trace control circuit 6.

The register 1 samples a trace target signal 11 supplied from an external unit (not shown) every clock. Trace memory 2 receives write data signal 1 from register 1
2 is input, and data is written to 1 in accordance with the trace memory address signal 14 from the trace counter 3 and the write enable signal 24 from the trace control circuit 6.

It also sends out the read data signal 13 read from the address indicated by the trace memory address signal 14 from the trace counter 3.

The trace counter 3 is a counter that performs a counting operation when the counter enable signal 23 from the trace υ1111 circuit 6 is logic "1", and the counter value indicates the address of the trace memory 2 as the trace memory address signal 14.

The multiplexer 4 inputs part of the write data signal 12 from the register 1 and the address signal 15 supplied from the external unit, and writes instruction bits for starting and stopping the trace operation from the external unit to the trace control memory 5. At the time of tracing, select the address signal 15 supplied from the external unit, and at the time of tracing, select a part of the write data signal 12 from the register 1 and send it to the trace control memory 5.
output as an address.

An address is specified in the trace control memory 5 by an address signal 16 from the multiplexer 4, and a trace start instruction signal 17 and a trace stop instruction signal 1B from an external unit are written to that address. The trace start instruction signal 17 written in the trace υJtlO memory 5 instructs the start of tracing, and the written trace stop instruction signal 18 instructs the stop F of the trace. The trace start instruction signal 17 and trace stop instruction signal 18 written in the trace control memory 5 are read out with their addresses specified by the address signal 16 from the multiplexer 4, and the read trace control signals 19 and 20 are read out by the trace control circuit. The trace control signals 19 and 20 control the start and stop of the trace operation.

The trace control circuit 6 controls the start and stop of the trace operation. This trace operation starts when the trace control signal 19 from the trace control memory 5 and the trace control signal 21 supplied from the external unit are "1", and the trace operation stops when the trace control signal 19 from the trace control memory 5 and the trace control signal 21 supplied from the external unit are "1". This is performed when the control signal 20 and the trace control signal 22 supplied from the external unit are "1".

From trace control memory 5! - Trace control signal 19 and trace control signal 21 from external unit are “1”
When this happens, the counter enable signal 23 becomes "1" and the trace counter 3 starts counting. At this time, the write enable signal 24 is outputted one pulse at a time for each clock cycle, the old data signal 12 is iq loaded into the trace memory 2, and the trace operation is started.

Trace control mta number 20 from trace v control memory 5
and the trace control signal 22 from the external unit is “1”.
When the time reaches 0', the counter enable signal 23 becomes 0', and the trace counter 3 stops counting.

At this time, the write enable signal 24 also becomes 0'', the writing of the write data signal 12 to the trace memory 2 is stopped, and the trace operation is stopped.

FIG. 2 is a diagram showing a memory map of the trace control memory 5 of FIG. 1. Assuming that the bit width of the trace target signal 11 is 40 bits, 8 bits of the address of the trace control memory 5 are supplied, and for each address, a trace start instruction signal 17 and a trace stop instruction signal for controlling the trace operation at t11 are supplied. 18 is written.

FIG. 3 is a time chart showing the operation of one embodiment of the present invention. The operation of one embodiment of the present invention will be explained using these FIGS. 1 to 3.

To perform the trace operation, the external unit clears all the contents of the tracemi control memory 5 to "°0", and then clears the tracemi control memory 5 at address "0000100G" (hexadecimal 08) as shown in FIG.
Assume that the trace start bit of 11) is set to "1" and the trace stop bit of address "1001001G" (hexadecimal 92+1) is set to "1".

At this time, when the 8 bits of the write data signal 12 from register 1 become 0811° in cycle 2,
The trace control signal 19 from the trace control memory 5 is “
1” is output, instructing the start of the trace operation.T
In the third cycle, the counter enable signal 23 becomes “
1'', the trace counter 3 starts a counting operation, an address is supplied to the trace memory 2, and a write enable signal 24 is outputted to start writing the write data signal 12 to the trace memory 2.

In the Tn cycle, when the 8 bits of the write data signal 12 from the register 1 become "92", "°1" is output to the trace control signal 20 from the trace control memory 5, instructing to stop the trace operation. .In the Tn+1 cycle, the counter enable signal 23 goes to °“O.
II, the trace counter 3 has a count value rm+I
Indicate J to stop the counting operation and save trace memory 2.
At the same time, the write enable signal 24 is fixed at 0'', and writing of the write data signal 12 to the trace memory 2 is stopped.

Although the trace operation start and stop instruction bits (trace control information) are written to one address each in the trace control memory 5, the trace operation start and stop instruction bits may be written to multiple addresses. It is also possible to trace the start of the I-race operation.
It is also possible to set it from an external unit using the Il signal 21 and write only the instruction bit for stopping the trace operation into the trace i+m+ memory 5.

In this way, the instruction bits for starting and stopping the trace operation are written in the trace control memory 5 whose addresses are part of the signal to be traced 11, and the supply and stop of the address to the trace memory 2 are controlled according to the instruction bits. At the same time, the supply and stop of the write enable signal 24 are controlled by 1tIQIIl to control the start and stop of writing of the write data signal 12 (trace target signal 11) to the trace memory 2, thereby improving the trace operation. Start and stop can be flexibly controlled. By freely setting the start and stop of this trace operation, it is possible to collect trace information that matches the operating status of the system.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, according to the present invention, according to the trace control information that is set in advance in accordance with the control information within the information processing device and that indicates the start and stop of recording of the 1lItld information to the trace memory. By controlling the start and stop of recording control information to the trace memory, the start and stop of tracing can be flexibly started and stopped.1. lJ
This has the advantage of being able to collect trace information that matches the operating status of the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a diagram showing a memory map of the trace control memory of FIG. 1, and FIG. 3 is a time chart showing the operation of one embodiment of the present invention. It is. Explanation of symbols of main parts 1...Register 2...Trace memory

Claims (1)

[Claims] A tracer circuit having a trace memory for sequentially recording control information in an information processing device, the trace being set in advance in correspondence with the control information and indicating the start and stop of recording of the control information in the trace memory. A storage means for storing control information is provided, and the start and stop of recording of the control information in the trace memory is controlled in accordance with the trace control information read from the storage means in response to input of the control information. A tracer circuit characterized by: