JPS60159951A - Tracing system in information processing device - Google Patents

Abstract

PURPOSE:To execute an instruction counter trace and an event trace of only a necessary part by providing a trace control memory which has stored trace information for showing whether a trace is necessary or not, and setting suitably the contents of trace control information. CONSTITUTION:A trace control memory 5 of a trace device 10 receives an address signal from an address bus 9A of a common bus 9. On the other hand, a trace control device 6 receives a control signal from a control bus 9C of the common bus 9. When a prescribed control signal is received, a processor 1 detects a fact that an access of some device or a memory has been started, and in this case, trace control information is read out of the trace control memory 5. Subsequently, in accordance with this trace control information, prescribed information loaded on the common bus 9 is fetched, and control for storing it in a trace information memory 7 is executed.

Description

[Detailed Description of the Invention] [Technical field to which the invention pertains] This invention relates to a tracing method in an information processing device, and in particular, it is used to check program errors, device operations, etc. in the information processing device, and detect faults, etc. This is a tracing method for the instruction counter trace (hereinafter referred to as ICl-race) and event trace (hereinafter referred to as Ev trace) of an arithmetic processing unit (processor), etc., performed in order to analyze the The present invention relates to an efficient tracing method that allows tracing of specific locations and eliminates the need to change the tracing program.

[Prior art and its problems]

In general, ICl-race is performed to record the history of the flow of programs executed by a processor, and E-trace is performed to record commands and data with peripheral devices such as communication devices and input/output devices.

It is used to store the history of interactions such as interrupts and interactions with other systems via these devices.

By employing such IC traces and EV) traces, it is possible to know what kind of history was followed when a failure occurred, and it becomes a powerful means for failure analysis. In addition, it becomes easy to check for errors in the created program.

Conventionally, IC trace is performed by tracing the address signal in the instruction fetch cycle by determining the status signal output from the processor. However, in reality, it is often sufficient to trace only the vicinity of instructions that change the flow of the program, such as branch instructions or subroutine call instructions; The method of collecting all driving history uniformly has the drawback of extremely inefficient use of memory for tracing.

To compensate for these shortcomings, there are methods that decode instructions zenered by the processor and perform IC tracing only when the instructions change the flow of the program. A tracing method has been proposed, but the former requires a large amount of hardware for decoding instructions, and the latter also inevitably requires a similar increase in hardware.

On the other hand, conventionally known E-trace is a method in which a processor executes a predetermined diagnostic program. This will increase the processing time. Furthermore, when the E-trace program is run, the time relationship between interactions with peripheral devices changes, and the failures that would occur without tracing may no longer occur.

Furthermore, in this type of E-trace, when a fault occurs, tracing is often focused on the target fault in order to analyze the fault, but in that case, it is necessary to change the program, and the program is This is a problem because there is a risk that a change error could lead to a new failure.

[Purpose of the invention]

The purpose of the present invention has been made in view of the drawbacks and problems of the prior art, and is to eliminate such drawbacks and problems, and to implement only the necessary parts using simple hardware such as IC) lace and E. (2) To provide a tracing method for an information processing device capable of tracing.

[Key points of the invention]

The features of this invention to achieve the above objects are as follows:
A trace control memory storing trace information indicating whether tracing is necessary is provided corresponding to the address space of the processor, and when the processor accesses the address space for the purpose of command Zener, communication, input/output control, data transfer, etc. It controls the storage of trace information according to the contents of the trace control memory, and its configuration is as follows:
A trace control memory stores at least trace control information indicating whether tracing is necessary and is accessed by an address sent from the processing device; a trace information memory stores traced information; and a trace control memory that stores trace control information indicating whether tracing is necessary; When information is transferred between A trace control device is provided for controlling storage in the memory.

By doing this, it is possible to trace only the information that needs to be traced according to the trace control information, and it is possible to trace only the necessary parts of the IC (IC) race or EV trace without creating a special program.

In this specification, access is a broad concept that is not limited to simply referencing or reading data, but also includes writing, data transfer, command sending, etc., and designation of a transfer destination when transferring information. use.

[Embodiments of the invention]

Examples will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

1 is a processor, and includes a processor 1 and a program memory 2 . Data memory 31 peripheral devices 4. The trace devices 10 are connected to each other via a common bus 9 to form an information processing system.

Here, the trace device 10 includes a trace control memory 5.
Trace control device6. It is equipped with a trace information memory 7 and a clock 8. Here, the trace control memory 5 of the trace device 10 receives an address signal from the address bus 9A of the common bus 9. On the other hand, the trace control device 6
From the control bus 9C of the common bus 9 to the control t
I received the M issue. When the predetermined control signal is received, it is detected that the processor 1 has started accessing a certain device or memory, and at this time, trace control information is read from the trace control memory 5. Then, in accordance with this trace control information, control is performed to take in predetermined information carried on the common bus 9 and store it in the trace information memory 7.

Note that the common bus 9 includes an address bus 9A and a data bus 9.
D, and a control bus 9C.

Also, in the figure, A, C, and D are addresses, respectively.

It represents the control and data input/output terminals.

Now, the processor 1 accesses the data memory 3 and the peripheral device 4, for example, and exchanges data or transfers predetermined data with them via the common bus 9. These data memory 3 and peripheral devices 4 are allocated and mapped to predetermined areas of the address space of the processor 1.

In performing such processing, the processor 1 accesses the program memory 2 to fetch instructions, and accesses the data memory 3 to reference and store data. It also accesses peripheral devices 4 such as communication devices and input/output devices for communication and input/output.

The trace control information read from the trace control memory 5 here is information stored at a location corresponding to the address accessed by the processor 1. Here, program memory 2. As shown in FIG. 2, the mapping relationship between the address space accessed by the processor 1 and the address area of the trace control memory 5, to which the register 4a of the data memory unit 3 and the peripheral device 4 are allocated, can be accessed by the processor 1. An address area 21 of the trace control memory 5 is arranged corresponding to the access space 20. Note that the correspondence between the addresses of the trace control memory 5 is as follows:
Of course, it is not necessary to correspond to all 0's, and it is sufficient to limit the trace to only the space where tracing is necessary.

Now, in accordance with the read trace control information, the trace control device 6 sends a control signal to the trace information memory 7 for fetching predetermined information from the common bus 9, depending on whether tracing is necessary. .

Here, the predetermined information stored in the trace information memory 7 includes address information obtained from the address bus 9A, data information (data, command information) obtained from the data bus 9D, and control information (data, command information) obtained from the control bus 9C. (read information, write information, status information, etc.), various information necessary for tracing 1 For example, clock 8
This information includes information regarding the time since.

By the way, the trace control device 6 controls selectively storing such predetermined information in the trace information memory 7 as necessary, and for this purpose, in this embodiment,
This takes the configuration shown in Figure 3.

In FIG. 3, reference numeral 11 indicates the structure of this trace control information, and the first information position 12 is a data area indicating a trace request, and is represented by, for example, a flag focus. The second information position 13 is a data area indicating a request to stop tracing, and is similarly expressed in flags, etc. The third information position 14 indicates a trace information selection code. The trace information selection code is for selecting data to be traced. For example, it is often not necessary to trace the trace time every time, so you can trace it selectively.
Data may not be present when an instruction is fetched. Also,
When data is 1-laced, all bits of the address are unnecessary, as long as it can be distinguished from other data. For this reason, it is possible to select only the necessary 1 to race information in this trace information selection code.

The next fourth information location 15 is a data area indicating a trace identification code. This trace identification code is used, when the selection code of trace information indicates data selection, to distinguish the data portion from other data and to compress the trace information.

In addition, a request for incrementing the trace address of the trace information memory 7 that stores trace information may be defined to store only a predetermined portion of trace information as necessary, and such instructions may be provided. For this purpose, it is possible to refer to any of the information in the first to fourth information positions, or to incorporate such definition information as part of any of the information. For example, the trace address may be updated individually according to the content by referring to the trace request for the first information location 12.

This is effective for partial tracing when there is an interrupt, for example, and the storage area of the trace information memory 7 can be effectively utilized. In other words, when there is an interrupt, control of the interrupt program generally starts from a specific preset address, so the address can be updated from the point at which that address is specified. , it is possible to provide an effective means for analyzing failures caused by interrupt timing.

The trace control device 6 of the trace device 10 reads such trace control information from the trace control memory 5 when the processor 1 accesses it, and decodes it.

Then, the address of the trace information memory 7 is updated as necessary to control writing of trace information.

FIG. 4 is a block diagram showing a specific configuration of such a trace control device 6, and FIG. 5 is a timing chart for explaining its operation. Note that the same reference numerals as in FIG. 1 indicate the same things.

In this example, the address of the trace information memory 7 is updated in accordance with the access by the processor 1, and for ease of understanding, only trace request information and trace stop request information are written to the trace information memory 7 as write control information. Show what you used.

61 is a control circuit of the trace control device 6, 62 is a flip-flop, 63 is an address counter for the trace information memory 7, and 64 is an AND gate.

When accessing another device, processor 1 first sends an address signal 22 onto address bus 9A, and when writing data, sends write data 23 onto data bus 9D, as shown in FIG. Thereafter, the processor 1 sends a write signal 24 onto the control bus 9C. In addition, in the figure, 2.32 indicates a glue point in the case of a lead.

Here, the address signal 22 on the address bus 9A is input to the trace control memory 5, and the write signal 24 on the control bus 9C is input to the control circuit 61. When the control circuit 61 receives the write signal 24 via the signal line 600, it sends the read command 25 to the trace control memory 5 via the read line 601 to read the trace control information 26, and also reads the write timing signal line 605. A write command signal is sent to the AND gate 64 via the AND gate 64.

At this time, the read address of the trace control memory 5 from which the trace control information 26 is read matches the address sent from the processor 1.

Then, a trace request signal of the trace control information 25 (with the trace request information as a flag bit) is sent to the trace request signal line 602, and a trace stop request signal (with the trace stop request information as the flag bit) is sent to the trace stop request signal line 603. Read out.

Here, the flip-flop 62 is normally in a set state and sends an output of "1" to the AND gate 64 via the signal line 604, and receives, for example, a tracest knob request signal as "flag 1". It is reset and stores the invalid state. In other words, the flag is “
When a trace request signal indicating a trace request set to 1" is read, the read trace stop request signal (flag "1") resets the flip-flop 62 and sets its Q output to 0". do. This Q output ″O
'' is sent to AND gate 64 to disable the AND condition and disable tracing.

Now, from the control circuit 61 to the write timing signal line 605
The write command signal sent above is combined with the trace request signal from the trace control memory 5 by an AND gate 64.
- An AND condition with the signal from the flip-flop 62 that determines whether the race is valid or invalid is taken and sent to the trace information memory 7 via the write signal line 606 as the write command signal 27 of the trace information memory 7.

The conditions for sending out this write command signal 27 are when the flag bit 1- of the trace request signal is "1" (trace requested) and the flag bit of the trace stop request signal is "0" (trace stopped). be.

When predetermined information selected according to the trace control information is loaded into the trace information memory 7 by this write command signal 27, the control circuit 61 writes an address counter that stores the address of the trace information memory 7. The address count up signal 28 is sent to the address counter 63 via the count amplifier signal line 607.
Update the value of Then, connect this to the address signal line 60
8 to the trace information memory 7.

In this way, as long as there is a tray ridge request, predetermined information is sequentially stored in the trace information memory 7 according to the update of the address.
will be stored in.

Here, the flag bit of the trace stop request signal is “
When there is a trace stop request of "1", the flip-flop 62 is reset and its Q output becomes "O", resulting in a trace invalid state.

As a result, the AND condition is not satisfied in the AND gate 64, and henceforth, the write command signal 62 from the trace control device 6 to the trace information memory 7 will not be generated.

Therefore, no new tracing will be performed.

As can be understood from the above description, in this embodiment, trace information is IMed when the flag as the next trace request signal of the trace control information is set to "1". Therefore, where tracing is not required, this flag may be left as "0". Furthermore, when performing error processing, since tracing is no longer necessary, the trace request stop signal can be set to "1" to prevent further tracing.

Here, the information selected as trace information may be address information as IC trace, or EV)
As a race, along with time data from the clock 8, addresses, data, control information, etc. may be arbitrarily selected and stored in the trace information memory 7. Note that such selection can be realized by storing predetermined information in the trace control memory 5 in advance as trace control information.

Here, the information stored in the trace information memory 7 is read out when a failure occurs, and displayed on a display device, etc., and, if necessary, printed out on a printer etc. for analysis.

Figures 6 (aL, (b), (c) and 7) show one specific example of actually tracing according to the input/output operation program in the embodiment shown in Figure 1. Figure 6(a) shows the flow diagram of input/output processing, and Figure 6(b) shows the flow diagram of input/output processing.
) shows the area of the data memory 3, and FIG. 6(C) shows each register of the input/output device. Further, FIG. 7 is a schematic diagram showing the data storage state of the trace information memory 7.

i6 In each step of the process in Figure 6(a), the step subscript code (tl) indicates a trace request, and (s) indicates a trace stop request.
) (, #IOC is the command register of the input/output device, #IOD is the data register of the input/output device, #
IO3 indicates the status register of each input/output device. Furthermore, as shown in Figure 6(b), #FL
G indicates a flag storage area of the data memory 3, and #STS indicates a status information storage area of the data memory 3.

First, in step ■, program 1 is started as an input/output operation program, and processor 1
As shown in FIG. 7, when the process of placing 0'' in #FL and G is performed, the time 102 indicated by the clock 8 is
0 on the time plane 31, write/read control signal “O”
(read) is in tlH2 of W/R, and the start address of program 1 (program 1-1 address) is in address column 3.
3 and the instructions of the program 1-1 are stored as data 634 in the trace information memo I77 as trace information.

In the next step (2), the processor 1 transfers data to the input/output device #IOD via the common bus 9. As a result, time 1o2t, W
"1" (write) in /rT column 32, address column 33
The #IOD address is stored in the #IOD address, and the write data is stored in the data column 34, respectively.

Next, proceeding to step (2), processor l transfers a write command for outputting predetermined data to the input/output device to #IOC of the input/output device. As a result, the time 1021°W/R column 32 shows "1" on the time screen 31 as 1 to race information.
(Write), enter #1 in the address field 33. Write command data is stored in the OC address and data columns 34, respectively. In addition, as shown by the symbol ft) in FIG. 6(C), each register #IO3, #IOD,
When accessing the #IOC, a trace request is set correspondingly, so information is traced.

The processor 1 then moves to a time monitoring loop step to monitor responses from the input/output devices. This step is from step ■ to step ■. That is,
In step ■, set the number of loops corresponding to the monitoring time in the variable Ro, and in step ■, determine whether the #FLG flag is "#FLG=O" to check the response from the input/output device, and then
When the ES condition is met, the variable RO is the number of loops at step ■.
is subtracted by 1, and in step ■ it is determined whether the variable Ro has become "0". If the YES condition is determined, N01 is determined in step ■.
]", a trace is recorded as a malfunction, and error processing begins in step (■).

On the other hand, when the input/output device is started in the process of step (2), the program 2 is started and the time 1040 is displayed on the time plane 31 as trace information. In column 32 of W/R, aO” (
Read), the start address of program 2 (program 2-1 address) is stored in address field 33, and the command in program 2-1 is stored in data field 34, respectively.

Here, the input/output device performs an output operation.

When the process is finished, a result indicating the completion is written to #IO3, and a completion interrupt is issued to the processor 1.

When the processor 1 receives this interrupt, the program 2 reads data from #IO3 in step (a) of the program 2 and stores it in the variable R2. As a result, as trace information, the time xo4o is stored in the time field 31, "0" (read) is stored in the v/n field 32, the address of t[O3 is stored in the address field 33, and the data is stored as read status in the data field 34. .

Then, in the next step ■b, the variable R2 is processed as status information indicating the next predetermined process, and in the step ■C, the value of the variable R2 is transferred to #STS. Next step d
Then, processor 1 sets "1" to #FLG and notifies program 1 of the end of processing. As a result, as trace information, time 31 before time 1042. W/H column 3
2 is stored as "1" (write), the address field 33 stores the address of #STS, and the data field 34 stores data as the processing status.

Here, program 1 is notified of the end by setting #FLG to "1" from program 2, and if this is within the monitoring time, a No condition is determined in step (2), and # in step [phase]. ST.

The data of S is set to variable R1. As a result, as trace information, 1 at time 1046°W/R 31 before time
“0” (read) in lI32, #S in address field 33
TS address, data lI! Data as processing status is stored in I34.

Then, in step 0, it is determined whether the content entered in variable R1 is process A, and if the YES condition is met, process A is entered in step 2. On the other hand, if the No condition is met, the process moves to step @, and it is determined whether the content entered in the variable R1 in step @ is the process B. If the YES condition is the result, the B process is entered in step 0. Here, if it is neither the A process nor the B process, the determination at step @ results in a No condition, and the process moves from step @ to step ■, where error processing is entered. At this time, in step O, the trace information is 31 before time 1047. “0” in column 32 of W/roof
” (read), program 1-11 in address field 33
Address (address of instruction for A judgment process), data column 3
4 respectively store the instructions of the program 1-1. In addition, in step @, the trace information is 1047 before time 31, "O" (read) in column 32 of W/,
The program 1-12 address (address of the instruction for the B determination process) is stored in the address column 33, and the instruction of the program 1-12 is stored in the data register 134, respectively. Then, in step ■, the trace information is 31 before time ro4.
O″ (lead) to #1Il132 of s, w/H.

Program 1-9 address (address of error handling instruction) in address field 33, program 1-9 in data field 34
Nine instructions are stored respectively. After this, a 1-race stop request is issued, flip-flop 62 is reset, and tracing is thereafter stopped.

If such trace information is read out and displayed on a display device, etc., it can be seen that execution of program 1 started at time 1020, and that error processing was started at time 1048 due to a failure, and the data You can check the contents of each data in column 34, such as whether the command was valid or not, whether the output data was correct or not, how long the input/output device was executed, and whether the status was valid or not. It becomes possible to check.

Here, since tracing is not performed after tracing is stopped in response to a trace stop request, the history that led to the occurrence of the above-mentioned failure remains in the trace information memory 7.

In this way, if you examine the trace results, you can not only trace the running of the program (but also know the data exchanged with the input/output device, the results of processor processing, the execution time of the input/output device, etc.), and find out where the cause of the failure is. You can easily find out if there is one.

Now, if you store trace control information such as whether tracing is necessary or not at the address location of the trace control memory corresponding to the program area of the processor, it will be possible to trace only the necessary parts of the IC. Ev tracing can be performed by storing trace control information in an address location of a trace control memory corresponding to an address area of a control register of a peripheral device such as a communication device or an input/output device.

Furthermore, if trace control information is stored in the address location of the trace control memory corresponding to a predetermined data area to be processed by the processor, it is possible to trace the processing status of the processor, thereby controlling the overall operation of the processor. This has the advantage that tracing can be done simultaneously with the same configuration.

Further, by simply changing the contents of the trace control memory, the 1-race target can be easily changed, and tracing can be performed in accordance with the content and degree of the failure.

As explained above, the trace control memory of the embodiment is
It may be a ROM, FROM, or RAM, and may be rewritten from a processor console or the like.

Furthermore, if a direct memory access device (DMA device) is connected to a common bus, the trace device detects which mask device is on the common bus and traces this device at the same time. Yo, a, Yani at the same time c:xylx7. □.

becomes. In this way, the object to be traced in the present invention is not limited to those that correspond to accesses of arithmetic processing units, but can be traced to any processing apparatus that has an access function. good.

In the embodiment, the tracing device is connected to the common bus in advance, but instead of being connected in this way and built into the information processing device, the tracing device is connected to the common bus when a failure occurs. Good too. In this case, the information processing device does not require any trace circuits or programs, and even if the tracing device is connected in the event of a failure, the information processing device will not be affected in any way. .

Furthermore, the trace control information only needs to indicate whether or not tracing is necessary, and a trace stop request, data selection information, etc. are not necessarily required.

In such a case, data will be recorded randomly.

Note that by setting a trace stop request, the trace can be stopped at a necessary point, which not only prevents the history from being destroyed during failure analysis, but also has the advantage of being able to check each block. According to selection information, etc., there is an advantage that stored trace information can be compressed.

In the embodiment, the IC) race and the EVI-race are performed at the same time, but it is of course possible to perform only the IC) race or only the E-trace. Also,
It goes without saying that the present invention can be used not only for failure analysis, but also for debugging during program development, checking the operation of peripheral devices, etc.

〔Effect of the invention〕

As can be understood from the above explanation, according to this invention,
A trace control memory storing control information indicating whether tracing is necessary is provided corresponding to the address space of the processing device, and tracing is controlled according to the contents of the trace control memory in response to access from the processing device. Therefore, by appropriately setting the contents of the trace control information, it is possible to perform one or both of the ICl-race and the EV) race only for the necessary portions.

As a result, you can easily set the race goal without creating a special program, and you can easily race only the necessary parts (IC trace and EV) without the need for a lot of hardware for decoding instructions. This means that it can be done efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is an explanation showing the mapping relationship between the address space accessed by the processor in FIG. 1 and the address of the trace control memory. 3 is a concrete explanatory diagram of the trace control information in the trace control memory in FIG. 1, FIG. 4 is a block diagram showing the concrete configuration of the trace control device, and FIG. Timing chart diagram for explanation, FIG. 6(a)
, , (b), and (C) each show one of the specific examples when tracing is actually performed according to the input/output operation program in the embodiment shown in FIG. )
6(b) is an explanatory diagram of the data memory area, FIG. 6(C) is an explanatory diagram of each register of the input/output device, and FIG. 7 is a diagram of the input/output processing. FIG. 2 is a schematic diagram showing the data storage state of the trace information memory shown in FIG. l --- Processor (arithmetic processing unit). 2...-program memory, 3-data memory. 4- Peripherals; 5-1- Race control memory. 6-) Race device, 7-) Race information memory, 8-
clock. Figure 4 qI-

Claims (2)

[Claims] (1) In an information processing device comprising a processing device and a predetermined device connected to the processing device via a bus and accessed from the processing device, trace control information indicating at least whether tracing is necessary is stored, and the processing device When the processing device transfers information between the trace control memory that is accessed by the address sent from the trace control memory, the trace information memory that stores the information to be traced, and the predetermined device, the access trace control that reads the trace control information from the address of the trace control memory that has been read, and performs control to store predetermined data sent on the bus in the trace information memory according to the read trace control information; A tracing method in an information processing device, characterized by comprising: (2) A tracing method in an information processing apparatus according to claim 1, wherein the trace control information includes information indicating whether tracing is necessary and information for stopping tracing.