JPS6282438A - Control system for interruption of debug in information processor - Google Patents

Abstract

PURPOSE:To acquire a desired request to start an interrupt for debugging while reproducing the same state as actual circumstance by controlling the start of the interrupt for debugging in accordance with contents of write data with respect to a write request to a specific address of a memory. CONSTITUTION:A command and an address sent from a memory access control part 2 through a signal line 201 are compared with comparison information in a comparison command and address register 4 by a comparing circuit 6. Write data sent from the memory access control part 2 through a signal line 202 is compared with comparison information in a comparison data register 5 by a comparing circuit 7. In this case, mask data, which has the same bit width as write information in the comparison data register 5 and write data sent from the memory access control part 2, is stored in a mask data register 9. Its output 901 is used for control of a mask circuit 10. An output 801 of and AND gate 8 is sent to an operation control part 1 as a control signal of the start of the interrupt for debugging.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a control method for debug interrupts in an information processing device.

[Conventional technology]

2. Description of the Related Art Conventionally, in information processing devices, debugging work has been carried out by focusing on memory access operations in order to analyze malfunctions caused by logical mistakes in programs or hardware failures. Conventionally, for such debugging work, a special register is used to store the type of memory request to be detected and the access address, and the desired memory access is performed as the program is executed on the information processing device set to debug mode. hardware support was provided to detect when a debug interrupt condition occurred and report it to software.

[Problems to be Solved by the Invention] Such conventional debugging capabilities are of great use when accessing a specific memory address itself is an action directly linked to the problem to be debugged. It's an asshole. But what about the case of accessing that particular 7 tres? When tf R exists, the debug interrupt yl is notified () (tti) in any of them, so it is actually meaningless to determine whether it is a case 4 (software debug interrupt) l processing routine. Do you need to do something?
Toshiru. In this judgment, for example, when an a1'L-S-- error is reported in memory write rifnis I, the important judgment material is what value the data of that γl-response was rewritten to. It often happens. This kind of check/7ing of lf data is possible with soft pino air, but it usually occurs at -1゛ due to the extra debugging interrupt processing that occurs easily when the desired case appears. The disadvantage is that the case for which you want to collect information cannot be reproduced in debug mode, and the debug function is not effectively utilized.

An object of the present invention is to capture a desired request while reproducing the same state as the real environment, and to interrupt debugging. The purpose is to be able to start up the system without any problems.

[Means for solving problems]

In order to achieve the above object, the present invention provides memory relief l
(1) a first comparison information holding means that holds comparison information regarding the cloak and address; a second comparison information holding means that holds comparison information regarding write data; and a memory request command generated in the information processing device. and address and said first comparison information holding means 6, a first comparison means for comparing the held comparison information; and write data generated in said information processing device and said second comparison information holding means a second comparing means that compares the comparison information according to the contents of mask data indicating bit positions to be compared between the two; and a predetermined comparison between the first comparing means and the second comparing means. Debug interrupt activation means is provided for generating a control signal for activating a debugging interrupt when a result is obtained.

[Effect]

The first comparison information holding means holds the write command as the command type and the specific address as the address, and the second comparison information holding means holds the data for comparison, and the held data 1) When a match is detected in both the first and second comparing means, the debug interrupt starting means starts the debug interrupt If activated, a memory request will be made in which data having the same data pattern as the data pattern at a specific bit position determined by the mask data on the back of the comparison data will be written in response to a specific response. A dehasog interrupt is activated when it occurs.

If the debug interrupt activation means activates the debug interrupt when a match is detected by the first comparison means and no match is detected by the second comparison means, the comparison data will be stored at a certain address. A debug interrupt can be activated when data other than data j having the same data pattern as the data pattern of a specific bit is written.

〔Example〕

The figure is a block diagram of the main parts of an information processing device according to an embodiment of the present invention, in which 1 is an arithmetic control section including all main circuits for controlling and executing arithmetic operations, 2 is an arithmetic control section inside the arithmetic control section 1, A memory access control unit having an interface with the main storage device 3; 4 a comparison command/address register for holding comparison information with actual memory access commands and addresses; 5 a memory access register for use when the memory access is a write command; A comparison data register 6 is used to hold comparison information with actual write data, and a comparison data register 6 is used to store the command and address sent from the memory access control unit 2 to the main storage device 3 through the signal line 201.
A comparison circuit 7 compares the write data sent from the memory access control unit 2 to the main storage device 3 through the signal line 202 with the comparison information held in the comparison data register 5. The comparator circuit to be compared with 8 is Antogame 1. An output 801 of this AND gate 8 is sent to the arithmetic control section 1 as a control signal for activating a debug interrupt.

Further, in the figure, reference numeral 9 denotes a mask data register in which mask data having the same bit width as the write data from the comparison data register 5 and the memory access control unit 2 via the signal line 202 is stored. Output 901 is used to control mask circuit 10. That is, “l” of each bit of the mask data register 9
The portions corresponding to "0" are compared in the comparator circuit 7, but the portions corresponding to "0" are excluded from the comparison and are treated as human data that match (b).

The activation of the debug interrupt in the information processing apparatus of this embodiment is controlled as follows.

Suppose now that the memory request to be detected is a write command, and that we want to cause a debug interrupt only when some bit positions of a specific address are rewritten to a specific data pattern that is known in advance. This is effective when, for example, when a certain program runs, the contents of a specific address are disturbed by a special pattern that would normally not exist, and debugging takes much longer than before. This is one such event.

When performing a debug interrupt as described above, first, the program stores the command of the memory request to be detected and the address value to be accessed as comparison information in the comparison command/address register 4 via the signal line 101, and also stores the above-mentioned specific data as comparison information. Data including the pattern is stored as comparison information in the comparison data register 5 via the signal line 102.

Furthermore, among the data written to the memory, only the bit position corresponding to the bit position to be compared is marked with "1", and the rest are "0".
The resulting mask data is stored in the mask data register 9 via the signal line 105. Then, by setting the debug mode, the input signal 104 of the AND gate 8 is set to "1", and from then on, the comparison circuit 6.7 outputs the comparison match signal 6.
The check for 01,701 is started. At this time, in order to enable the operation of the comparison circuit H7, the signal line 103 is set to "1" as specified by the program.

In the above state, start executing the program in question. Even under normal conditions, this program cannot use the comparison command.
Writing is performed to the address set in the address register 4, but among the data sent from the memory access control unit 2 via the signal wire 202 to that address, the data is compared by the mask data register 9. If the current field is a normal value, there is no match with the comparison data register 5, so the output 801 of the AND gate 8 is 0', and no extra debugging interrupt is generated. Therefore, the same environment as would occur in normal operating mode without setting debug mode is guaranteed. In addition, since the mask data register 9 and the mask circuit 10 are provided, it is possible to avoid comparing fields in which the rewrite pattern during normal operation cannot be predicted in advance among the words of a specific address. The probability of a data interrupt occurring is even lower.

On the other hand, when a desired memory request occurs, that is, abnormal data is written in an unexpected routine in this case, the outputs 601 and 701 of the comparison circuit 6.7 both become "1" and the AND gate 8 A debugging interrupt is generated by the output 801, making it possible to obtain valuable information for locating program bugs or hardware failures.

In the above embodiment, the comparator circuit 7 is configured so that when it detects a match between the data written to the main memory 3 and the data held in the comparison data register 5, the output cuff 01 becomes '1', and the comparison information and I set the debug interrupt to start when data with the same field is written, but
For example, when the comparator circuit 7 detects a mismatch, the output cuff 01 is set to "1", or the signal on the input signal line 701 of the AND gate 8 is inverted and input to the AND gate 8. By doing so, the specific bit position of a specific address is originally! ! It is also possible to configure a circuit deharsing interrupt to be activated when a case in which J1 is destroyed due to a value other than the specific value held is generated.

If the :1-7 pin 1 of the memory request is a read command, the signal line 103 is set to "0" and the comparator 87
By always setting the output cuff 01 to "1" regardless of the data C1:, it is possible to generate a data interrupt only according to the state of the output of the 11S comparison circuit #I6. .

〔Effect of the invention〕

As explained above, the present invention controls the activation of debug interrupts according to the contents of the write data regarding a write request to a specific address in memory, thereby allowing the desired request to be executed while reproducing the same state as the actual environment. tdi j and trigger debug interrupt)
1, which has the effect of improving debugging efficiency. Further, since the second comparing means compares the written data and the comparison information held in the second comparison information holding means according to the contents of the mask data indicating the bit positions to be compared between the two, the specific address An effective debug interrupt can be generated even for data in which there is a field whose rewrite pattern cannot be predicted in advance during normal operation in the I-node.

BRIEF DESCRIPTION OF THE DRAWINGS The figure is a block diagram of main parts of an information processing apparatus according to an embodiment of the present invention. In the figure, ] is an arithmetic control unit, 2 is a memory access control unit, 3 is a main memory, 4 is a comparison command/address register, 5 is a comparison data register, 6.7 is a comparison circuit, and 8 is a comparison circuit.
9 is an AND gate, 9 is a mask data register, 10 is a mask circuit, and 801 is a data interrupt activation control signal.

Claims (1)

[Claims] First comparison information holding means for holding comparison information regarding commands and addresses of memory requests; second comparison information holding means for holding comparison information regarding write data; a first comparing means for comparing a command and address of a memory request with comparison information held in the first comparison information holding means; and write data generated in the information processing device and the second comparison information holding means. a second comparing means for comparing the comparison information held in the first comparing means according to the contents of mask data indicating bit positions to be compared between the two; and the first comparing means and the second comparing means 1. A debug interrupt control method for an information processing device, comprising: debug interrupt activation means for generating a control signal for activating a debug interrupt when a predetermined comparison result is obtained.