JPS6270947A - Control system for debug interruption - Google Patents

Abstract

PURPOSE:To debug a case including a memory access sequence by using a storing means to store the information word containing the debug interruption control information. CONSTITUTION:The addresses and commands stored in the fields of the ADDR and the CMD of a debug information memory circuit 4 are supplied to the input at one side of each of comparators 7 and 8 via signal lines 401 and 402. While the main memory address 202 and a request command 203 given from a memory access control circuit 2 in an actual memory access mode are applied to the input at the other side of each of comparators 7 and 8. The pointer information on a PNT field is supplied to the input at one side of a switch circuit 6. Thus the pointer information on the PNT field is selected only in case the addresses of the memory request are coincident and the commands are dissident respectively. In other cases, the value obtained by adding 1 to the contents of an address pointer 5 is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a debug interrupt control method in an information processing device, and particularly to a debug interrupt control method for controlling debug interrupts based on debug interrupt control information stored in advance.

[Conventional technology]

In conventional information processing devices, debugging with a focus on memory access operations is an effective way to analyze the causes of malfunctions caused by logical errors in programs, hardware failures, etc. It's being used. In other words, by setting the debug mode in advance and setting the type and address of the memory access that you want to detect in a special prepared register, when the desired memory access is issued, it will be detected and a debug interrupt will be reported to the software. There has been extensive hardware support.

[Problem that the invention seeks to solve]

The conventional debug interrupt control method described above is quite useful when targeting a single memory access, but there are generally multiple cases in which a specific address is accessed, and debug interrupts are generated at timings other than the desired memory request. is often reported. For this reason, various judgments are made within the software debug interrupt processing routine,
This method has the disadvantage that it requires a procedure of dynamically resetting commands and addresses for match detection to reach the target memory request.

In addition, due to the occurrence of such extra debugging interrupts and software routine operations, there is a timing lag with the event that should be investigated, and the case that you want to investigate may not be reproduced, which is a drawback. .

In view of the above-mentioned points, an object of the present invention is to provide a debug interrupt control method that allows debugging of a case including a memory access sequence in the same state as in a real environment.

Means for Solving Problem C] The debug interrupt control method of the present invention uses a plurality of pieces of information including address information of a memory request to be detected, command information, pointer information, and debug interrupt control information that indicates whether a debug interrupt is possible or not. information word storage means for storing a word; an address pointer for specifying the address of the information word stored in the information word storage means; and address information read from the information word specified by this address pointer and information for an actual memory request. a first comparing means for detecting a match with address information; a second comparing means for detecting a match between the command information read from the information word specified by the address pointer and the command information of the actual memory request; A debug interrupt report that reports a debug interrupt when a match is detected by the first comparing means and the second comparing means and the debug interrupt control information read from the information word specified by the address pointer indicates that interrupts are enabled. and when a match is detected by the first comparing means and the second comparing means and the debug interrupt control information read from the information word specified by the address pointer indicates that interrupts are disabled, an addition means for adding "1" to the content; and when only the first comparison means detect a match, the pointer information read from the information word specified by the address pointer is stored in the address pointer as new content; and a switching means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The debug interrupt control method of this embodiment includes an arithmetic control circuit 1 that includes all the main parts that control and execute arithmetic operations, and a memory access control circuit 2 that is located within the arithmetic control circuit 1 and has an interface with a main storage device 3. , a debug information recording circuit 4 that records a plurality of debug information words for detecting debug interrupts by memory access, and an address pointer 5 that provides a continuation of the debug information storage circuit 4 and a write address.
, a switching circuit 6 for selecting the input of the address pointer 5, and comparison circuits 7 and 8 for comparing the address information and command information from the memory access control circuit 2 with the address information and command 1'ff information from the debug information storage circuit 4. , an AND circuit 9 which takes the logical product of the output signal 701 of the comparison circuit 7 and the negative output signal 802 of the comparison circuit 8, the output signal 701 of the comparison circuit 7, the output signal 801 of the comparison circuit 8, and the output signal from the debug information storage circuit 4. Debug interrupt control information 404
AND circuit 10 that performs logical product with , address pointer 5
The main part thereof is composed of an adder 11 that adds "1" to the contents of.

In the debug interrupt control system of this embodiment, the format of the debug information word set in the debug information storage circuit 4 by the software program is determined as shown in FIG. In Figure 2, the debug information word ``
The "ADDR" field contains the address of the main memory 3 to be accessed by the memory request (hereinafter abbreviated as main memory address), and the "CMD" field contains the "read for instruction fetch" field that indicates the type of memory request. ”, “Read for operand fetch”, “Write to operand”, etc. are included as encoded commands. The addresses and commands stored in the “ADDR” and “CMD” fields are
It serves as one input of comparison circuits 7 and 8 via signal lines 401 and 402 shown in FIG. The other input of the comparison circuits 7 and 8 is the main memory address 2 at the time of actual memory access given from the memory access control circuit 2.
02 and request command 203.

Due to the match of the main memory addresses, the output signal 7 of the comparison circuit 7
01 becomes "1". Due to the matching of the request commands, the output signal 801 of the comparison circuit 8 becomes "1'. The output signal 802 of the comparison circuit 8 is the negative signal of the signal 80.
It becomes "1" when the commands do not match.

In FIG. 2, "PNT" is a field that stores pointer information to be input data to the address pointer 5, and becomes one input to the switching circuit 6 via the signal line 403. The selection signal of the switching circuit 6 is the output signal 90 of the AND circuit 9.
It is 1. In other words, only when the address of the memory request matches and the command does not match, "PNT
” field pointer information is selected. In other cases, the value obtained by adding “1” to the contents of the address pointer 5 by the adder 11 is selected. is updated when the comparison circuit 7 detects a match between the addresses of the memory requests.

In Figure 2, "C" is a field for storing 1-bit debug interrupt control information, and if there is a memory access where both the main memory address and the request command match, we want to activate the debug interrupt at that point. This is a field that is set to "1" when the match is checked, and "0" when the match check is to be continued with the next entry. Specifically, the function of determining whether to start a debug interrupt or continue matching check with the next entry in accordance with the debug interrupt control information in the 'C' field is realized by the AND circuit 10. The debug interrupt control information 404 is given as an input to the output signal line 10 of the AND circuit 10.
01 is a debug interrupt report line to the arithmetic control circuit l.

Now, let us consider a case where a 4-word debug information word as shown in FIG. 3 is set in the debug information storage circuit 4 via the signal line 101 by software designation from the arithmetic control circuit 1. When the setting of the debug information word shown in FIG. 3 is completed, the address pointer 5 is initialized to "0" by the instruction from the software, and then the program starts running normally on the information processing device.

For example, when a request for "instruction read" to address 'a' is issued, since the addresses match and the commands do not match, the pointer information of the "PNT" field is stored in the address pointer 5 via the switching circuit 6. However, since the pointer information of the debug information word of entry "0" is O", the comparison based on the debug information word of the same entry will be continued. A debug information word of “0” is used until a “write” to address “a” is detected.
When it is detected, the contents of address pointer 5 are incremented by "1" by adder 11, and a match check using the debug information word of entry "1" begins.The first memory access to "b address" is "instruction read". If,
Since the debug interrupt control information of the debug information word of entry "1" is "O", the next step is a match check with the debug information word of entry "2". A memory access of "one operand read to address C" is issued. At that point, the entry “2”
Since the debug interrupt control information in the debug information word for " is "1", a debug interrupt is reported and the series of match check sequences ends. On the other hand, if the first memory access to "b address" is not "instruction read" If
Since pointer information "3" of the debug information word of entry "1'" is set to address pointer 5, entry "3"
This is a match check for a "ride to address d" using the debug information word. Then, to “address d”.

When the memory access for "write" occurs, entry "3" is accessed.
Since the debug interrupt control information of the debug information word "" is "1", the debug interrupt is reported and the series of match check sequences ends.

As in the example above, according to the debug interrupt control method of this embodiment, detection of a memory access to a specific address that occurs after a complex sequence, which has been difficult in the past, can be done by changing the operation timing during the sequence. This can be done effectively without software intervention. Except for the initial settings of the debug information storage circuit, the investigation event can be reproduced without changing the external environment for memory access, so you can work efficiently without wasting time creating the system environment for investigation. I can do it.

In addition, in the explanation of the operation of the above embodiment, the debug information word is 4.
Although the case where the word is used as an example has been illustrated, it goes without saying that the number of words of the debug information word can be increased or decreased as necessary.

〔Effect of the invention〕

As explained above, by providing an information word storage means for storing information words including debug interrupt control information, the present invention enables debugging of cases involving complex memory access sequences that were conventionally difficult to analyze in a real environment. This has the effect of making it easier to proceed while reproducing the same state.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
A diagram showing the format of the debug information word used in the debug interrupt control method shown in the figure, and FIG. 3 is a diagram showing an example of setting data of the debug information word to explain the operation of the debug interrupt control method shown in FIG. It is. In the figure, ■...Arithmetic control circuit, 2...Memory access control circuit, 3...Main storage device, 4...Debug information storage circuit, 5...・Address pointer, 6...Switching circuit, 7.8...Comparison circuit, 9.10...AND circuit, 11...Addition circuit. Ku ′・−・′

Claims (1)

[Scope of Claims] Information word storage means for storing a plurality of information words including address information of a memory request to be detected, command information, pointer information, and debug interrupt control information indicating whether or not a debug interrupt is to be performed; an address pointer that specifies the address of the information word stored in the storage means; and a first comparing means that detects a match between the address information read from the information word specified by the address pointer and the address information of the actual memory request. and a second comparing means for detecting a match between the command information read from the information word specified by the address pointer and the command information of the actual memory request, and a match is detected by the first comparing means and the second comparing means. is detected and the debug interrupt control information read from the information word specified by the address pointer indicates that the interrupt is enabled, debug interrupt reporting means reports a debug interrupt, the first comparison means and the second addition means for adding "1" to the contents of the address pointer when a match is detected by the comparison means and the debug interrupt control information read from the information word specified by the address pointer indicates that interrupts are disabled; A debug interrupt characterized by comprising: switching means for storing the pointer information read from the information word specified by the address pointer in the address pointer as new content when only the first comparing means detects a match. control method.