JP3102381B2 - Task debugging device, task debugging method, and recording medium therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a task debugging device having a break function for temporarily interrupting the processing of a task operated on an operating system.

[0002]

2. Description of the Related Art A task debugging apparatus of this type is used for debugging a task which is a program unit managed by an operating system, and is particularly used for debugging a program shared by a plurality of tasks managed by a real-time operating system. Used for debugging.

Generally, when a plurality of tasks are operated on a real-time operating system, the tasks are switched by issuing a system call or generating an interrupt. That is, the timing at which the tasks are switched and the execution order are determined during the operation of the computer system, and are not necessarily the order intended by the application developer. When the entire system is temporarily suspended (hereinafter, referred to as a break) in such a state and the operation is resumed, the operation may not be able to be reproduced because the state of the system is different from the state when the break is not performed.

Therefore, there is a need for a task debugging technique that allows the entire system to operate without breaking only the designated task and without breaking other tasks.

[0005] As an example of such a task debugging technique, the technique is described in Japanese Patent Application Laid-Open No. H4-157537. In Japanese Patent Application Laid-Open No. H4-157537, a task to be broken is specified for a shared address area shared by a plurality of tasks by causing a target system to be debugged to execute a processing procedure described below. Breakpoint setting is realized.

FIG. 4 is a flowchart showing a procedure of a conventional task debugging technique to be processed by the target system itself.

In FIG. 4, in the conventional task debugging method, an address corresponding to an instruction to be broken is stored in a first register of a target system in advance (step C1), and a task to be broken is stored in a second register. A task identifier for identification is stored (step C2).

When the target system is operated in such a state, the target system compares the address currently being executed with the address stored in the first register (step C3), and if the two addresses do not match, The program is executed as it is until the addresses match (step C4). On the other hand, if the addresses match in the process of step C3, the task identifier of the task being executed and the second
Is compared with the task identifier stored in the register (step C5). If the two task identifiers do not match in the process of step C5, the process returns to step C4 to continue executing the program (step C5). If the task identifiers match in the process of step C5, the task is broken (step C6).

[0009]

However, in the task debugging method as described above, a break is once made at a specified address, it is determined whether or not the currently executing task is the task to be broken, and the task to be broken is determined. If not, the processing of that task is continued, and this processing is repeated until the task to be broken is reached.

That is, since an unnecessary break is performed during the execution of a task, there is a problem that the processing is delayed by that amount and the operation is not performed in real time.

[0011] In the task debugging method described above,
Since the processing is broken using the address trap function of the CPU of the target system, a storage area for storing the program for the address trap processing is required, and there is a problem that the program storage unit of the target system is reduced.

When a break function for breaking a task is provided not in the target system but in a task debugging device for debugging the task,
The output state of each component of the task debug device is generally undefined at the time of a break or resumption of operation of the target system. Therefore, in this case, a process for operating the target system in real time is required even when the output state of each component is undefined.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and performs a break process without overhead (no processing delay) and a program storage unit of a target system. It is an object of the present invention to provide a task debugging device that does not need to use a task.

[0014]

In order to achieve the above object, a task debugging apparatus according to the present invention has a break function for temporarily suspending processing of a target system to be debugged at a desired task and address. A task debugging device used to support debugging, in which a break address, which is an address to be interrupted, is set in advance, and an execution address, which is an address currently being executed in the target system, and the break address. An instruction execution event detector that sets an output signal to an active state when the two match, and sets an output signal to an inactive state when the execution address does not match the break address; and an input address event control signal. When the address signal is in the active state, the output signal is set to the active state, Address event detector output signal control means for setting an output signal to an inactive state when the event control signal is inactive; and a break task identifier which is an identifier of a task to be interrupted is set in advance, and the target system Knows the task to perform,
If the execution task identifier, which is the identifier of the task currently being executed by the target system, and the break task identifier match, the address event control signal is set to an active state, and the execution task identifier, the break task identifier, together if but not identical sets the address event control signal to the inactive state, the terpolymer
When the operation of the get system resumes,
Execution task identifier, which is the identifier of the task executed by the
If the break task identifier matches, the address
Set the active event control signal to the active state, and
Disc identifier does not match the break task identifier
In this case, the address event control signal is set to the inactive state.
An address event control state changing means for setting an address event control state change means for setting an output signal of the instruction execution event detector to an active state, and an output of the address event detector output signal control means. And a break generation circuit for interrupting processing of the target system at a corresponding task and address when a signal is set to an active state.

Further, the task debugging method of the present invention includes a break process for temporarily suspending the processing of the target system to be debugged at a desired task and address, and a task debugging method for supporting the debugging of the task. When an execution address that is an address currently being executed in the target system matches a break address that is a preset address to be interrupted, an output signal is set to an active state, and the execution address and An instruction execution event detection process of setting an output signal to an inactive state when the break address does not match; and setting an output signal to an active state when an input address event control signal is in an active state; Set the output signal to inactive state when the event control signal is inactive Address event detector output signal control processing, when the operation of the target system is restarted, and when the target system recognizes a task to be executed, an execution task identifier which is an identifier of a task currently being executed by the target system and The address event control signal is set to an active state when the set break task identifier which is the identifier of the task to be interrupted is set, and the address event control signal is set when the execution task identifier does not match the break task identifier. The control signal is set to an inactive state and the target
When the target system resumes operation, the target system
An execution task identifier which is an identifier of a task to be executed;
If the break task identifier matches the address
Setting the event control signal to the active state,
When the identifier does not match the break task identifier
Sets the address event control signal to an inactive state
An address event detection process including an address event control state change process, an active signal is output by the instruction execution event detection process, and an active signal is output by the address event detector output signal control process. And a break signal generating process for generating a signal for interrupting the processing of the target system at a corresponding task and address.

Further, the recording medium of the present invention has a break function for temporarily suspending processing of a target system to be debugged at a desired task and address, and a task used to support debugging of the task. A recording medium on which a program to be executed by the debugging device is recorded, and output when the execution address which is the address currently being executed in the target system matches the break address which is a preset address to be interrupted. An instruction execution event detection process of setting a signal to an active state and setting an output signal to an inactive state when the execution address and the break address do not match; and when an input address event control signal is in an active state. , The output signal is set to an active state, and the address event control signal is inactive. In the state, the address event detector output signal control processing for setting the output signal to an inactive state, and when the operation of the target system is resumed and when the target system recognizes the task to be executed, If the execution task identifier which is the identifier of the task being executed matches the preset break task identifier which is the identifier of the task to be interrupted, the address event control signal is set to the active state, and the execution task identifier is set. If the address does not match the break task identifier, the address event control signal is set to an inactive state and the target system
When the system resumes operation, the target system executes
The execution task identifier, which is the
If the task ID matches, the address event
The control signal is set to the active state, and the execution task identifier is set.
If the break task identifier does not match
Address that sets the address event control signal to the inactive state
Address event detection processing including a change event control state change processing, an active state signal is output by the instruction execution event detection processing, and an active state signal is output by the address event detector output signal control processing. And a program for causing the task debugging device to execute a break signal generation process of generating a signal for interrupting the processing of the target system at a corresponding task and address.

The task debugging device configured as described above comprises an address event detector and an address provided therein.
The address event control signal is set to an active state or an inactive state by the event control state changing means when the operation of the target system is resumed and when the task executed in the target system is recognized.

The address event detector output signal control means sets the output signal to an active state when the address event control signal is in an active state, and outputs the output signal when the address event control signal is in an inactive state. Set to inactive state.

At this time, the break generation circuit responds only when the output signal of the instruction execution event detector is set to the active state and the output signal of the address event detector output signal control means is set to the active state. The processing of the target system is interrupted by the task and the address.

Therefore, even when the output state of a component is undefined at the time of a break or resumption of operation of the target system, the address event control of the address event detector is performed.
When the operation of the target system is resumed by the control state changing means , the address event control signal is set to an active state or an inactive state, so that the task debug device interrupts the processing of the target system except for the desired task and address. There is no.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the task debugging device of the present invention.

In FIG. 1, a task debugging device 110 of the present invention is a device having a break function for breaking a process of a target system 120 having a CPU 121 and a program storage section 122 in which a program is stored. The program storage unit 122 has an execution task identifier storage area 123 in which an execution task identifier for identifying a task currently being executed in the target system 120 is stored.

The task debugger 110 has a break address which is an address corresponding to an instruction to be broken, an address of an execution task identifier storage area 123, and a break task identifier for identifying a task to be broken. Are set respectively.

The task debugging device 110 of the present invention determines whether the execution address, which is the address currently being executed in the target system 120, and the break address match, and outputs when the two addresses match. Set the signal to the active state (hereinafter referred to as active),
An instruction execution event detector 112 for setting an output signal to an inactive state (hereinafter referred to as inactive) when two addresses do not match, and an instruction execution event for setting a break address in the instruction execution event detector 112 Setting means 111 and execution task identifier storage area 123
When the execution task identifier is written to the address (when the task to be executed is recognized), it is determined whether the execution task identifier and the break task identifier match, and the two task identifiers match. When the address event control signal for controlling the address event detector output signal control means described later is set to active,
Address event detector 116 for setting an address event control signal to inactive when two task identifiers do not match; address event setting means 115 for setting a break task identifier to address event detector 116; An address event detector output signal control means for setting the output signal to active when the signal is active, and setting the output signal to inactive when the address event control signal is inactive; 1
The break generation circuit 113 that breaks the processing of the CPU 121 of the target system 120 and the processing of the CPU 121 of the target system 120 are resumed when the output signal of the counter 12 and the output signal of the address event detector output signal control means 118 are active, respectively. Let CP
U execution control means 114.

The address event detector 116 determines whether the execution task identifier written in the address of the execution task identifier storage area 123 matches the break task identifier when the operation of the target system 120 is resumed. The address event control state changing unit 119 sets the address event control signal to active when the two task identifiers match, and sets the address event control signal to inactive when the two task identifiers do not match. Have.

By the way, if the task debugging device 110
When configured with a computer having a PU, the task debug device 110 operates not only as a break function for breaking the processing of the target system 120 but also as another function. Therefore, the output state of each component of the task debug device 110 described above is generally undefined when the target system 120 breaks or resumes operation.

Therefore, the target system 120
In order to execute in real time the processing from the time when the operation is restarted to the time when the break address is reached, if the execution task at the time of restarting the operation is a break task, the output signal of the address event detector output signal control means 118 is Must be set to active.

Therefore, the address event detector 116
Not only sets the address event control signal to active or inactive when the execution task identifier is written to the address of the execution task identifier storage area 123, but also changes the address event control state changing means 1.
19, the address event control signal is set to active or inactive even when the operation of the target system 120 is resumed.

In such a configuration, the operation of the task debugging device of the present invention will be described next with reference to FIGS.

FIG. 2 is a flowchart showing a processing procedure of a break task identifier and a break address preset for the task debugging device shown in FIG. FIG. 3 is a flowchart showing an operation procedure of the task debugging device shown in FIG.

In FIG. 2, a break address is previously set in the execution event detector 112 by the instruction execution event setting means 111 (step A1), and the address event setting means 1 is set in the address event detector 116.
15 sets a break task identifier (step A2).

The address event control state changing means 119 compares the execution task identifier written in the address of the execution task identifier storage area 123 with the break task identifier when the operation of the target system 120 is resumed (step A3). When the execution task identifier and the break task identifier match, the address event control signal is set to active. At this time, the output signal of the address event detector output signal control means 118 is set to active (step A4).

On the other hand, if the execution task identifier and the break task identifier do not match in the process of step A3, the address event control state changing means 119 sets the address event control signal to inactive. At this time, the output signal of the address event detector output signal control means 118 is set to inactive (step A5).

After the processing of steps A1 to A5 is completed, when the target system 120 is operated, the task debugging device 110 executes the processing according to the procedure shown in FIG.

In FIG. 3, the target system 120
CPU 121 of the task debugging device 110
When the process is started according to an instruction from the execution control unit 114 (step B1), first, the instruction execution event detector 11
2 determines whether or not the address event control signal is active (step B2), and if the address event control signal is active, determines whether the execution address matches the break address (step B2). B
5). If the execution address matches the break address, the process proceeds to the break generation circuit 113 to break the target system 120 at the corresponding address (step B6). If the execution address does not match the break address, the process returns to step B2.

When the address event control signal is inactive in the processing of step B2, the address event detector 116 matches the execution task identifier written at the address of the execution task identifier storage area 123 with the break task identifier. Is determined (step B
3) If the execution task identifier and the break task identifier match, the address event control signal is set to active, and the process proceeds to step B5.

If the execution task identifier and the break task identification do not match in the process of step B3, the address event control signal is set to inactive (step B4), and the process returns to step B3.

Next, a specific operation of the task debugging device will be described with reference to FIG.

In the following, a case will be described in which the target system 120 is once broken to execute debugging, and operation is resumed from that state.

First, when the execution task at the time of resuming the operation is a break target, the address event control state changing means 119 sets the address event control signal to active. At this time, the instruction execution event detector 112
Determines whether the execution address matches the break address (step B5). If the execution address matches the break address, the break generation circuit 1
13, the CPU 121 of the target system 120
Break the processing of.

When the task switching occurs after the operation is resumed (when the task is switched to a task other than the break task), the address event control signal is set to inactive by the address event detector 116. At this time, the address event detector 116 operates until the execution task identifier written at the address of the execution task identifier storage area 123 and the break task identifier match.
Steps B3 and B4 are repeated. If the execution task identifier and the break task identifier match,
Proceeding to step B5, the instruction execution event detector 112 determines whether the execution address matches the break address as described above. If the execution address matches the break address, a break occurs. The CP of the target system 120 by the circuit 113
Break the process of U121. If the execution task at the time of resuming the operation is not a break target, the address event control state changing means 119 sets the address event control signal to inactive. At this time, the task debugging device shifts to the process of step B3. Subsequent processing is the same as in the case where the task switching described above has occurred, and a description thereof will be omitted.

Since the instruction execution event detector 112 and the address event detector 116 operate asynchronously, it is determined whether or not the execution task identifier and the break task identifier match, and the execution address and the break address are determined. The determination as to whether or not is the same may be performed first.

As described above, by controlling the output signal of the address event detector output signal control means 118 by the address event control signal, the break generation circuit 113 can break the processing except for the desired task and address. Therefore, a break function without overhead (no processing delay) can be realized.

The CPU of the target system 120
Since the address trap function of the memory 121 is not used, a processing program therefor is stored in the program storage unit 1.
22, need not be stored in the target system 120.
Need not be used for the program storage unit 122.

The processing of each component constituting the task debugging device 110 may be performed by a computer having a CPU. In that case, the computer has a recording medium (not shown) on which a program for executing a break process is recorded, and the above-described processing procedure is executed according to the program recorded on the recording medium. Here, the recording medium may be a magnetic disk, a semiconductor memory, or another recording medium.

[0047]

Since the present invention is configured as described above, the following effects can be obtained.

Since the task debugging device does not interrupt the processing of the target system except for the desired task and address, a break function without overhead (no processing delay) can be realized.

Further, since the address trap function of the CPU of the target system is not used, there is no need to store a processing program for that purpose in the program storage unit, and it is not necessary to use the program storage unit of the target system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a task debugging device according to the present invention.

FIG. 2 is a flowchart showing a processing procedure of a break task identifier and a break address which are set in advance for the task debugging device shown in FIG. 1;

FIG. 3 is a flowchart showing an operation procedure of the task debugging device shown in FIG. 1;

FIG. 4 is a flowchart showing a procedure of a conventional task debugging technique to be performed by the target system itself.

[Explanation of symbols]

 Reference Signs List 110 task debugger 111 instruction execution event setting means 112 instruction execution event detector 113 break generation circuit 114 CPU execution control means 115 address event setting means 116 address event detector 118 address event detector output signal control means 119 address event control state change Means 120 Target system 121 CPU 122 Program storage unit 123 Execution task identifier storage area

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/28-11/36 G06F 9/46 330-340

Claims (3)

(57) [Claims] 1. A task debugging device having a break function for temporarily suspending processing of a target system to be debugged at a desired task and address, and used for assisting debugging of the task. A break address, which is an address to be interrupted, is set. When the break address matches the execution address, which is the address currently being executed in the target system, an output signal is set to an active state, and the execution address and the break address are set. An instruction execution event detector for setting an output signal to an inactive state when the break address does not match; and setting an output signal to an active state when an input address event control signal is in an active state; Set output signal to inactive state when event control signal is inactive Address event detector output signal control means, and in advance, a break task identifier which is an identifier of a task to be interrupted is set, and when the target system recognizes a task to be executed, When the execution task identifier, which is an identifier, and the break task identifier match, the address event control signal is set to an active state, and when the execution task identifier does not match the break task identifier, the address event control signal is set to the active state. and sets the non-active state, the
When the operation of the target system resumes,
Execution task identification, which is the identifier of the task executed by the system
If the child and the break task identifier match,
The address event control signal is set to the active state,
The line task identifier matches the break task identifier
If not, the address event control signal is inactive.
An address event control state changing means for setting the output signal of the instruction event execution detector to an active state, and an output of the address event detector output signal control means. And a break generation circuit for interrupting processing of the target system at a corresponding task and address when a signal is set to an active state. 2. A task debugging method for supporting debugging of a task, comprising: a break process for temporarily suspending processing of a target system to be debugged at a desired task and address. The output signal is set to an active state when the execution address which is the address currently being executed and the break address which is a preset address to be interrupted are set, and when the execution address does not match the break address. A command execution event detection process for setting an output signal to an inactive state; and setting an output signal to an active state when an input address event control signal is in an active state, wherein the address event control signal is inactive. When the output signal is set to the inactive state, the address event detector output signal Processing, when the target system recognizes the task to be executed, the execution task identifier which is the identifier of the task currently being executed by the target system and the break task identifier which is a preset identifier of the task to be interrupted, If they match, the address event control signal is set to an active state. If the execution task identifier and the break task identifier do not match, the address event control signal is set to an inactive state and the target is set to the inactive state.
When the target system resumes operation, the target system
An execution task identifier which is an identifier of a task to be executed;
If the break task identifier matches the address
Setting the event control signal to the active state,
When the identifier does not match the break task identifier
Sets the address event control signal to an inactive state
An address event detection process including an address event control state change process, and an active signal is output by the instruction execution event detection process, and an active signal is output by the address event detector output signal control process. And a break signal generating process for generating a signal for interrupting the processing of the target system at a corresponding task and address. 3. A program which is provided with a break function for temporarily suspending processing of a target system to be debugged at a desired task and address, and which is executed by a task debugging device used to support debugging of the task. A recording medium on which the output signal is set to an active state when an execution address that is an address currently being executed in the target system matches a break address that is a preset address to be interrupted; An instruction execution event detection process of setting an output signal to an inactive state when the execution address does not match the break address; and setting the output signal to an active state when the input address event control signal is in an active state. Output signal when the address event control signal is inactive. Address event detector output signal control processing for setting to an active state; and when the target system recognizes a task to be executed, an execution task identifier which is an identifier of a task currently being executed by the target system and a preset interruption. If the break task identifier, which is the identifier of the task to be performed, matches, the address event control signal is set to the active state. If the execution task identifier does not match the break task identifier, the address event control signal is set to non-active. and it sets the active state, the target
When the target system resumes operation, the target system
An execution task identifier which is an identifier of a task to be executed;
If the break task identifier matches the address
Setting the event control signal to the active state,
When the identifier does not match the break task identifier
Sets the address event control signal to an inactive state
An address event detection process including an address event control state change process, an active signal is output by the instruction execution event detection process, and an active signal is output by the address event detector output signal control process. And a break signal generating process for generating a signal for interrupting the processing of the target system at a corresponding task and address, and a program for causing the task debugging device to execute the process.