JP2653412B2 - How to set breakpoints - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for setting a breakpoint for stopping program execution halfway in a program debugging support tool such as a so-called debugger.

[0002]

2. Description of the Related Art Conventionally, many debugging support systems have a breakpoint function for interrupting the execution of a program at a predetermined instruction. In the debugging process of a program, this kind of breakpoint function is useful and is incorporated in many debugging support systems. This function is to halt the execution of a program to be debugged each time with an arbitrary instruction designated in advance. When using this function, the user designates an instruction whose execution is to be stopped in advance, and then starts the debug target program. Thus, the debug target program stops executing at the designated instruction. At that time, the operator can check or change the values of the registers and memories at the time of the stop, if necessary. Thereafter, the program execution can be resumed from the point at which the program was stopped (for example, see "Information Science Dictionary," Iwanami Shoten, First Edition, 1990, p.655, "Breakpoint", etc.). There are the following methods (1) to (3) for realizing the breakpoint function.

(1) Replace a designated instruction with a trap instruction. That is, when a trap instruction is detected, a trap is generated, control is passed to the debug support program via the trap processing routine, and the user is notified of the fact. When execution restart is instructed, the execution of the replaced original instruction is simulated, and then control is returned to the original (for example, Iizuka, Tanaka "Software Oriented Architecture")
Ohmsha, 1st Edition, 1985, p.212, "Indexing for Instruction Execution"). This method has a feature that a plurality of breakpoints can be set in a program.

(2) A breakpoint register is provided in hardware. Breakpoint register (BPR)
Is a register that holds the address of the instruction whose execution is to be stopped. When the instruction specified by this register is detected, a trap is generated, control is passed to the debug support program via the trap processing routine, and the user is notified of the fact. When execution resume is instructed, the control is returned (for example, see “32-bit microprocessor”, Nikkei McGraw-Hill, p. 178). This method
It has the following features (a) and (b). (A) There is no need to change the program to be debugged. (B) There is no need to simulate instruction execution.

(3) A flag for controlling a breakpoint is prepared for each instruction. When an instruction in which this flag is set is detected, a trap is generated, control is passed to the debug support program via the trap processing, and the user is notified of that. When execution restart is instructed, control is returned to the original (for example, Iizuka, Tanaka "Software Oriented Architecture" Ohmsha First Edition, 1985, p.212
See “Indexing Instruction Execution”). This method has the following features (a) and (b). (A) A plurality of breakpoints can be set. (B) There is no need to simulate instruction execution.

[0006]

However, the above-mentioned prior arts (1) to (3) have the following problems. That is, the technology (1) includes the following (a) and (b)
There was such a problem. (A) The original program needs to be rewritten to set a breakpoint. Therefore, when the program is written in a read-only memory or the like and the program cannot be rewritten, a breakpoint cannot be set. (B) In order to resume the execution of the program from the breakpoint, it is necessary to simulate the execution of the rewritten original instruction. Therefore, the following (A), (B)
There was a problem.

(A) In the case of an instruction using the program counter relative addressing mode or the like, since the value of the program counter is different from the execution state of the original program, many instructions are required to correctly simulate. (A) If the state of the processor such as the privileged mode is different from the execution state of the original program, it cannot be detected in the original program state even if execution of the instruction is not permitted.

[0008] The method (2) has the following problem. Since the number of breakpoint registers that can be prepared by hardware is limited, it is not possible to set more breakpoints. For example, when the number of breakpoint registers is four, only four breakpoints can be monitored at the same time. (3) has the following problems (a) and (b). (A) It is necessary to rewrite the flag of the instruction in the original program to set a breakpoint. Therefore,
(1) As in (a), when a program is written in a read-only memory or the like and the program cannot be rewritten, a breakpoint cannot be set. (B) It cannot be applied to processors other than a special processor having a flag for controlling a breakpoint in an instruction.

The present invention has been made in view of the above points, and solves the problems of the conventional methods (1) to (3) and has the following features (A) to (C). It is an object of the present invention to provide a breakpoint setting method in which a debug support system can realize a breakpoint of instruction execution while keeping the same. (A) Any number of breakpoints can be set. (B) There is no need to rewrite the debug target program. (C) There is no need to simulate instruction execution.

In the method of setting a breakpoint according to the present invention, in a program including a plurality of instructions, a plurality of breakpoints for respectively stopping the execution of the program at each designated instruction are prepared, and the address of the instruction being executed is equal to or more than the breakpoint. And the address of the breakpoint closest to that address is held in a register, and when an instruction present at the address held in the register is executed, an interrupt is requested by a breakpoint detection mechanism for stopping program execution, If a branch instruction branching to a discontinuous address appears during the sequential execution of instructions at consecutive addresses in the program, after execution of the branch instruction, at or above the address of the branch destination, and To reset the address of the breakpoint closest to that address to the register Interrupts requests to branch trace mechanism, the branch trace mechanism branch destination is characterized in executing the interrupt said branch trace mechanism only when there outside address range set in advance.

When the execution of a program is started to debug the program, an interrupt is executed between an execution start address and a breakpoint address that is equal to or more than the execution start address and closest to the execution start address. It is characterized in that an address range for prohibition is set.

When the program execution is resumed after the execution of the program is interrupted at the break point, when the execution of the program is resumed, an execution resuming address and a break point which is equal to or greater than the execution resuming address and closest to the execution resuming address are used. It is characterized in that an address range for interrupt inhibition is set between addresses.

[0013]

In the breakpoint setting method of the present invention, the breakpoint setting routine predicts a breakpoint to be detected next among a plurality of designated breakpoints, and stores the address in the breakpoint register. Set. That is, the next breakpoint that will appear according to the execution of the program is predicted, and the breakpoint register is replaced accordingly. Thus, one breakpoint register supports a plurality of breakpoints. The breakpoint is predicted and the breakpoint register is set at the timing immediately before the execution of the debug target program starts.
At the time of resuming program execution and at the time of branching after detecting a breakpoint.

The breakpoint is predicted by utilizing the following properties. That is, unless a branch occurs, the address of the instruction to be executed increases sequentially.
Therefore, the address of the next breakpoint has the address closest to that address among the breakpoint addresses higher than the current instruction execution address. On the other hand, when the same prediction is performed when a branch occurs, there is a waste in setting the same breakpoint as the breakpoint already set in the register again. Therefore, only when the branch destination is outside a certain range, the register is reset, thereby avoiding waste.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram for explaining the operation of a breakpoint setting method according to the present invention. An apparatus for realizing the method of the present invention includes a breakpoint register 1, a breakpoint detection mechanism 2, a branch tracing mechanism 3, a comparator 4, an interrupt processing routine T, and a breakpoint setting routine B. You. One breakpoint register 1 is provided. Note that at least one breakpoint register 1 is provided, and there may be two or more breakpoint registers.

The breakpoint detection mechanism 2 is a mechanism for requesting an interrupt for stopping program execution when an instruction specified by the breakpoint register 1 is detected or executed. Branch trace mechanism 3
Is a mechanism for requesting an interrupt for register reset when a branch occurs. The comparator 4 is a mechanism for limiting the interrupt operation of the branch trace mechanism within a certain address range. The details will be described later. The interrupt processing routine T is a routine for debugging the target program P by the debug support program D.

On the other hand, the target program P is a program to be debugged, is composed of a plurality of instructions, starts execution from an execution start address, and has breakpoints BP1, BP2, and BP3 set in advance. Breakpoints BP1, BP2, and BP3 indicate addresses at which debugging is stopped halfway. These addresses are stored in a predetermined storage area (not shown) of the debug support program D.

The debug support program D is a set of various routines for debugging. This includes a breakpoint setting routine B. The breakpoint setting routine B is a routine for setting the addresses of the breakpoints BP1, BP2, and BP3 on the target program P in the breakpoint register 1. The breakpoint setting routine B includes a subroutine executed in the debug support program D. Breakpoints BP1, BP2, BP3 described above
Is specified by a user who is debugging the target program P using the debug support program D. All specified breakpoints BP1, BP2, BP3
Is stored in a storage area used by the debug support program D. For example, in this embodiment, three breakpoints BP are included in the target program.
1, BP2, and BP3 are set, and the addresses are assumed to increase in this order.

Next, the operation of the above-described device will be described. First, the user inputs the breakpoints BP1, BP2, BP
After setting 3, the debug support program D is instructed to execute the target program P. Then, the first breakpoint BP1 is set in the breakpoint register 1 by the procedure described later, the interrupt operation of the breakpoint detection mechanism 2 and the branch trace mechanism 3 is enabled, and the interrupt processing routine T is executed from the debug support program D. The control is transferred to the target program P via this.

When a breakpoint BP1, BP2 or BP3 specified by the breakpoint register 1 is detected, control is passed to the debug support program D via the interrupt processing routine T. Here, the execution of the target program P is interrupted, and a predetermined debugging process such as checking the value of the memory is executed. Thereafter, when the user instructs the debug support program D to resume the execution of the target program P, the break point setting routine B is executed to set a new break point in the break point register 1 and then the interrupt processing routine T
The control is passed to the target program P via. When a branch is detected by the branch tracing mechanism 3, control is passed to the breakpoint setting routine B via the interrupt processing routine T, the breakpoint setting is switched, and the target is set via the interrupt processing routine T. Control is returned to program P.

When a breakpoint specified by the breakpoint register 1 is detected by the breakpoint detection mechanism 2, control is transferred to the interrupt processing routine T before executing the instruction. Therefore, after that, the execution is restarted from the breakpoint instruction. When a branch is detected by the branch tracing mechanism 3, control is transferred to the interrupt processing routine T after the execution of the instruction that caused the branch is completed. Therefore, after the breakpoint register 1 is reset, the program continues from the instruction at the branch destination. If the instruction specified by breakpoint register 1 causes a branch, the breakpoint has priority. The continuation address when returning from the interrupt processing routine T is stored in a special register or stack and can be known from the debug support program D.

FIG. 2 is an explanatory diagram of the interrupt inhibiting operation. In the method of the present invention, when a branch instruction appears, there are two cases, a state as shown in FIG. 1 and a state as shown in FIG. That is, in the case shown in FIG. 1, the branch instruction is passed through one breakpoint BP2 to the branch destination L of a larger address. In this case, since the breakpoint BP2 has already been set in the breakpoint register 1, an operation of newly setting the breakpoint BP3 after branching is required. This is because the program is executed toward the higher address.

On the other hand, as shown in FIG. 2, consider a case where a branch is made to a branch destination L smaller than the branch instruction. In this case, the breakpoint BP2 has already been set in the breakpoint register 1. Therefore, there is no need to reset the contents of the breakpoint register 1. Further, if such a resetting operation is repeated, useless processing time is wasted. In a program of this type having a lot of repetitive processing, such waste is not negligible as a whole. The apparatus of the present invention is configured so that such waste can be removed.

FIG. 3 is an explanatory diagram of the address range. Useless resetting of the breakpoint register 1 as described above occurs when the branch destination by the branch instruction is within a certain address range. Therefore, in order to recognize the address range, the comparator 4 described in FIG. 1 is provided. The comparator 4 includes two registers LCAR4-1 and UCAR4-2 as shown in FIG. In this example, the program execution has already been stopped once at the breakpoint BP1, and the next address (B
The execution of the program has been resumed from the instruction at (P1 + 1). At that time, the address of the breakpoint closest to that address, that is, the address of the breakpoint BP2 is set in the breakpoint register 1.

Therefore, the execution resume address, that is, the address next to the address of the breakpoint BP1 is set in the register LCAR4-1, and the address of the breakpoint BP2 is set in the register UCAR4-2. Then, the branch destination L of the branch instruction is the two registers LCAR
It is determined whether the address is outside the address range indicated by 4-1 and UCAR4-2. As a result, the branch trace interrupt is prohibited when the distance is within this range.

FIG. 4 is a block diagram showing a configuration of a comparator for making the above-mentioned comparison judgment. In this circuit,
The register LCAR4-1 described above and the register UC
An AR 4-2 and two comparators 4-3 and 4-4, an OR gate 4-5 for calculating a logical sum of these outputs, and an AND gate 4-6 are provided.

The output of the register LCAR4-1 is input to the comparator 4-3 together with the address TA of the next instruction to be executed, and the size is compared. Also, register UCAR
The output of 4-2 is input to a comparator 4-4 together with the address TA of the next instruction to be executed, and a comparison is made as to which is larger. The outputs of the comparators 4-3 and 4-4 are connected to an OR gate 4-5.
And the logical sum is obtained, the address of the next instruction to be executed is changed to the register LCAR4-1 and the register UCAR4-
Only when the address is outside the address range indicated by 2, the output of the OR gate 4-5 becomes "1".

On the other hand, the AND gate 4-6 has, in addition to the output of the OR gate 4-5, a signal BR indicating that a branch has occurred and a flag B indicating whether or not to perform branch tracing.
T is input. Therefore, the output of the AND gate 4-6 is when the branch destination by the branch instruction is out of the address range set by the comparator, and the branch has occurred.
Also, it becomes "1" only when the flag indicating that branch tracing is performed is "1". When the output of the AND gate 4-6 becomes "1", the breakpoint register 1
Is interrupted to set a new breakpoint.

The above example is an operation example in which the execution of a program is resumed after the execution of the program is temporarily suspended at a breakpoint after the start of the program, but the execution of the program is started for the first time for debugging the program. In this case, the register LCAR4-1 contains:
The execution start address is set, and the register UCAR4-
In 2, the address of the first breakpoint BP <b> 1 set in the breakpoint register 1 may be set.

Hereinafter, the processing procedure of the present invention will be described in order using a flowchart. FIG. 5 is an operation flowchart at the start of program execution according to the present invention. First, in step S1, it is determined whether the number of breakpoints is zero. This is because if the number of breakpoints is 0, it is not necessary to adopt the method of the present invention. If there is one or more breakpoints, the process proceeds to step S2, where the breakpoint detection mechanism 2 and the branch trace mechanism 3
Enable the operation of. Then, in step S3, a break point that is equal to or higher than the execution start address and that is closest thereto is searched for. In the embodiment of FIG. 1, this breakpoint is breakpoint BP1. Therefore, in step S4, the addresses are set for the breakpoint register 1 and the register UCAR4-2. Further, an execution start address is set in the register LCAR4-1. Thus, the preparation for starting the execution of the program is completed.

When it is determined in step S1 that the number of breakpoints is 0, the interrupt by the breakpoint register is invalidated, the branch trace is invalidated, and the debugging process is started (step S5). In this case, the method of the present invention is not performed.

FIG. 6 is a flowchart showing the operation when the program is interrupted and restarted. When the processing described in FIG. 5 is executed, FIG.
For example, the break point BP
At 1, the execution of the program is stopped. In that case, the program is restarted by the procedure shown in FIG. First, in step S1, an execution restart address is obtained. This is an operation for obtaining an address next to the address of the breakpoint BP1. In the next step S2, a breakpoint larger than the execution resuming address and closest thereto is searched for.

Next, in step S3, it is determined whether there is a corresponding break point. If there is a corresponding break point, the process proceeds to step S4, and the address is set in the break point register 1. Further, in step S5, the same value as that of the breakpoint register 1 is set in the register UCAR4-2. Then, the address of the instruction next to the execution restart address is set in the register LCAR4-1. As a result, preparation for restarting the program is completed, and the program is executed from the execution restart address. If it is determined in step S3 that there is no corresponding breakpoint, the process proceeds to step S6, where a value larger than the maximum value of the instruction address is set in the breakpoint register 1, and the program is executed to the end. .

FIG. 7 is a flowchart showing the operation of generating a branch trace interrupt. During the operation of the above program,
When a branch instruction appears, whether or not an interrupt of the branch tracing mechanism occurs is determined by the judgment of the comparator 4 described above. When an interruption of the branch tracing mechanism occurs, a process as shown in FIG. 7 is executed.

First, in step S1, an execution restart address is obtained. Further, a breakpoint that is equal to or higher than the execution restart address and that is closest to the breakpoint is searched (step S2).
Then, in step S3, it is determined whether there is a corresponding breakpoint. If there is a corresponding breakpoint, the process proceeds to step S4, and the address is set in the breakpoint register 1. Thereafter, in step S5, the same value as that of the breakpoint register 1 is set in the register UCAR4-2. Next, in step S6, a break point having a smaller address than the address set in the break point register 1 and having the largest address is searched for. In step S7,
Determine if there is a corresponding breakpoint.
If there is a corresponding break point, step S
8 and the next address of the address is stored in the register LC.
AR4-1 is set.

On the other hand, if it is determined in step S3 that there is no corresponding breakpoint, a value larger than the maximum value of the instruction address is set in the breakpoint register 1
Set to. If it is determined in step S7 that there is no corresponding breakpoint, the process proceeds to step S10, and the execution start address is set in LCAR4-1. That is, the register is reset only when the address range of the branch destination is before the execution start address.

By the above processing, the execution of the program can always be stopped at the address of the breakpoint that is equal to or higher than the address of the instruction being executed and the address of the breakpoint that is already set in the breakpoint register. When a branch instruction that does not require changing the address of a breakpoint is executed, debugging can be performed efficiently while prohibiting interruption of the branch trace mechanism. This also allows the contents of the breakpoint register to be rewritten each time, eliminating the need to provide many breakpoint registers. The present invention is not limited to the above embodiments. Since the register for determining the upper limit of the address range in the comparator is the same as the content of the breakpoint register, both registers may be shared. Further, the configuration of the comparator may be implemented by software instead of the hardware described above.

[0038]

The breakpoint setting method of the present invention described above has the following effects since a plurality of breakpoint addresses are sequentially set in at least one register. (A) Since it is not necessary to rewrite the program to be debugged, a breakpoint can be set for a program on a read-only memory. (B) Since it is not necessary to simulate the instruction at the breakpoint, a routine and a data area for simulating the instruction can be eliminated. (C) Any number of breakpoints can be set. (D) The execution state of the program can be made the same as during normal operation. Therefore, there is no need to provide a mechanism such as a special flag in the instruction itself. (E) Since the interrupt of the branch tracing mechanism is executed only when the branch destination instruction by the branch instruction is out of a certain address range, there is no waste in setting a breakpoint.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the operation of a breakpoint setting method according to the present invention.

FIG. 2 is an explanatory diagram of an interrupt disabling operation.

FIG. 3 is an explanatory diagram of an address range.

FIG. 4 is a configuration block diagram of a comparator.

FIG. 5 is an operation flowchart at the start of program execution.

FIG. 6 is an operation flowchart at the time of program interruption / resumption.

FIG. 7 is a flowchart of a branch trace interrupt generation operation.

[Explanation of symbols]

 1 Breakpoint register 2 Breakpoint detection mechanism 3 Branch tracing mechanism 4 Comparator P Target program T Interrupt processing routine D Debugging support program BP1, BP2, BP3 Breakpoint

Claims (3)

(57) [Claims] In a program including a plurality of instructions, a plurality of breakpoints for stopping execution of the program at each designated instruction are prepared, and a plurality of breakpoints are provided at an address equal to or more than the address of the instruction being executed. Holds the address of the nearest breakpoint in the register, and when executing the instruction at the address held in the register, requests an interrupt to the breakpoint detection mechanism to stop the execution of the program. If a branch instruction that branches to a discontinuous address appears during the sequential execution of existing instructions, after the execution of the branch instruction, a breakpoint that is equal to or greater than the address of the branch destination and closest to that address is executed. Requesting an interrupt from the branch trace mechanism to reset the address in said register; Serial branch trace mechanism branch destination, the breakpoint setting method characterized by executing an interrupt of the branch trace mechanism only when there outside address range set in advance. 2. When starting execution of a program for debugging the program, interrupts are prohibited between an execution start address and a breakpoint address that is equal to or higher than the execution start address and closest to the execution start address. 2. The method for setting a breakpoint according to claim 1, wherein an address range for setting is set. 3. When the execution of the program is resumed after the execution of the program is interrupted at the break point, the execution start address and the break point which is equal to or more than the execution restart address and closest to the execution restart address are set. 2. The method according to claim 1, wherein an address range for disabling interrupts is set between addresses.