JPH0315949A - Debugging system - Google Patents

Abstract

PURPOSE:To attain debug in which that the common resource of a system does not change is set as a premise by giving a sole bus use right to a processor where a debug exception occurs. CONSTITUTION:A circuit 42 storing a processor in the middle of obtaining a bus and a circuit 43 detecting the reading of a vector for debug exception are used. A bus mediation circuit 4 giving the sole bus use right to the processor where the debug exception occurs is constituted, and programs to be debugged existing on the system are all stopped. Namely, the execution of the program to be debugged is interrupted in the processor where the debug exception occurs, and the execution of a debug program is started instead. At that time, all the programs to be debugged are stopped. Thus, debug in a state where the common resource is freezed is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a debugging method in a multiprocessor system in which a plurality of processors access shared resources via a common bus.

[Conventional technology]

The method of halting program execution under arbitrary conditions and referencing resources is an effective method for programmatic debugging. In particular, a common method is to embed a breakpoint instruction in a program to be debugged, generate a debugging exception when the processor executes the instruction, and transfer control of the program to the debugging program.

[Problem to be solved by the invention]

The debugging methods described above are effective for debugging programs on a single processor, but when used on multiple processors, only one processor in the system may stop program execution. Since the program continues to be executed on other processors, the resources of the system are changed during debugging, making debugging difficult.

[Means to solve the problem]

In a multiprocessor system where multiple processors access shared resources via a common bus, by using a circuit that remembers which processor is acquiring the bus and a circuit that detects vector reads for debug exceptions, it is possible to The bus arbitration circuit that gives exclusive bus usage rights can be ignored, and all debug target programs existing on the system can be stopped all at once. In the processor where the debug exception occurred, execution of the debug target program is interrupted and execution of the debug program is started instead, but at this point all debug target programs have stopped, so the shared resources are frozen. It is possible to debug in the current state. In order to restart the debug target program after debugging is complete, the processor running the debug program issues an instruction to the bus arbitration circuit to release the bus from exclusive use, and then the debug program Returns control to the suspension point of the debug target program where the debug exception occurred. The above series of procedures enables debugging without changing the resources of the system.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. The processors 1 to 3 execute programs by accessing the shared memory 6 and the input/output device 7 via a common bus router. When processor E~3 accesses the common bus 5, it first sends a bus acquisition request signal to the bus arbitration circuit 4, and receives a bus use permission signal from the bus arbitration circuit 4, thereby making it possible to use the common bus. . During normal program execution, the bus right determining circuit 41 determines the bus right to use the bus for all processors 1 to 3, either equally or with priority.

Next, using the flowchart of FIG. 2, it will be explained how the circuit of FIG. 1 operates when a debug exception occurs. Program steps (hereinafter referred to as PS) 100 to 10
2, PS200-202 and PS300-PS302 are programs to be debugged that run on the processors 1-3, respectively, and PS303-308 are debug programs that start execution when a debug exception occurs in the processor 3.

Assume that a debug exception occurs in P S 3'0 1 of the debug target program being executed by processor 3. In this case, in order to acquire the start address of the debug exception handling routine, the processor 3 acquires the common bus 5 and then reads the debug exception vector existing on the shared memory 6. Since the address and status necessary for reading this debug exception vector are output to the debug exception vector read detection circuit 43, the debug exception vector read detection circuit 43 detects when a debug exception occurs in any processor on the system using the signal on this common bus. Detect what happened.

On the other hand, each time the bus usage right determination circuit 41 determines a processor to use the bus, it writes the processor number to the bus acquisition processor memory circuit 42, so the debug exception vector read detection circuit 43 detects the debug exception vector read. When detected, the contents of processor storage circuit 42 indicate processor 3 while acquiring the bus. The bus right determining circuit 41 learns that a debug exception has occurred in the processor 3 from the output of the debug exception vector read detection circuit 43 and the output of the bus acquisition processor memory circuit 42. After the occurrence of this debug exception, the bus right determining circuit 41 grants permission to use the bus only in response to a bus acquisition request from the processor 3.

As a result, processors 1 and 2 each have PSIOI
, a bus acquisition wait occurs in the PS 201, and the execution of the debug target program on the processor 1.2 is stopped. In the processor 3, control is transferred to the debug program due to a debug exception, the registers of the debug target program are saved in the PS 304, and the debug operation is performed in the PS 305, but in this state, the processor 3 is not executing the program, It becomes possible to debug without changing the resources of the system.

After the debug operation is completed, the PS 306 issues a command to the bus arbitration circuit 4 to release the exclusive use of the bus. An exclusive bus release command detection circuit 44 existing in the bus arbitration circuit detects the command issued from the PS 306 and requests the bus right determination circuit 41 to perform bus arbitration operation in the normal state.

After this, the bus right determining circuit 41 also grants permission to the processor 1 and the processor 2 to use the bus, so the debug target program whose operation has been stopped at the PSIOI and the PS 201 resumes operation. In addition, the processor 3 on which the debugging program was being executed
Then, PS307 restores the registers of the program to be debugged, and PS308 executes a return instruction to resume program execution starting from PS301.

The above series of procedures enables debugging without changing the resources of the system. In the above embodiment, the target is a debug exception that occurs from inside the processor, but a similar method can be applied to a debug exception that occurs from outside the processor.

〔Effect of the invention〕

As described above, the present invention allows programs to be debugged in the entire system to be stopped immediately after the debug exception occurs by giving exclusive bus usage rights to the processor in which the debug exception occurs. This enables debugging on the assumption that the system's shared resources do not change, and has the effect of efficiently debugging programs on multiprocessors, which is difficult to do.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a flow chart showing the operation. 1 to 3... Processor, 4... Bus arbitration circuit, 4l
. . . Bus usage right determination circuit, 42 . . . Bus acquisition processor storage circuit, 43 . . . Debug exception vector read detection circuit, 44 . common bus, 6... shared memory, 7.
...I/O device.

Claims (1)

[Claims] A multiprocessor system in which a plurality of processors access a shared resource via a common bus, the system including a bus acquisition processor storage circuit and a debug exception vector read detection circuit, the bus acquisition processor storage circuit and the debug exception vector read detection circuit. Debugging characterized by having a bus arbitration circuit that grants exclusive bus usage rights to a processor in which a debugging exception has occurred based on the output of the vector read detection circuit, and releases the exclusive use of the bus based on an instruction from the processor. method.