JPS59100966A - Shared bus control system of multiprocessor system - Google Patents

Abstract

PURPOSE:To attain a detailed analysis of a system operation or a debug in a lock mode by invalidating forcibly the holding function of bus control right in a mode where the clocks are produced discretely with step operations. CONSTITUTION:Just a clock *PCLK is produced from a clock control circuit 16 when another processor writes a command for generation of a single clock to a register within a processor control circuit 12. Thus a processor system 1 has its state advanced by an amount equivalent to a clock. In this case, a bus control right holding request signal *LOCK is never delivered to a bus control circuit 13 although the bus control right holding request *LOCK RQ is delivered from a processor circuit 11 since the bus control right holding invalid signal *STEP is supplied to a bus control right holding control circuit 14. Therefore other processors can use a shared bus after an instruction for use of the shared bus is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a control method for a shared bus dominance holding function in a multiprocessor system in which a plurality of processor systems are connected to a shared bus.

Prior Art and Problems A multiprocessor system has a function that monopolizes the shared memory when a certain processor system reads the shared memory via the shared bus until the next write is completed. There are things. This function is called the lotus control retention function, and is useful, for example, when executing flag test l- and set consecutively (hasu control relinquishment occurs between test and cent, and other There is no need to worry about the processor's processor system interrupting and rewriting the flag). This lotus control right holding function (lock function) is controlled by the processor itself that uses the function, and other processors cannot intervene.

By the way, the step operation that provides a clock discretely is used, for example, to debug a program, and each time an instruction is executed, another processor checks the status of the processor system in question (to be debugged) and displays it on a display. Once the bus mastership retaining function is enabled by the processor being deactivated, the other processor cannot use the bus and cannot control the state of the processor system until the path mastership retaining function is released. This makes it impossible to monitor the status for each single step.

Purpose of the Invention As mentioned above, the bus mastership retaining function is useful for reading and writing flags like test-and-sent, and eliminating interference from other processor systems during this time, but it is useful for debugging etc. Harmful. Therefore, the present invention attempts to forcibly disable the lotus control right holding function in the latter case.

Composition of the Invention The present invention provides a common node for a multiprocessor system in which a plurality of processor systems share the same bus, and the processor system has a function of retaining bus dominance to monopolize the path over the execution of multiple instructions. In the control method,
In a mode in which the processor system generates clocks discretely and operates in steps, the feature is that the lotus control holding function is forcibly disabled, and this will be explained in detail below with reference to the illustrated embodiment. explain.

Embodiment of the Invention FIG. 1 shows an example of a multiprocessor system, in which a first processor system 1, a second processor system 2,
10 control systems 3 and shared memory 4 or shared lotus 5 are connected to each other. When a plurality of systems 1.2 try to use the shared lotus 5 at the same time, the lotus control priority assigned to each system in advance is generally followed, and the system with a higher rank acquires the lotus. When the execution of the command to use the lotus is completed, the master relinquishes control of the lotus, and issues a new request for control of the lotus when the next command to use the lotus is executed.

However, for example, if a common flag is set in the memory 4 for each processor 1 and 2, and the state of the other processors is known from the state of that flag, it is possible to make a decision by reading the flag. Results may be written to the same flag.

In such a case, if you release Has5 at the stage of reading, there is a possibility that another processor will interrupt and change this flag, and the contents of the flag will be different between the time of reading and the time of writing. There is a risk of erroneously recognizing the status of other processors.

In such a case, use the above-mentioned path ownership retention mechanism to ensure that the path ownership is not relinquished even if a higher-priority lotus request occurs between the time the flag is read and the flag is written. .

However, in the step mode in which the processor clock is applied not continuously but discretely, when another processor checks the state of this processor every clock to check the execution result of the program, the following disadvantages occur. This step mode is used, for example, when debugging a program;
It is necessary to check the execution result every time an instruction is executed.

However, in the conventional method, once the bus mastership holding mechanism is enabled, other processors cannot use the bus, so a check using a shared path cannot be executed until the bus mastership holding mechanism is disabled. In other words, even if step mode is used, information necessary for debugging cannot be obtained.

FIG. 2 is a block diagram showing one embodiment of the present invention. The processor system 1 of this example has a processor circuit 11. Prosensor control circuit 12. Lotus control circuit 13. Hass dominance retention control circuit 14. Clock generation circuit 15. It is composed of a clock control circuit 16 and the like. To enter step mode, use another processor (processor system 2)
or writes a command instructing the step mode to a register in the processor control circuit 12. Output from register (
NORM/*5TEP) is the black/7ri control circuit 16
and the Hass control right holding circuit 14, of which *5 TEP are processor clocks (*PCLK).
and invalidates the lotus control right holding signal (*LOCK). When another processor writes a command to instruct the generation of a single clock to the register in the processor system 11 circuit 12, only one clock * PCLK is generated from the clock control circuit 1G, and the processor system 1 receives one clock. The disease progresses. At this time, the processor circuit 11 issues a request to retain control of the lotus (* LOCK R
Q) is issued, the bus mastership retaining invalid signal (*5TEP) is sent to the bus mastership retaining control circuit 14 as described above.
is input, the lotus control right holding request signal (*LOCK) is not issued to the bus control circuit 13.

Therefore, when the execution of an instruction using the shared bus is completed, the bus is released, allowing other processors to use the shared bus and read necessary information.

FIG. 3 shows details of the lotus dominance holding control circuit 14. 1
41 and 142 are flip-flops for synchronizing asynchronous signals, and a signal (*5TE
P: This is a clock asynchronous to the clock) and a clock for the processor that cannot be stopped (O
PC). 143 is a Nant gate that receives a bus mastership holding request signal (*LOI) from the processor circuit 11;
IJ RQ ) and is disabled in step mode. Figure 4 shows the timing.

opc is a synchronization clock generated by the clock generation circuit 15. Output NORM/ of processor control circuit 12
* When 5TEP goes to L (low) level, the output NORM of flip-flop 142 shown in FIG. 3 goes to L with a delay of two clocks. That is, at the first rise of the clock OPC after NORM/*5TE)' becomes L level, the L level is taken into the flip-flop 141 and its Q output becomes L, and at the next rise of the clock OPC, the Q output becomes L. The L level of the output is taken into the flip-flop 142 and its Q output NORM is set to L. NORM=L indicates step mode, closes the gate 1-143, and invalidates the lotus control holding request LOCK RQ from the processor circuit 11. In other words, *LOCR is set to H (high) level.

This *LOCK is given through the bus control circuit 13 to a lotus priority encoder connected to a suitable location on the shared bus, and if the encoder *LOCK=L, it allows the processor system 1 that issued it to monopolize the shared bus 5. However, if *LOCK=H, it is determined that there is no bus lock, and the lotus use request is processed according to the normal priority order. In this way, if *5TEP is L, that is, in debug mode, the bus mastership holding function is forcibly canceled. This lock release mechanism may be provided in the debugging processor system, but not in the debugging processor system.

Effects of the Invention As described above, according to the present invention, the bus mastership holding function can be disabled during step operation, so the operation of the processor system can be analyzed in detail, and there is an advantage that debugging can be performed even when the system is locked. .

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a general multiprocessor system, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a detailed diagram of the lotus dominance holding control circuit according to the present invention. , Figure 4 is a timing diagram. In the figure, ■, 2 is a processor system, 5 is a shared hash, 1
4 is a bus mastership holding control circuit. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi

Claims (1)

[Claims] In a common bus control method for a multiprocessor system in which multiple processor systems share the same bus and the processor system has a function of retaining bus mastery to monopolize the bus over the execution of multiple instructions, the processor system uses a discrete clock. 1. A shared bus control method for a multiprocessor system, characterized in that in a mode in which a step operation occurs in a step mode, the lotus control right holding function is forcibly disabled.