JPH06103110A - Breakpoint setting system - Google Patents

Abstract

PURPOSE:To set may breakpoints without rewriting an instruction at the time of debugging a program. CONSTITUTION:A breakpoint setting routine B predicts the breakpoint to be detected in the next time in plural designated breakpoints, and sets its address to a breakpoint register 1. The address of the next breakpoint has the nearest address to its address in the breakpoint address exceeding the present instruction executing address. When a branch occurs, only in the case a branch destination is outside of a prescribed range, the register 1 is reset and a useless setting operation is avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a breakpoint setting method for stopping the execution of a program in a program debug support tool such as a so-called debugger.

[0002]

2. Description of the Related Art Conventionally, many debug support systems have a breakpoint function for interrupting the execution of a program with a predetermined instruction. This kind of breakpoint function is useful in the debugging process of a program, and is incorporated in many debugging support systems. This function is to stop the execution of a debug target program each time by an arbitrary instruction designated in advance. When using this function, the user specifies the instruction whose execution is to be stopped in advance, and then starts the debug target program. As a result, the debug target program stops execution at the specified instruction. At that time, the operator can inspect or change the value of the register or the memory at the time of the stop, if necessary. After that, it is also possible to restart the execution of the program from the point at which it stopped (for example, see “Information Science Dictionary”, Iwanami Shoten, 1st edition, 1990, p.655, “Breakpoints”). As a method of realizing this breakpoint function, there are the following methods (1) to (3).

(1) A designated instruction is replaced with a trap instruction. That is, when a trap instruction is detected, a trap occurs, control is passed to the debug support program via the trap processing routine, and the user is notified of that fact. When it is instructed to resume execution, it simulates the execution of the original instruction that was replaced, and then returns control (eg, Iizuka, Tanaka "Software Oriented Architecture").
Ohmsha, 1st edition, 1985, p.212, "Indexing for instruction execution"). This method has the feature that multiple breakpoints can be set in the program.

(2) A breakpoint register is provided in hardware. Breakpoint register (BPR)
Is a register that holds the address of the instruction whose execution is to be stopped. When the instruction designated by this register is detected, a trap occurs, control is passed to the debug support program via the trap processing routine, and the user is notified of that fact. When the execution is restarted, the control is returned to the original state (for example, see “32-bit microprocessor” Nikkei McGraw-Hill, p.178). This method
It has the following features (a) and (b). (A) It is not necessary to change the debug target program. (B) It is not necessary to simulate the execution of instructions.

(3) A flag for controlling a breakpoint is prepared for each instruction. When an instruction in which this flag is set is detected, a trap occurs, control is passed to the debug support program via the trap processing, and the user is notified of that fact. When the execution is instructed again, the control is returned to the original state (for example, Iizuka, Tanaka "Software Oriented Architecture" Ohmsha, 1st edition, 1985, p.212).
See "Indexing for instruction execution"). This method has the following characteristics (a) and (b). (A) Multiple breakpoints can be set. (B) It is not necessary to simulate the execution of instructions.

[0006]

However, the above-mentioned conventional techniques (1) to (3) have the following problems. That is, the technology of (1) includes the following (a) and (b)
There was such a problem. (A) It is necessary to rewrite the original program to set a breakpoint. Therefore, if the program is written in a read-only memory or the like and the program cannot be rewritten, the breakpoint cannot be set. (B) In order to restart the execution of the program from the breakpoint, it is necessary to simulate the execution of the rewritten original instruction. Therefore, the following (a), (a)
There was a problem.

(A) Program counter In the case of an instruction using the relative addressing mode or the like, since the value of the program counter is different from the execution state of the original program, many instructions are required for correct simulation. (B) When the processor state such as the privileged mode may be different from the execution state of the original program, it cannot be detected even when the execution of the instruction is not permitted in the original program state.

Further, (2) has the following problems. There is a limit to the number of breakpoint registers that the hardware can provide, so you cannot set more breakpoints. For example, if the number of breakpoint registers is four, only a maximum of four breakpoints can be monitored simultaneously. Then, (3) has the following problems (a) and (b). (A) It is necessary to rewrite the flag of the instruction in the original program to set the breakpoint. Therefore,
(1) Similar to (a), if the program is written in a read-only memory or the like and the program cannot be rewritten, the breakpoint cannot be set. (B) It cannot be applied to a processor other than a special processor in which an instruction has a flag for controlling a breakpoint.

The present invention has been made by paying attention to the above points, solves the problems of the conventional methods (1) to (3), and has the following characteristics (A) to (C). It is an object of the present invention to provide a breakpoint setting method by which a debug support system can realize a breakpoint for instruction execution while keeping the same. (A) An arbitrary number of breakpoints can be set. (B) It is not necessary to rewrite the debug target program. (C) It is not necessary to simulate the execution of instructions.

[0010]

According to the breakpoint setting method of the present invention, in a program consisting of a plurality of instructions, a plurality of breakpoints for stopping the execution of the program at each designated instruction are prepared and executed. A register that holds the address of a breakpoint that is greater than or equal to the address of the inside instruction and an instruction that exists at the address held in that register, and requests an interrupt to stop program execution When a branch instruction that branches to a discontinuous address appears in the middle of sequentially executing instructions existing at consecutive addresses in the program and the breakpoint detection mechanism, after the execution of the branch instruction, the branch destination Above the address,
And a branch trace mechanism for requesting an interrupt for resetting the address of the breakpoint closest to the address in the register, and the branch trace mechanism has a branch destination outside the preset address range. Only in this case, the interrupt of the branch trace mechanism is executed.

In order to debug the program, when the execution of the program is started, an interrupt is prohibited between the execution start address and an address equal to or higher than the execution start address and closest to the execution start address. It is characterized by setting the address range of.

Further, when the execution of the program is resumed after the execution of the program is interrupted at the break point, it is between the execution restart address and an address which is equal to or higher than the execution restart address and which is the closest to the execution restart address. In addition, it is characterized in that an address range for disabling interrupts is set.

[0013]

In the breakpoint setting method of the present invention, first, the breakpoint setting routine predicts a breakpoint to be detected next among a plurality of designated breakpoints, and stores the address in the breakpoint register. Set. That is, it predicts the next breakpoint that will appear as the program executes and swaps the breakpoint registers accordingly. This supports multiple breakpoints with one breakpoint register. The timing of predicting the breakpoint and setting the breakpoint register is just before the execution of the program to be debugged,
It is when program execution is restarted after a breakpoint is detected and when a branch occurs.

Further, the prediction of the breakpoint is performed by utilizing the following properties. That is, as long as no branch occurs, the address of the executed instruction is sequentially increased.
Therefore, the address of the next breakpoint has the address closest to that of the breakpoint addresses above the current instruction execution address. On the other hand, if a similar prediction is made when a branch occurs, there is a waste of resetting the same breakpoint as the breakpoint already set in the register. Therefore, waste is avoided by resetting the register only when the branch destination is outside a certain range.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a diagram for explaining the operation of the breakpoint setting method of the present invention. An apparatus for implementing the system of the present invention comprises a breakpoint register 1, a breakpoint detection mechanism 2, a branch trace mechanism 3, a comparator 4, an interrupt processing routine T, and a breakpoint setting routine B. It One break point register 1 is provided. At least one break point register 1 is provided, and two or more break point registers 1 may be provided.

The breakpoint detection mechanism 2 is a mechanism for requesting an interrupt for stopping program execution when an instruction designated by the breakpoint register 1 is detected or executed. Branch trace mechanism 3
Is a mechanism for requesting an interrupt for register reset when a branch occurs. The comparator 4 is a mechanism for limiting the interrupt operation of the branch trace mechanism within a fixed address range. The details will be described later. The interrupt processing routine T is a routine for debugging the target program P by the debug support program D.

On the other hand, the target program P is a program to be debugged, is composed of a plurality of instructions, starts to be executed from an execution start address, and has preset breakpoints BP1, BP2 and BP3. Breakpoints BP1, BP2, and BP3 indicate addresses at which debugging is stopped halfway. These addresses are stored in a predetermined storage area (not shown) of the debug support program D.

The debug support program D is a set of various routines for debugging. A breakpoint setting routine B is included in this. The break point setting routine B is a routine for setting the addresses of the break points BP1, BP2, and BP3 in the target program P in the break point register 1. The breakpoint setting routine B is composed of a subroutine executed in the debug support program D. Breakpoints BP1, BP2, BP3 described above
Is specified by the user who is debugging the target program P using the debug support program D. All specified breakpoints BP1, BP2, BP3
The address of is stored in the storage area used by the debug support program D. For example, in this embodiment, three break points BP are included in the target program.
It is assumed that 1, BP2, BP3 are set and the addresses are increased in this order.

Next, the operation of the above-mentioned device will be described. First, the user selects break points BP1, BP2, BP
After setting 3, the debug support program D is instructed to execute the target program P. Then, the first breakpoint BP1 is set in the breakpoint register 1 in the procedure described later, the interrupt operation of the breakpoint detection mechanism 2 and the branch trace mechanism 3 is enabled, and the debug support program D executes the interrupt processing routine T. Control is transferred to the target program P via.

When the break point BP1, BP2 or BP3 specified by the break point register 1 is detected, control is passed to the debug support program D via the interrupt processing routine T. Here, the execution of the target program P is interrupted, and a predetermined debugging process such as checking the memory value is executed. After that, when the user instructs the debug support program D to resume execution of the target program P, the breakpoint setting routine B is executed to set a new breakpoint in the breakpoint register 1, and then the interrupt processing routine T
Control is passed to the target program P via. When a branch is detected by the branch trace mechanism 3, control is passed to the breakpoint setting routine B via the interrupt processing routine T, the breakpoint setting is switched, and the target is passed via the interrupt processing routine T. Control is returned to program P.

When the breakpoint detection mechanism 2 detects a breakpoint designated by the breakpoint register 1, control is transferred to the interrupt processing routine T before the instruction is executed. Therefore, after that, the execution is restarted from the breakpoint instruction. When a branch is detected by the branch trace mechanism 3, control is transferred to the interrupt processing routine T after the execution of the instruction causing the branch is completed. Therefore, after the breakpoint register 1 is reset, the program continues from the branch destination instruction. If the instruction specified in Breakpoint Register 1 causes a branch, the breakpoint takes precedence. The continuation address when returning from the interrupt processing routine T is stored in a special register or stack and can be known from the debug support program D.

FIG. 2 is an explanatory diagram of the interrupt prohibition operation. In the method of the present invention, when a branch instruction appears, there are two cases, a state as shown in FIG. 1 and a state as shown in FIG. That is, in the case shown in FIG. 1, one branch point BP2 is passed by the branch instruction to proceed to the branch destination L of a larger address. In this case, since the break point BP2 has already been set in the break point register 1, it is necessary to perform the operation of newly setting the break point BP3 after the branch. This is because the program will be executed in the direction of the larger address.

On the other hand, as shown in FIG. 2, consider the case of branching to a branch destination L smaller than the branch instruction. In this case, the breakpoint BP2 has already been set in the breakpoint register 1. Therefore, it is not necessary to reset the contents of the breakpoint register 1. Further, if such resetting operation is repeated, useless processing time is consumed. In a program of which this type of repetitive processing is frequent, such waste is not negligible as a whole. The apparatus of the present invention is configured to eliminate such waste.

FIG. 3 is an explanatory view of the address range. The useless resetting process of the breakpoint register 1 as described above occurs when the branch destination by the branch instruction is within a certain address range. Therefore, in order to recognize this address range, the comparator 4 described in FIG. 1 is provided. The comparator 4 is composed of two registers LCAR4-1 and UCAR4-2 as shown in FIG. In this example, the program execution has already stopped once at the breakpoint BP1, and the next address (B
The execution of the program is restarted from the instruction in P1 + 1). At that time, the address of the breakpoint closest to the address, that is, the address of the breakpoint BP2 is set in the breakpoint register 1.

Therefore, the execution restart address, that is, the address next to the address of the breakpoint BP1, is set in the register LCAR4-1, and the address of the breakpoint BP2 is set in the register UCAR4-2. The branch destination L of the branch instruction is the two registers LCAR.
4-1 and UCAR4-2 determine whether it is outside the address range. As a result, the branch trace interrupt is prohibited when it is within this range.

FIG. 4 shows a block diagram of the configuration of a comparator for making the above-mentioned comparison judgment. In this circuit,
The register LCAR4-1 and the register UC described above
An AR 4-2 and two comparators 4-3 and 4-4, an OR gate 4-5 that takes the logical sum of these outputs, and an AND gate 4-6 are provided.

The output of the register LCAR4-1 is input to the comparator 4-3 together with the address TA of the instruction to be executed next, and its size is compared. Also, register UCAR
The output of 4-2 is input to the comparator 4-4 together with the address TA of the next instruction to be executed, and which is larger is compared. The outputs of the comparators 4-3 and 4-4 are connected to the OR gate 4-5.
And the logical sum is obtained, the addresses of the instructions to be executed next are stored in the registers LCAR4-1 and UCAR4-.
The output of the OR gate 4-5 becomes "1" only when it is outside the address range indicated by 2.

On the other hand, the AND gate 4-6 has, in addition to the output of the OR gate 4-5, a signal BR indicating that a branch has occurred and a flag B indicating whether or not the branch trace is performed.
T and enter. Therefore, the output of the AND gate 4-6 is when the branch destination by the branch instruction is outside the address range set by the comparator, and a branch has occurred,
Moreover, it becomes "1" only when the flag indicating that the branch trace is performed is "1". When the output of the AND gate 4-6 becomes "1", the break point register 1
An interrupt is generated to set a new breakpoint.

The above example is an operation example in which the execution of the program is resumed after the execution of the program is suspended at the breakpoint after the program is started. However, the execution of the program is started for the first time for debugging the program. In this case, the register LCAR4-1 has
Set the execution start address and register UCAR4-
The address of the first breakpoint BP1 set in the breakpoint register 1 may be set in 2.

The processing procedure of the present invention will be described below in order with reference to the flowcharts. FIG. 5 is an operation flowchart at the start of program execution according to the present invention. First, in step S1, it is determined whether the number of break points is zero. This is because if the number of breakpoints is 0, it is not necessary to adopt the method of the present invention. If there is one or more breakpoints, the process proceeds to step S2, where the breakpoint detection mechanism 2 and the branch trace mechanism 3 are used.
The operation of is enabled. Then, in step S3, a breakpoint that is equal to or higher than the execution start address and is closest to the execution start address is searched. In the example of FIG. 1, this breakpoint is breakpoint BP1. Therefore, in step S4, the address is set to the breakpoint register 1 and the register UCAR4-2. Further, the execution start address is set in the register LCAR4-1. This completes the preparation for starting execution of the program.

When the number of breakpoints is determined to be 0 in step S1, the interrupt by the breakpoint register is disabled, the branch trace is disabled, and the debugging process is started (step S5). In this case, the method of the invention is not carried out.

FIG. 6 shows an operation flowchart when the program is suspended and resumed. When the processing described in FIG. 5 is executed,
For example, the break point BP as described in
At 1, the execution of the program is stopped. In that case, the program is restarted in the procedure as shown in FIG. First, in step S1, the execution restart address is obtained. This is the work of obtaining the address next to the address of the breakpoint BP1. In the next step S2, a breakpoint that is larger than the execution restart address and is closest to the execution restart address is searched for.

Next, in step S3, it is determined whether or not there is a corresponding break point. If there is a corresponding breakpoint, the process proceeds to step S4 and the address is set in the breakpoint register 1. Further, in step S5, the same value as the breakpoint register 1 is set in the register UCAR4-2. Then, the address of the instruction next to the execution restart address is set in the register LCAR4-1. As a result, the preparation for restarting the program is completed, and the program is executed from the execution restart address. If it is determined in step S3 that there is no corresponding breakpoint, the process proceeds to step S6, a value larger than the maximum instruction address is set in the breakpoint register 1, and the program is executed to the end. .

FIG. 7 shows a flow chart of the branch trace interrupt generation operation. During the operation of the above program,
When a branch instruction appears, whether the interrupt of the branch trace mechanism occurs or not is determined by the judgment of the comparator 4 described above. When an interrupt of the branch trace mechanism occurs, the processing shown in FIG. 7 is executed.

First, in step S1, an execution restart address is obtained. Furthermore, a breakpoint that is equal to or higher than the execution restart address and is closest to the address is searched (step S2).
Then, in step S3, it is determined whether or not there is a corresponding breakpoint, and if there is a corresponding breakpoint, the process proceeds to step S4 and the address is set in the breakpoint register 1. Then, in step S5, the same value as that of the breakpoint register 1 is set in the register UCAR4-2. Next, in step S6, a breakpoint having a maximum address smaller than the address set in the breakpoint register 1 is searched for. In step S7,
Determine if there is an applicable breakpoint.
If there is a corresponding breakpoint, step S
8 and the address next to that address is registered in the register LC.
Set to AR4-1.

On the other hand, when it is determined in step S3 that there is no corresponding breakpoint, a value larger than the maximum value of the instruction address is set in the breakpoint register 1
Set to. If it is determined in step S7 that there is no corresponding breakpoint, the process proceeds to step S10 and the execution start address is set in LCAR4-1. That is, as a result, the register is reset only when the branch destination address range is before the execution start address.

With the above processing, the program execution can always be stopped at the address of the instruction being executed or more and at the address of the breakpoint closest to the address, and the program already set in the breakpoint register. When a branch instruction that does not need to change the address of the breakpoint is executed, it is possible to efficiently perform the debugging process while prohibiting the interrupt of the branch trace mechanism. Further, this makes it possible to rewrite the contents of the breakpoint register each time, and it becomes unnecessary to provide a large number of breakpoint registers. The present invention is not limited to the above embodiments. Since the register that determines the upper limit of the address range in the comparator is the same as the content of the breakpoint register, both registers may be used in common. Further, the configuration of the comparator may be software instead of the above hardware.

[0038]

According to the breakpoint setting method of the present invention described above, a plurality of breakpoint addresses are sequentially set in at least one register, so that the following effects are obtained. (A) Since it is not necessary to rewrite the program to be debugged, a breakpoint can be set for the program on the read-only memory. (B) Since it is not necessary to simulate the instruction of the breakpoint, the routine and data area for simulating the instruction can be eliminated. (C) An arbitrary number of breakpoints can be set. (D) The execution state of the program can be the same as during normal operation. Therefore, it is not necessary to provide a mechanism such as a special flag in the instruction itself. (E) Since the interrupt of the branch trace mechanism is executed only when the branch destination instruction by the branch instruction is outside the fixed address range, there is no waste in setting the breakpoint.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a breakpoint setting method operation of the present invention.

FIG. 2 is an explanatory diagram of an interrupt prohibition operation.

FIG. 3 is an explanatory diagram of an address range.

FIG. 4 is a configuration block diagram of a comparator.

FIG. 5 is an operation flowchart at the start of program execution.

FIG. 6 is an operation flowchart when resuming program interruption.

FIG. 7 is a flowchart of a branch trace interrupt generation operation.

[Explanation of symbols]

 1 Breakpoint register 2 Breakpoint detection mechanism 3 Branch trace mechanism 4 Comparator P Target program T Interrupt processing routine D Debug support program BP1, BP2, BP3 Breakpoint

Claims (3)

[Claims] 1. In a program consisting of a plurality of instructions, a plurality of breakpoints for stopping the execution of the program at each designated instruction are prepared, and the breakpoint is equal to or greater than the address of the instruction being executed. A register that holds the address of the nearest breakpoint, a breakpoint detection mechanism that requests an interrupt to stop program execution when the instruction that is stored in that register is executed, and consecutive addresses in the program If a branch instruction that branches to a non-contiguous address appears during the sequential execution of an instruction that exists in, the breakpoint after the execution of the branch instruction is equal to or higher than the branch destination address and is the closest to the address. Tracer that requests an interrupt to reset the address of the register in the register A breakpoint setting method, wherein the branch trace mechanism executes an interrupt of the branch trace mechanism only when a branch destination is outside a preset address range. 2. When the program is started to be executed for debugging the program, an interrupt is prohibited between the execution start address and an address equal to or higher than the execution start address and closest to the execution start address. 2. The breakpoint setting method according to claim 1, wherein the address range is set. 3. When resuming the execution of the program after interrupting the execution of the program at the breakpoint, between the execution resuming address and an address which is equal to or higher than the execution resuming address and which is the closest to the execution resuming address. To
2. The breakpoint setting method according to claim 1, wherein an address range for disabling interrupts is set.