JPH04145544A - Debugging device - Google Patents

Abstract

PURPOSE:To make independent break points settable at every thread so as to improve the efficiency of the debugging work of a debugging device by providing the identifier to the thread being executed at a real machine. CONSTITUTION:A thread identifier to be broken and address are inputted from a keyboard 13 and a break point discrimination circuit 17 is selected on the basis of the thread identifier. After selection, a break point address is set in the circuit 17. When thread switching operations occur during the execution of a real machine 2, the identifier of the thread to be executed next is set in a register 18 and the break point discrimination circuit 17 corresponding to the thread is selected through a decoder 19. The break point of the thread is discriminated by means of the selected circuit 17. Therefore, the need of discriminating whether or not a broken thread is an aimed thread to be made whenever the execution is broken at break points is eliminated and the efficiency of the debugging work of this debugging device is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a debugging device, and particularly to a depacking device that sets independent breakpoints for each thread when a plurality of threads are executed in the same address space.

[Conventional technology]

Conventionally, in a debugging device connected to an actual device for debugging, a breakpoint determination circuit is used to determine whether or not an address at which a break should be made is reached based on the address signal and control signal of the actual device in order to stop the execution of the actual device. A method for comparing and determining an instruction fetch address obtained from an address signal and a control signal of an actual machine with a breakpoint address set in the debug device itself, and a select map in the debug device corresponding to the instruction fetch address. There is a method of determining based on memory output.

[Problem to be solved by the invention]

In the conventional method described above, when debugging threads running in the same address space, all breakpoints for the threads to be debugged are set in the debugging device, and the breakpoints are set as instruction fetch addresses on the address bus of the actual machine. An execution break operation occurs every time a point appears, and there is a problem in that a breakpoint cannot be set only at the target address of the target thread.

Therefore, the operator has to judge whether the thread whose execution has broken on the actual machine is the target thread or not, and if it is the target program, debug it, which has the disadvantage of poor work efficiency during debugging. Ta.

The present invention solves these conventional drawbacks, and its purpose is to improve the efficiency of debugging by making it possible to set independent breakpoints for each thread even in threads running in the same address space. There is a particular thing.

[Means to solve the problem]

A debugging device of the present invention is a debugging device that performs program debugging by extracting address signals, data signals, and control signals from a system bus of an actual machine or a read terminal of the processor, which is equipped with a processor and a program memory storing a control program for the processor. means for accumulating identifiers of threads being executed on the actual device; a breakpoint determination circuit that determines whether an address should be broken from an address signal and a control signal that are being executed on the actual device; and the breakpoint. The CPU 11 includes a circuit for selecting a determination circuit based on the value of a stack pointer, and is configured to perform a thread-independent break operation.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a debugging device according to the present invention, and is composed of a debugging device 1 and an actual device 2. In FIG.

The debug device 1 includes a processor 10 , a memory 11 , a display 2 , a keyboard 13 , a breakpoint determination circuit 17 , a register 18 that stores the identifier of the thread being executed, and the output of the register 18 is decoded and the breakpoint determination circuit 17 is selected. A decoder 19 is provided for

The actual device 2 includes a processor 201 and a program memory 21 in which a control program for the processor 20 is stored. The processor 20 and program memory 21 are connected to the registers 18 of the debug device 1 by an address bus 22, a data bus 23, and a control bus 24. Furthermore, the address bus 22 of the actual machine 2. The control bus 24 is the breakpoint determination circuit 17 of the depacking device 1.
It is connected to the.

The memory 11 of the debugging device 1 includes a program that controls the display 12 and keyboard 13 to set and cancel breakpoint addresses in the break/void determination circuit 17 corresponding to the thread to be set.

Next, the operation of the debugging device shown in FIG. 1 will be explained with reference to the flowchart shown in FIG. First, the program included in the memory 11 in the debugging device 1 is activated.

The program causes the thread identifier and address to be broken to be input from the keyboard 13, selects the break point determination circuit 17 from the thread identifier, and sets the break address using the same circuit.

Next, when a thread switching operation occurs in the execution state of the actual device 2, the control program included in the memory 21 performs the processing shown in FIG. That is, the control program saves the execution state of the previously executed thread in the memory 21 (step 31), and sets the identifier of the thread to be executed next in the register 18 (step 32). register 1
The decoder 19 decodes the thread identifier stored in 8 and selects the breakpoint determination circuit 17 corresponding to the program identifier (steps 33 and 34). Next, execution moves to the thread, and during execution of the thread, when the address set in the selected breakpoint determination circuit 17 appears at the time of instruction fetch, the breakpoint determination circuit outputs 1'', and the decoder 19 The logical sum with the output of is taken by AND gate 1-101 and OR gate 102
This causes the processor 20 of the actual device 2 to break, and also causes the processor 1 of the debug device 1 to detect the occurrence of the break.
0 and terminates the operation.

〔Effect of the invention〕

As explained above, according to the present invention, a breakpoint address is set in the breakpoint determination circuit corresponding to the thread to be broken for debugging, and the identifier of the thread to be executed next is set in the register when switching thread execution. Then, the breakpoint determination circuit corresponding to the thread is selected through the decoder, and the breakpoint determination circuit for the thread is determined by the selected breakpoint determination circuit, so that the target thread does not reach the target break address. Execution on the actual machine is broken only when it is reached.

Therefore, it is no longer necessary to judge whether the broken thread is the intended thread every time execution breaks at a breakpoint, as in the past, and debugging efficiency can be improved compared to conventional debugging equipment. This has the effect of significantly improving software productivity.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a flow chart showing thread identifier setting processing. DESCRIPTION OF SYMBOLS 1...Debug device, 2...Actual machine, 10...Processor, 11...Memory, 12...Display,
13...Keyboard, 17...Break point determination circuit, 18...Register, 19...Decoder.

Claims (1)

[Claims] A debugging device that performs program debugging by extracting address signals, data signals, and control signals from a system bus of an actual machine or a read terminal of the processor, which is equipped with a processor and a program memory storing a control program for the processor; means for accumulating identifiers of threads being executed; a breakpoint determination circuit for determining whether or not an address should be broken from the address signal and control signal being executed in the actual device; What is claimed is: 1. A debugging device comprising: a circuit for making a selection based on a thread, and performing a thread-independent break operation.