JPH0581068A - Debugging support device - Google Patents

Abstract

PURPOSE:To provide a debugging support device where plural supervisory points in debugging can be set without affecting debugging, hardware constitution is small and whose performance difference in processing speed in a debugging state and a non-debugging state is small. CONSTITUTION:A processor 1X1 adopting tag architecture is used. A breake bit 21iB interrupting the execution of an instruction is prepared in the tag of an instruction memory 21, and a watch bit 22jW interrupting a processing at the time of data access in the tag of a data memory 22. When the processor 1X1 accesses to a memory cell where the breake bit 21iB or the watch bit 22jW is set, an interruption drive means (1X2, 1X3 or 1X4 and 1X5) interrupts the processor 1X1 for starting a debugging processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debug support device for supporting a debugging system.

[0002]

2. Description of the Related Art Programs are often complicated and large due to the complexity of computer systems, diversification of information to be handled, diversification of usage forms of computer systems, expansion of users, etc. Is becoming indispensable (reference:
"Software-Oriented Architecture", Hajime Iizuka, Hidehiko Tanaka, 1985 (Ohmsha, pp205-216).

One of the important points in constructing a debugging system is to bring the debug state and the non-debug state as close as possible. Items that should be brought closer include, for example, the processing speed in the debug state and the non-debug state.

For example, when debugging a program, consider interrupting the execution of the program at a specified location and examining the contents of registers and memory. In this case, as a mechanism for assisting debugging, a method may be considered in which a mechanism is provided in which all instructions executed by the processor are interrupted before instruction execution, and program execution control and data access are monitored. However, in this method, during debugging, an interruption occurs each time an instruction is executed, and it is necessary to search each time whether this interruption is designated by the programmer for debugging, so the processing speed of the program is significantly reduced. To do.

Therefore, in order to make up for such a drawback, the following hardware mechanism for identifying the interruption point and interrupting it has already been proposed for debugging support.

(1) Mechanism Related to Program Execution Control A special register (hereinafter, referred to as a break point register) indicating an instruction execution interruption point (hereinafter, referred to as a break point) of the program is prepared inside or outside the processor to provide an instruction. Each time a fetch occurs, the address is compared with the contents of the breakpoint register, and if they match (the breakpoint is reached), execution is suspended.

(2) Mechanism for data access A special register (hereinafter, referred to as watchpoint register) indicating a monitoring point of data access (interruption point of memory operation instruction: hereinafter referred to as watchpoint) is provided inside or outside the processor. Every time a data access occurs, the address is prepared and the contents of the watchpoint register are compared, and if they match (when the watchpoint is accessed), the execution is interrupted.

[0008]

However, when a debugging system is constructed using the above-mentioned two debug support mechanisms, there are the following problems.

When a program with a large number of steps is targeted or a program which handles a large amount of data is targeted, it is necessary to specify a plurality of breakpoints or a plurality of watchpoints in order to make the debugging function effectively. Sometimes. In order to comply with this, a debugging system is constructed by implementing a plurality of breakpoint registers and a plurality of watchpoint registers. In general, the debugging system is general-purpose so that it can process a plurality of programs, and there is a limit even if a plurality of breakpoint registers and a plurality of watchpoint registers are mounted. Therefore, it may not be possible to specify all required breakpoints or watchpoints. In order to solve this, it is necessary to mount a large number of breakpoint registers and watchpoint registers, and the hardware becomes huge. When a register is provided inside the processor, it is often difficult to make it into one chip, and when it is provided outside, the entire device becomes large.

It is conceivable that such a plurality of breakpoints and a plurality of watchpoints may be searched by software by causing an exception (trap) each time an instruction fetch or data access is performed. In this way, there will be no problem when implemented by hardware. But,
In the case of this method, since the search processing is performed for each instruction fetch or data access, there is a problem that the performance difference in the processing speed between the debug state and the non-debug state becomes large. Further, when the target for constructing the debugging system is a parallel processor system, the operation itself of the program may change due to this overhead, which may hinder debugging.

The present invention has been made in consideration of the above points, and it is possible to set a plurality of monitoring points for debugging without affecting debug, and the hardware configuration is small and the debug state is small. An object of the present invention is to provide a debug support device capable of reducing the difference in performance between the non-debug state and the non-debug state.

[0012]

In order to solve such a problem, according to the first aspect of the present invention, in a processor system having at least one processor adopting a tag architecture, instruction execution is suspended during a tag of a memory cell. There is provided an instruction execution interruption bit for causing the processor to access the memory cell in which the instruction execution interruption bit is set, and an interrupt driving means for applying an interruption for starting the debugging processing is provided.

According to the second aspect of the present invention, in a processor system having at least one processor adopting a tag architecture, a memory operation interruption bit for interrupting a process when accessing a data memory is included in a tag of a memory cell. An interrupt driving means is provided, which is prepared and applies an interrupt for starting the debugging process to the processor which has accessed the memory cell in which the memory operation interruption bit is set.

[0014]

In the first aspect of the present invention, the instruction execution interruption bit for interrupting the instruction execution is prepared in the tag of the memory cell. Then, when the processor accesses the memory cell in which the instruction execution interruption bit is set, the interrupt driving means issues an interrupt to the processor to activate the debugging process.

Further, in the second aspect of the present invention, a memory operation interruption bit for interrupting the processing when accessing the data memory is prepared in the tag of the memory cell. Then, when the processor accesses the memory cell in which the memory operation interruption bit is set, the interrupt driving means issues an interrupt to the processor to activate the debugging process.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a parallel processor system will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of a parallel processor system to which this embodiment is directed.

In FIG. 2, the parallel processor system 1
Is a plurality of processor modules 11, 12, ..., 1n
And the shared memory module 20 are connected via the shared bus 30. Each processor module 11, 1
, 1n are respectively provided with processors 111, 121, ..., 1n1 adopting the tag architecture.
Accesses the shared memory module 20 as necessary. The shared memory module 20 includes an instruction memory 21 that stores an instruction group related to a program to be debugged.
And a data memory 22 storing a data group related to a program to be debugged.

In addition to the basic configuration of the parallel processor system 1 as described above, the following configuration and functions for debugging are provided. about this,
A description will be given also with reference to FIGS. 1 and 3.

One cell 21i of the instruction memory 21 has a tag section 21i1 and an instruction section 21i, as shown in FIG.
2, and a break bit 21iB indicating whether or not the instruction at the address is a breakpoint is prepared as one tag bit in the tag portion 21i1. In addition, one cell 22j of the data memory 22
3B, as shown in FIG. 3B, is composed of a tag section 22j1 and a data section 22j2. It is determined whether or not the data of the address is a watchpoint as one tag bit in the tag section 22j1. Watch bit 22jW shown
Is prepared. The instruction memory 21 of this embodiment is
Like the data memory 22, the tag information can be updated by a memory operation instruction (write processing or the like) from the processor.

Each processor module 1x (x is 1, 2, ..., N) is provided with a configuration for monitoring whether or not the break bit 21iB and the watch bit 22jW are significant.

As a monitoring configuration of the break bit 21iB, as shown in FIG. 1 (A), a NAND circuit 1x2 and a latch circuit 1x3 are provided. Latch circuit 1x3
Is for latching a break mode signal BPE indicating whether or not to generate an interrupt when a breakpoint is accessed. When the debugging process based on the break point is performed, the break mode signal BPE in the set state is latched. The NAND circuit 1x2 is
Break bit 21iB and break mode signal BPE
Is set, the interrupt signal INTREQ0 as a breakpoint is given to the processor 1x1.

As a monitoring configuration of the watch bit 22jW, as shown in FIG. 1B, a NAND circuit 1x4 and a latch circuit 1x5 are provided. Latch circuit 1x5
Is to latch a watch mode signal WPE indicating whether or not to generate an interrupt when a watch point is accessed. When performing the debugging process based on the watchpoint, the watch mode signal WPE in the set state is latched. The NAND circuit 1x4 is
Watch bit 22jW and watch mode signal WPE
When both are set, the interrupt signal INTREQ1 as a watchpoint is given to the processor 1x1.

The shared memory module 20 also stores a debugger (debugging program) 23. When the processor 1x1 is given the interrupt signal INTREQ0 as a breakpoint, the debugger 23
Of the debugger 23 is executed, and when the interrupt signal INTREQ1 as the watchpoint is given, the processing part of the debugger 23 for the watchpoint is executed.

The debugger 23 includes a bit operation processing portion that causes any or a predetermined processor to set or reset the break bit and the watch bit, and
Break mode signal BPE and watch mode signal WPE
A mode operation processing portion is provided for causing any or a predetermined processor to set or reset the above. That is, any or a predetermined processor "sets (resets) the break bit of the instruction memory cell" or "sets (resets) the watch bit of the data memory cell based on the bit manipulation processing portion of the debugger 23. The data operation instruction “” is given to the memory control circuit (not shown) of the shared memory module 20 to set (reset).

In the above construction, the operator first
The debugger 23 is used while using an input / output device (not shown) to set break bits and watch bits for predetermined instructions and predetermined data relating to the program to be debugged. After that, the operator sets the break mode signal BPE and the watch mode signal WPE using the debugger 23 while using an input / output device (not shown). Then, the program to be debugged is activated.

Here, it is assumed that a processor 1x1 gives an instruction address for accessing the instruction memory 21 to fetch an instruction to the shared memory module 20.
In this case, as shown in FIG. 1A, the instruction stored in the instruction memory cell at that address is given to the processor, and the break bit 21iB stored in the instruction memory cell is transferred to the NAND circuit 1x2. Given.

When the break bit 21iB is not set, the NAND circuit 1x2 to the processor 1x1.
Interrupt request signal INTREQ0 is not output to
Processor 1x1 executes the instruction without interruption.

On the other hand, when the break bit 21iB is set, the break mode signal BPE is set, so the NAND circuit 1x2 to the processor 1x.
The interrupt request signal INTREQ0 is output for 1
Before executing the instruction, the processor 1x1 interrupts the debugger 23 to execute the processing when the breakpoint is detected.

It is also assumed that a processor 1x1 gives a data address for accessing the data memory 22 and a memory operation instruction (write or read) to the shared memory module 20. In this case, as shown in FIG. 1B, the data stored in the data memory cell at the address is read out, or the data is written in the data memory cell at the address, and the data memory cell is also written in the data memory cell. The stored watch bit 22jW is given to the NAND circuit 1x4.

If the watch bit 22jW is not set, the NAND circuit 1x4 to the processor 1x1.
Interrupt request signal INTREQ1 is not output to
The processor 1x1 continuously executes processing according to the program to be debugged without interruption.

On the other hand, when the watch bit 22jW is set, the watch mode signal WPE is set, and therefore the NAND circuit 1x4 outputs the interrupt request signal INTREQ1 to the processor 1x1. The debugger 23 is interrupted to execute the processing when the watchpoint is detected.

Therefore, according to the above-described embodiment, since the tag architecture is adopted and the break bit and the watch bit for designating the break point and the watch point are provided in the tag, a plurality of break points and watch points are provided. Can be specified easily, and the hardware for monitoring the breakpoints and watchpoints need not be provided for each breakpoint or watchpoint, and can be made small.

Further, since the monitoring by software is not executed, no time is spent for the monitoring operation, and by not setting the break bit or the watch bit for the debug processing, it is possible to avoid the time during debugging. Further monitoring of debugging can be prevented, the processing speeds in the debug state and the non-debug state can be made approximately the same, and an efficient debugging system can be realized.

Further, since each point is set without using a register, the hardware configuration for monitoring each point is easily provided outside the processor as described above, and a plurality of processors are formed on the same chip. It becomes easier to do. In practice, it is considered to mount a plurality of processors forming a parallel processor system on the same chip, and in the case of the above-described embodiment, the configuration that supports debugging does not impose such a limitation on the same chip.

Incidentally, similar flags (break bit, watch bit) are adopted without adopting the tag architecture.
May be stored in the memory to execute the same processing, but the hardware configuration becomes complicated, or the software processing takes a lot of time, and the effects of the above-described embodiment cannot be obtained.

In the above embodiment, the hardware for monitoring each point is the processor module 1x.
Although the one provided on the side is shown, the shared memory module 20
It may be provided on the side. Further, instead of providing the monitoring hardware configuration for each processor in a one-to-one correspondence, the monitoring hardware configuration may be provided in common and its output may be given to each processor via the selector.

Further, in the above-mentioned embodiment, the one which supports the debugging system which performs the debugging processing at the break point and the debugging processing at the watch point is shown, but the debugging system which performs the debugging processing at any one of the points is shown. It can also assist the system.

Furthermore, in the above embodiment, the debugger 2 sets or resets the bit for each point.
Although the operation performed by using OS 3 is shown, it may be executed by using the OS.

Furthermore, the application system of the present invention is not limited to the parallel processor system, but can be applied to a system having only one processor.

[0041]

As described above, according to the present invention, the tag architecture is adopted and the instruction execution interruption bit for interrupting the instruction execution during the tag of the memory cell and / or the memory operation for interrupting the processing when accessing the data memory. Since the interrupt bit is prepared and the processor that accessed the memory cell in which the instruction execution interrupt bit or the memory operation interrupt bit is set is provided with the interrupt driving means for applying the interrupt for starting the debugging process, it may affect the debugging. Thus, it is possible to realize a debug support device capable of setting a plurality of monitoring points for debugging, and having a small hardware configuration and capable of reducing a difference in performance in processing speed between a debug state and a non-debug state.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of an embodiment.

FIG. 2 is a block diagram showing a parallel processor system to which an embodiment is applied.

FIG. 3 is an explanatory diagram showing a memory cell configuration of an example.

[Explanation of symbols]

1 ... Parallel processor system, 11-1n (1x) ... Processor module, 1x1, ... Processor, 1x2, 1
x4 ... NAND circuit, 1x3, 1x5 ... Latch circuit, 20
... shared memory module, 21 ... instruction memory, 21iB
... break bit, 22 ... data memory, 22jW ... watch bit, 23 ... debugger.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akira Yamamoto 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (2)

[Claims] 1. A processor system having at least one processor adopting a tag architecture, wherein an instruction execution interrupt bit for interrupting instruction execution is prepared in a tag of a memory cell, and the instruction execution interrupt bit is set. A debug support device comprising an interrupt driving means for applying an interrupt for starting a debugging process to a processor that has accessed a memory cell. 2. A processor system having at least one processor adopting a tag architecture, wherein a memory operation interrupt bit for interrupting processing when accessing a data memory is prepared in a tag of a memory cell, and the memory operation interrupt bit is provided. The debug support apparatus is provided with an interrupt driving means for applying an interrupt for starting a debugging process to a processor that has accessed the memory cell set in the above.