JPS59202546A - Debugging device - Google Patents

Abstract

PURPOSE:To attain the step execution of the high class language level by using a bit map memory storing a data of prescribed value to a bit corresponding to a head address of the high class language step. CONSTITUTION:Prior to the execution of a high class language symbolic step, a multiplexer 7 of a debugging device 1 is changed over so as to connect an address bus 14 of a processor 2 and an address input of the bit map memory 8 thereby bringing the state of the memory 8 into the write state. Further, a prescribed value (e.g., 1 to the head address and 0 to other addresses) of data is written into the memory 8 based on the head address table of each high class language step being output information from a compiler (not shown). Then, when the debugging operator requests for the execution of step from a keyboard 5, an output of an AND gate 12 goes to 1 only when an output of the memory 8 is at level 1 so as to break a processor 21 of an active machine 20.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a debugging device that is connected to an actual device including a processor and performs program debugging of the actual device, and in particular, relates to a debugging device that debugs a program of the actual device, especially when a control program written in a high-level language is used. This invention relates to a debugging device that enables step execution at a high-level language level when debugging.

(Background of the Invention) Conventionally, as a method of performing step execution at a high-level language level, a method is known in which, for example, machine code for special debugging is inserted and step execution is performed. However, with this method, there are inconveniences such as the need to debug a program different from the program actually used, and the need to give special instructions to the compiler as a debug object. .

(Object of the Invention) In view of the above-mentioned problems with the conventional system, an object of the present invention is to enable step execution at a high-level language level using a program actually used in a debugging device.

(Structure and Effects of the Invention) The present invention provides a debugging device having a break function that uses a bit map that stores data of a predetermined value in bits that correspond to the address space of the program memory of an actual machine and correspond to the start address of a high-level language step. This invention is based on the concept of enabling step execution at a high-level language level, that is, high-level symbolic step execution, by performing a break operation at each start address using memory. It is possible to debug the program machine code at a high-level language level. Furthermore, it is possible to perform step execution as a high-level language debugger, and at the same time, it is also possible to execute control programs in real-time mode.

(Explanation of Examples) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 schematically shows a debugging device according to an embodiment of the present invention. The debug device 1 in the figure is a processor (CPU)
2) 2. Memory 3, display 4 consisting of a numeric display or CTR, etc., keyboard 5, simulation interface circuit 6, multiplexer 7, bitmap memory 8, controller 1 to roll circuit 9, flip-flop 10
．． Breakcon 1 to roll circuit 11, and gate 12
etc. The actual machine 20 that executes the program to be debugged includes a processor+11CPU 1) 21 and a program memory 22 in which a control program for the processor 21 is stored. Processor 21 and memory 2
2 are connected to each other by a system bus including a control bus 23, an address bus 24, and a data bus 25. Real I! The 20 control buses 23, address buses 24, and data buses 25 are connected to the control bus 13, address bus 14, and data bus 15 of the debug device 1, respectively, via the emulation interface circuit 6 of the debug device 1.

Further, the address bus 24 of the real m20 is connected to the multiplexer 7 of the debug device 1.

The bitmap memory 8 is a memory whose number of bits corresponds to the address bus of the program memory 22 of the actual machine 20. For example, if the program memory 22 has a capacity of 64 bytes, the map memory 8 has a number of bits corresponding to 64 bytes. It has a capacity of

The multiplexer 7 actually selects one of the 20 address buses 24 and the address bus 14 of the debug device 1.
This is for switching connection to the address input of the hemap memory 8.

Next, the operation of the debugging device shown in FIG. 1 will be explained with reference to the flowchart shown in FIG.

In the circuit shown in FIG. 1, the multiplexer 7 of the debugging device 1 is
switches to connect the address bus 14 of the processor 2 with the address input of the bitmap memory 8, and also applies a write signal W to the bitmap memory 8 from the control circuit 9 to put the bitmap memory 8 into a write state. .

Then, based on the start address table of each high-level language step, which is output information from a compiler (not shown), the bitmap memory 8 receives an address corresponding to this start address from the address bus 14 of the processor 2 and the data passcode 5. Write data of predetermined value. As the predetermined value data, for example, 111 I+ is written to the address corresponding to the start address. Furthermore, 110 I+ is written to other addresses.

In this way, after predetermined data values have been written to the pin 1-map memory 8 for all the start addresses of the high-level language steps, the debug operator issues a step execution request to the program to be debugged via the keyboard 5 or the like. When this is done, the high-level language sympolink step execution of the actual machine 20 is performed as follows. That is, processor 2
interrupts the write signal, puts the bitmap memory 8 in the read state, and connects the multiplexer 7 to the address bus 2 of the real 1120.
4 and the address input of the bitmap memory 8 are connected, and the flip-flop 10 is set via the control circuit 9 to switch the debugging device 1 to step execution mode, and then the break control is performed via the control circuit 9. The run signal of the actual 120 processors 21 is sent to the circuit 11. This allows processor 2
1 receives a run signal from the break controller 1 to the roll circuit 11 and executes the program of the actual machine 20.

At this time, the program memory 22 is accessed from the processor 21 of the actual machine 20 and instructions are executed.
The address data input to the address data is applied to the address input of the hit map memory 8 via the multiplexer 7.

Therefore, the p1 hemmap memory 8 is accessed by the same address as the address of the program memory 22 accessed in the embodiment 20, and its read output is applied to one input of the AND gate 12 via the output terminal 0tJT. The output of the flip-flop 10 is applied to the other input of the AND gate 12. Since this flip-flop 10 is set when a step execution request is made, the output of the bitmap memory 8 is applied to the high-level language step. In other words, when the position indicating the first address of ``1'' is level, the output of the AND gate 12 is ``level''.
As a result, the break controller 1 to the roll circuit 11 break the processor 21 of the actual device 20 and notify the processor 2 of the debugging device 1 of the occurrence of the break. , FJ''C, the flip-flop 10 is reset to its initial state, and a series of high-level language symbolic step execution operations are completed.

Note that if the debug device 1 is not set to step execution mode 1~, the flip-flop 10 is reset when the processor 21 of the actual device 20 is instructed to run, so a break occurs in the above procedure. didn't happen,
Therefore, the program to be debugged can be executed by a real-time mote.

In the above-described embodiment, a compiler separate from the debugging device is used, but the debugging device may also have a compiler (inclined).

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a general configuration of a debugging device according to an embodiment of the present invention, and FIG. 2 is a flowchart for explaining the operation of the debugging device shown in FIG. 1. 1...Debug device, 2...Processor, 8...
・Bitmap memory, 11...Break control circuit, 13.23...Control bus, 14.2
4...address bus, 15.25...data bus,
2o... Actual machine, 21... Processor, 22... Program memory. Patent applicant Tateishi Electric Co., Ltd. Agent Patent attorney Tatsuo Ito Agent Patent attorney Tetsuya Ito

Claims (1)

[Claims] 1. Retrieving address signals, data signals, and control signals from a system bus or a read terminal of the processor of an actual machine that includes a processor and a program memory that stores a control program for the processor created and compiled in a high-level language. A debug device for debugging a program, the debug device comprising:
A bitmap memory is provided in which predetermined value data is stored in bits corresponding to the address space of the program memory and corresponding to the start address of each high-level language step, and the program memory is accessed by operating the actual machine. A debugging device characterized in that the bitmap memory is accessed according to a memory address accessed at the time, and a break operation is performed when data of the predetermined value is read from the bitmap memory, thereby performing high-level language symbolic step execution. .