JPS59202547A - Debugging device - Google Patents

Abstract

PURPOSE:To set the optional number of desired conditional breaks by preserving a brake conditional setting table. CONSTITUTION:A multiplexer 7 of a debugging device 1 connects an address bus 16 of a processor 2 and an address input of a selection map memory 8 to bring this memory into the write state. Then, 16 kinds of stop conditions where the numbers of 0-15 are assigned as addresses are set to a break generation condition setting table memory BTM9. Then, the processor 2 interrupts the write signal of a control circuit 12 to bring the selection map memory 8 into the reading state, and also transmits a run signal of a processor 21 of an active machine 20 to a break control circuit 11 to control the execution of the program of the active machine 20. Further, the break generation conditional data is read from the BTM9 by using an identical address to the address of the program memory 22 to transmit the data to a comparison circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a debugging device that is connected to a device having a processor, that is, an actual device, and performs program debugging of the actual device, and in particular, the present invention relates to a debugging device that is connected to a device having a processor, that is, a real device, and performs program debugging of the real device, and particularly, In addition to generating a break using hardware, multiple condition settings are patterned, and all of the patterns are released and used at each address in the program memory, and the conditions are compared using a single comparison mechanism. Regarding debugging equipment.

(Background of the Invention) In most debugging devices, the means used to stop certain operations is based solely on matching addresses. However, there is a request from the operating side to perform a break based on conditions such as data matching or write mode, in addition to address matching. In this case, conventionally, after stopping the actual machine, the data is examined using software or a dedicated hardware device is installed, but breaks occur at unnecessary times, or the dedicated hardware Because of the equipment, there was also a limit on the number of breakpoints and break conditions.

(Object of the Invention) In view of the above-mentioned problems with the conventional type, an object of the present invention is to provide a debugging device that can set a desired conditional break on any side.

(Structure and Effects of the Invention) The present invention provides a debugging device having a break function, in which a select map memory is provided which stores break condition setting data corresponding to the address space of the program memory of an actual machine and corresponding to each address of the program memory. This is based on the concept of using a break condition setting table memory that is addressed by this select map memory output and outputs a break condition.According to the present invention, even a break with a condition is a break only when necessary. The number of breaks can be greatly reduced, allowing the actual vehicle to run in a manner close to real time.

Additionally, there is no limit to the number of conditional breaks that can be set.

(Explanation of Examples) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 schematically shows a debugging device according to an embodiment of the present invention. The debug device 1 in the same figure is a program
tJ2) 2, memory 4, display 5 consisting of a numeric display or CTR, etc., keyboard 6, emulation interface circuit 6, multiplexer 7, select map memory (SMM) 8, break generation condition setting table memory (BTM) 9, a comparison circuit 10, a break control circuit 11, a controller 1 to a roll circuit 12, gate circuits 13 and 14, and the like. The actual machine 20 that executes the program to be debugged is a processor (CPU 1)
21 and a program memory 22 in which a control program for the processor 210 is stored.

Processor 21 and memory 22 are connected to control bus 23
, an address bus 24 and a data bus 25. The address bus 24 of the real device 20 is connected to the multiplexer 7 of the debug device 1. Further, the control bus 23 and data bus 25 of the actual device 20 are connected to the comparison circuit 10.

The select map memory 8 has a number of bytes corresponding to the address space of the real program memory 22 and BTIVj.
For example, the program memory 22 has 64 bytes and 8 bytes.
If the 7M9 has a capacity that allows setting of 4 bits, that is, 16 break conditions, the select map memory will be 6.
4 has a capacity of 4 bits. In addition, 5MM
8 and 87M9 are random access memories (
RAM). Multiplexer 7 is
This is for switching and connecting either the address bus 24 of the real 120 or the address bus 16 of the debugging device 1 to the address input of the select 1-map memory 8.

Next, the operation of the debugging device shown in FIG. 1 will be explained with reference to the flowchart shown in FIG.

In the circuit of FIG. 1, first, the control circuit 12
The multiplexer 7 of the debugging device 1 connects the address bus 16 of the processor 2 and the address input of the select map memory 8 via the gate circuit 1.
3.14 is brought into conduction, and Aa-senmyo Do~D3 and DO~Q15 of 5MM8 and 87M9 are respectively connected to the data bus 17 of the debugging device 1, and a write signal W is applied to the select map memory 8. Set the select map memory 8 to the write state, and then
Set six types of stop conditions to 87M9.

These stop conditions are assigned numbers 0 to 15 as addresses, and these values are assigned to 4 bits of 5MM8 (0 to 15).
15) for all addresses. All of these operations are performed at the request of the debug operator. Thereafter, the processor 2 interrupts the write signal of the control circuit 12 to put the select map memory 8 in the read state, and the multiplexer 7
After setting the address bus 24 of the actual machine 20 and the address input of the select 1-map memory 8 to be connected, and making the circuits 1 to 13 and 14 non-conductive, the break control circuit 11 is connected to the actual 1 processor 21
Sends a run signal. This causes the processor 1
is given a rerun signal from the break controller 1 to the roll circuit 11 and executes the program of actual state 20.

At this time, the program memory 22 is accessed from the processor 21 of the actual machine 20 to execute instructions, but the address data input from the processor 21 to the memory 22 via the address bus 24 is transferred via the multiplexer 7 to the select map memory. 8 address inputs. Therefore, the select map memory 8 is stored in the actual machine 20.
The program memory 22 is accessed by the same address as the address accessed in the program memory 22, and its read output is applied to the address input of the BTM 9 via the M child DO-D3. As a result, 16-bit break generation condition data is read from the BTM 9, and this data is applied to the comparison circuit 10. The comparison circuit 10 compares the 16-bit (-) data output from the BTM 9 with the 16-bit data appearing on the control bus 23 and the data bus 25, and if they match, generates an output "1". 11 causes the processor 21 of the actual device 20 to break and notifies the processor 2 of the debugging device 1 of the occurrence of the break, thereby ending the -C1 operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a general configuration of a debugging device according to an embodiment of the present invention, and FIG. 2 is a schematic diagram for explaining the operation of the debugging device shown in FIG. 1...Debug device, 2...Procera 1), 8...
・Select map memory, 9...BTM, 10...
Comparison circuit, 11... Break control circuit, 23
...Control bus, 24...Address bus, 2
5...Data bus, 20...Actual machine, 21...Processor, 22...Program memory.

Claims (1)

[Claims] 1. Program debugging is performed by extracting the 71 heres signal, data signal, and control signal from the system bus or the lead terminal of the processor of an actual machine that is equipped with a processor 1 and a program memory that stores the control program of the processor. A debugging device, the debugging device includes a break generation condition setting table memory in which a plurality of break generation conditions are set, and a predetermined break generation condition selection corresponding to an address at which a break should occur in the actual processor frame. The select map memory that stores the data and the output data of the select map memory from the break occurrence condition setting table memory are displayed as 71~res and the break occurrence conditions read out and the data bus and control bus of the actual machine. 1. A debugging device comprising: a comparison circuit that detects a match with data that is displayed, and performs a break operation when the comparison circuit detects a match.