JPH02163842A - Program evaluating device for microcomputer - Google Patents

Abstract

PURPOSE:To simplify a debugging program to be set into a control computer by stopping temporarily the working of an evaluating microcomputer with the coincidence detecting output of a coincidence detecting circuit and carrying out the program evaluation. CONSTITUTION:An error code is previously stored in each address of an error code memory 4 in response to each address of a program memory 3. Thus the working of an evaluating microcomputer 1 is surely stopped temporarily only when the computer 1 has malfunction. Then a control computer 5 is actuated based on an error code received from the memory 4 and the error process data received from the computer 1. Then the computer 5 debugs automatically the program of the memory 3 and evaluates the memory. Thus it is possible to simplify a debugging program to be set into the computer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a program evaluation device for a microcomputer.

(B) Prior Art A case will be described in which conventionally, a program evaluation has been performed using an evaluation microcomputer having substantially the same functions as a one-chip microcomputer for mass production. First, when a predetermined address in the external program memory is accessed by the program counter built into the evaluation microcomputer, the program data stored in advance at the predetermined address in the program memory is read into the evaluation microcombicoater. Therefore, the internal circuit of the evaluation microcomputer operates based on the program data.

Here, a control circuit is provided for the evaluation microcomputer. That is, the control circuit is preset with address data of a predetermined address of the program memory at which the program is to be evaluated, and the address data of the program counter inside the evaluation microcomputer is preset in the control circuit. It is designed to be applied together with the Therefore, when the address data from the evaluation microcomputer is fully applied to the control circuit and the address data matches the predetermined data in the control circuit, a temporary stop signal is generated from the control circuit, which causes the time to stop. The signal causes the operation of the evaluation microcomputer to be temporarily stopped. At this time, program evaluation is performed by analyzing whether data obtained from the evaluation microcomputer is normal data corresponding to regular program data.

(c) Problems to be Solved by the Invention However, in the above-mentioned conventional technology, when evaluating a program, the program developer must analyze the data obtained from the evaluation microcomputer in a stopped state, debug the program, etc. , the program has to be executed while remembering the program contents in the program memory, and therefore there is a problem in that it takes a lot of time to analyze the data and debug the program.

(d) Means for Solving the Problems The present invention provides a program memory in which program data is stored, a control computer that writes/reads program data to/from a predetermined address of the program memory, and a control computer that writes/reads program data to/from a predetermined address of the program memory. an evaluation microcomputer that includes a built-in program counter for accessing addresses and operates by reading program data from a predetermined address of the program memory, and when the predetermined address of the program memory is accessed, In a microcomputer program evaluation device that evaluates a program by temporarily halting the operation of a computer, the evaluation device has an address corresponding to each address of the program memory, and the evaluation that must not occur in a program at a predetermined address of the program memory. an error code memory in which the error state of the evaluation microcombicoater is written as an error code by the control computer to an address corresponding to a predetermined address of the program memory; Stable data from the evaluation microcombicoater and an error code from the error code memory obtained when respective corresponding addresses of the memory are accessed simultaneously are applied, and a match between the status data and the error code is determined. and a coincidence detection circuit for detecting a coincidence, and according to the coincidence detection output from the coincidence detection circuit, the operation of the evaluation microcomputer is temporarily stopped and program evaluation is performed.

(1) The present invention is effective as follows when installed in a program evaluation device for a microcomputer. 6. In the configuration described in item (d) above, program data is written by the control computer to a predetermined address of the program memory, and An error hood is written and raised by the control computer at a predetermined address in the error code memory that corresponds to a predetermined address in the program memory. An error state of the evaluation microcomputer that should not occur in the program is stored as an error code.Then, the program counter inside the evaluation microcomputer stores the same address in the program memory and the error hood memory, respectively. When access is completed, the evaluation microcomputer operates based on the program data, and also reads the error code read from the error code memory and the status data output from the evaluation microcomputer (data loaded into the accumulator, etc.). Carry flags, etc.) are compared by the match detection circuit.When a match detection output is obtained from the match detection circuit based on the error code and status data, the operation of the evaluation microcomputer is temporarily stopped by the match detection output. Therefore, the error code at this time and the data from the evaluation microcombicoater are marked 71Llk on the control computer, and the program is automatically debugged by the control computer output.

(f) Example The details of the present invention will be specifically explained with reference to illustrated embodiments.

The drawing is a block diagram showing a microcomputer program evaluation device according to the present invention. Regarding the drawings, to explain the symbols and configuration, (1) is an evaluation chip (evaluation microcomputer), and the evaluation chip (1) has approximately the same functions as a mass-produced one-chip microcomputer. Furthermore, the evaluation chip (1) has a built-in break circuit (2) for temporarily stopping the operation of the evaluation chip (1). (3) is a program memory, and in the program memory (3), program data in units of 8 bits for controlling the operation of the evaluation chip (1) is stored at each address. . (4
) is an error code memory, and the error code memory (4) has addresses corresponding to each address of the program memory (3). The addresses of the error code memory (4) corresponding to each address of the program memory (3) contain the evaluation chip (1) that must not occur in the program at that address of the program memory (3). ) is stored as an 8-bit error code.0 For example, if the program data at a predetermined address in the program memory (3) is a table reference instruction, the table reference instruction Since table data is loaded into an accumulator (not shown) inside the variation chip (1), the table data must be ASCII codes such as numbers or alphabets. That is, if the table data becomes ASCII data other than numbers or alphabets, an error will occur in the evaluation chip (1).

Therefore, the table data will be an ASCII code other than numbers or alphabets, that is, the table data will be 30
H or less or 7FH or more means that the evaluation chip (1) is in an error state. Therefore, the corresponding address of the error code memory (4) corresponding to a predetermined address of the program memory (3) is as follows.
An error code obtained by converting the error state of the above-mentioned evaluation chip (1) into an 8-bit code is stored.

(5) is a controller computer, the control computer (5) performs various controls as described below, (6) is an address switch, and (7) is a data switch; 6) and the data switch (7)
) is internally switched by the control computer (5).
It is controlled by. (8) is a coincidence detection circuit, and the coincidence detection circuit (8) receives an 8-bit status obtained from the evaluation chip (1) which is operating with a program at a predetermined address in the program memory (3). data and the program memory (3
) corresponding to the predetermined address of the error hood memory (
4) and the 8-bit error code at the corresponding address are applied. And the evaluation chip (1
), the coincidence detection outputs of the coincidence detection circuits (8> to 11) are obtained, and the coincidence detection outputs are c.
It is applied to the break circuit (2) through the 3R gate (9), and the operation of the evaluation chip (1) is temporarily stopped. (10) is a control circuit, and 16-bit address data of a predetermined address of the program memory (3) at which program evaluation is desired is preset in the control circuit (10). In particular, the error code memory (10) does not store any error codes.
It is assumed that the address data of the remaining addresses in 4) are stored. And the evaluation chip (1
) The address data is incremented by an internal program counter (not shown) and applied to the control circuit (10), and when the address data by the program counter and the address data preset in the control circuit (10) match. , a coincidence output of "1" is obtained from the control circuit (10),
The coincidence output is applied to the break circuit (2) via the OR gate (9), and the operation of the evaluation chip (1) is temporarily stopped in the same way as described above. This operation is the same as the conventional one. It is assumed that the address bus between each structure shown in the drawing is 16 bits, and the data bus is 8 bits.

The operation of the drawings will be explained below.

First, program memory (3
), and further write an error code to the error code memory 4), control the address switch (6) and data switch (7) by operating the controller computer (5). . That is, the address switch (6) selects the 16-bit address data generated from the vehicle control computer (5), and the data switch (7) selects the 8-bit program data generated from the vehicle computer (5). and error hood are selected.Then, address data generated from the control computer (5) is applied to the program memory (3) and the error hood memory (4) via the address switch (6), When each corresponding address in the program memory (3> and error code memory (4)) is accessed, the program data generated from the control computer (5>) is transferred to the program memory (3) via the data switch (7). The error hood (a code indicating an error state in the program data) generated from the controller computer (5) is then written to the accessed address of the program memory (3) via the data switch (7). Error code memory (4) corresponding to
will be written to the corresponding address. By repeating this operation, writing of data to the program memory (3) and error hood memory (4) is completed. By operating the control computer (5), each data written in the corresponding addresses of the program memo J (3) and the error code memory (4) is read out and applied to the control computer (5), and the program is read out. It is also possible to check the contents of both the memory (3) and the error code memory (4). .

Next, when operating the evaluation chip (1) based on the program data stored in the program memory (3), the control computer (5) is operated and the address switch (6) and data switch (7) are operated. ) is controlled so that the address data generated from the program counter inside the evaluation chip (1) and the input/output data in the evaluation depth (1) are respectively selected. Then, the address data is sequentially incremented by the program counter inside the evaluation chip (1), and this address data is transferred to the program data (
3) and the error code memory (4), and when the corresponding addresses of both the program memory (3) and the error code memory (4) are accessed, the signal is written to the specified address of the program memory (3). The program data that has been stored is applied to the evaluation chip (1) via the data switch (7), and the evaluation chip (1) operates based on the program data, and the 8-bit data obtained at this time is status data will be applied to the coincidence detection circuit (8). On the other hand, the error code written in the corresponding address of the error code memory (4) corresponding to the specified address of the program memory (3) is applied to the coincidence detection circuit (8), and a coincidence with the status data is detected. will be carried out.

When the evaluation chip (1) operates normally, no coincidence detection output is obtained from the coincidence detection circuit (8).
Therefore, the evaluation chip (1) reads Jl, I! without stopping at -. Then it will work. However, when status data indicating an abnormality in the evaluation chip (1) is obtained, the status data and error code are applied to the coincidence detection circuit (8), and a coincidence detection output of "rl" is obtained. The match detection output activates the break circuit (2), which forces the operation of the evaluation chip (1) to be temporarily stopped. At this time, the erroneous processing data obtained from the evaluation chip (1) which is in the stopped state and the error code from the error code memory (4) are transferred via the data switch (7) to the controller. The control computer (5) controls the address switch (6) and data switch (7), and the evaluation chip (
Program memory that caused the operation in 1) to be in an error state (3)
The program will be debugged by a program set inside the control computer (5).

From the above, one to one for each address of program memory (3)
If an error code is stored in each address of the corresponding error code memory (4), the operation of the evaluation chip (1) will be performed only when the evaluation chip (1) makes an error operation. can be reliably paused. Based on the error hood from the error code memory (4) and the incorrect processing data from the evaluation chip (1), the control computer <5>
The control computer (5) can automatically debug the program in the memory (3). Therefore, the debugging program that must be installed in the control computer (5) is simpler than before, and the above-mentioned operation allows the program developer to execute the program while recalling the program contents in the program memory as in the past. The troublesome effort of analyzing data obtained from the variation chip (1) and debugging the program in the program memory (3) can be omitted, and the time required to debug the program can be significantly shortened.

(G) Effects of the Invention According to the present invention, if an error code is allowed to be stored in each address of the error hood memory that corresponds one-to-one to each address of the program memory, when the evaluation microcomputer performs an erroneous operation, Only then can the operation of the evaluation microcomputer be reliably stopped. Then, the control computer is operated based on the error hood from the error hood memory and the erroneous processing data from the evaluation microcomputer, and the control computer automatically debugs the corresponding program in the program memory and evaluates the program. Can be done. Therefore, the debugging program that must be built into the control combinator is simpler than before, and the above-mentioned operation allows the program developer to write the evaluation microcomputer while recalling the program contents as in the past. analysis of data obtained from
Also, the troublesome effort of debugging the program memory can be omitted, and the time required for debugging the program can be significantly shortened.

[Brief explanation of the drawing]

The drawing is a block diagram showing a microcomputer program evaluation device according to the present invention. (1)...Evaluation chip, (3)...
Program memory, (4)...Error code memory,
(5)...Control computer, (8)...
...Coincidence detection circuit.

Claims (2)

[Claims] (1) It has a built-in program memory in which program data is stored, a control computer that writes/reads program data to/from predetermined addresses of the program memory, and a program counter that accesses predetermined addresses of the program memory; and an evaluation microcomputer that operates by reading program data from a predetermined address in a program memory, and when the predetermined address in the program memory is accessed, the operation of the evaluation microcomputer is temporarily stopped to evaluate the program. In the microcomputer program evaluation device, the evaluation microcomputer has an address corresponding to each address of the program memory, and an error state of the evaluation microcomputer that must not occur in a program at a predetermined address of the program memory is an error state of the program memory. An error code memory written as an error code by the control computer to an address corresponding to a predetermined address, and an error code obtained when each corresponding address of the program memory and the error code memory are simultaneously accessed by the evaluation microcomputer. a coincidence detection circuit to which the status data from the evaluation microcomputer and the error code from the error code memory are applied, and which detects coincidence between the status data and the error code; A program evaluation device for a microcomputer, characterized in that the operation of the evaluation microcomputer is temporarily stopped based on a detection output, and a program evaluation is performed. (2) Data from the evaluation microcomputer based on the program data obtained when each corresponding address of the program memory and the error code memory are simultaneously accessed by a program counter inside the evaluation microcomputer; Applying an error code from the error code memory to the control computer and debugging the program in the program memory by the control computer based on the error code when a coincidence detection output is obtained from the coincidence detection circuit. Claim (1) characterized by
The described microcomputer program evaluation device.