JPH03214328A - Memory testing system - Google Patents

Abstract

PURPOSE:To shorten the test time by reading write data to a read register immediately after write, comparing it with a write register in which the write data is held and testing the normalness of a memory by coincidence or uncoincidence. CONSTITUTION:A test control circuit 8 instructs read of write data in the next cycle immediately after write, reads the data read by the instruction and stores it in a register 9. The contens of this read register 9 and a write register 6 in which the write data is held are compared by a comparator 10, and coinci dence or uncoincidence is outputte. As a result, when the uncoincidence is detected, for instance, an alarm is generated, a test is executed newly by a test program, or a memory address, etc., of the coincidence or uncoincidence are recored. In such a way, the memory test can be executed by a regular operation, and the test time at the time of periodical maintenance is shortened.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a memory test method, and the present invention is a memory test method that tests the normality of a memory in which data is written via a write register, with the aim of shortening the test time. A test control circuit that instructs to read the data immediately after writing the data, a read register that stores the data read by the instruction, and a comparison that compares the contents of the write register and the read register. The write data is read into the read register immediately after the write data is written, and compared with the write register in which the write data is held to test the normality of the memory based on a match or mismatch.

[Industrial application field] The present invention relates to improvements in memory testing methods.

In recent years, the capacity of memories in electronic devices has significantly increased due to falling prices, and the execution time of test programs that test the normality of the memory has been increasing. For this reason, it has become difficult to complete all tests within the time allotted for regular maintenance, and a memory test method that shortens test time is required.

[Prior Art and Problems to be Solved by the Invention] Conventionally, in order to confirm the normality of a memory, a test is performed from outside the electronic device using a test program (operated by an external processor), or the memory to be tested is tested using a test program (operated by an external processor). The method used is to run a test program on top of the computer.

In recent years, memory capacity has increased significantly due to architectural expansion and price reduction, and the execution time of a memory test program has increased in proportion to the memory capacity.

On the other hand, although the architecture of electronic devices is becoming more complex and the time taken to confirm the entire system is increasing, the allowable time for confirmation provided by users is decreasing year by year. As a result, it is becoming increasingly difficult to complete the execution of test programs for confirmation, including memory tests, within regular maintenance hours at the user's site.

In view of the above problems, it is an object of the present invention to provide a memory test method that shortens test time.

[Means to solve the problem]

In order to achieve the above object, the memory test method of the present invention uses a test control circuit 8 that instructs to read data immediately after writing the data, as shown in the block diagram of FIG.
A read register 9 stores data read according to the instruction, and a comparator 10 compares the contents of the write register 6 and the read register 9.

[For production]

The test l-control circuit 8 instructs to read the write data in the next cycle immediately after writing, and stores the data read in response to the instruction in the read register 9.

The contents of the read register 9 and the write register 6 holding the write data are compared by a comparator 10, and a match/mismatch is outputted.

When a mismatch is detected, for example, an alarm is generated and a new test is performed using a test program, or memory addresses and the like are recorded for each match/mismatch.

As described above, the test control circuit 8, read register 9,
By providing hardware such as the comparator 10,
Memory self-check can be performed during normal operation, and memory testing using a test program can be omitted. Therefore, even if the memory capacity increases, all tests can be executed within the allowable time.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment, and FIG. 2 is a time chart. In FIG. 1, reference numeral 1 denotes a processor, which reads/writes the memory 4 according to instructions from a program.

Reference numeral 2 denotes an address buffer, which holds address data output from the processor 1 at least until the next read/write cycle.

3 is an address decoder, 4 is the memory to be tested, and 5 is an output resistor, which reads the output of Prosensor 1 (
R) The data read out from the memory 4 by the signal is stored,
Read by processor 1.

6 is a write register, which receives the write (1) signal. The write data 20 output from the processor 1 together with the write address is held at least until the end of the next read/write cycle.

7 is a read/write control circuit, based on the W/R signal,
Performs read/write control of the memory 4.

A test control circuit 8 instructs the read/write control circuit 7 to read the same address in the next cycle (hereinafter referred to as test read) when one signal is detected.

9 is a read register in which test read data is set by the test control circuit 8;

A comparator 10 compares the contents of the write register 6 with the contents of the write register 9 and outputs a match/mismatch signal.

11 is a gate.

In the above configuration, the following memory self-check is performed.

(1) The processor I accesses the memory 4 according to a program not shown.

The read/write control circuit 7 outputs the control signal and the output of the address decoder 3 to the memory 4 in a predetermined sequence according to the W/R signal, and outputs the output of the write register 6 at the time of writing.
The data written in the memory 4 is written, and the data written in the memory 4 is outputted to the output register 5 during reading.

(2) When the enemy signal is output, the test control circuit 8
The read/write control circuit 7 detects this and issues a read instruction.
Output to.

Thereby, the read/write control circuit 7 performs read control in the next cycle immediately after writing.

At this time, the address huffer 2 holds the previous write address, and therefore data at the same address as the write address is read.

In this read cycle, the test control circuit 8 loads the data output from the memory 4 into the read register 9, and closes the gate 11 to prevent the data from being outputted. In addition, the access prohibition signal is also
is output to.

(3) As described above, the comparator 10 compares the contents of the write register 6, that is, the write data 20, and the contents of the read register 9, that is, the test-read read data 21, and outputs a match/mismatch signal.

As described above, self-checking of the memory 4 is automatically performed when writing data, loading a program, etc. in normal business operations.

It should be noted that the check result may be logged, for example, atres with one loss or no match, or an alarm may be generated when there is no loss.

〔Effect of the invention〕

As explained above, the present invention provides a memory test method that includes hardware that reads the same address immediately after writing and compares it with the written data, and since the memory test can be performed during normal operation, periodic maintenance This has the effect of shortening test time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment, and FIG. 2 is a time chart. In the figure, 1 is a pro sensor, 2 is an address Hanofa, 3 is an address decoder, 4 is a memory, 5 is an output register, 6 is a write resistor, 7 is a write/read control circuit, 8 is a test control circuit, and 9 is a read register. , 10 is a comparator, 1
1 is the gate, 20 is the write decoder.

Claims (1)

[Claims] A memory test method for testing the normality of a memory (4) into which data is written via a write register (6), the test control instructing to read the data immediately after writing the data. a circuit (8), a read register (9) that stores data read out according to the instruction, and a read register (9) that stores the contents of the write register (6) and the read register (9).
) is provided, reads the write data into the read register immediately after writing, compares it with the write register in which the write data is held, and if there is a match or mismatch, the memory (4) A memory test method characterized by testing the normality of.